Hello, and welcome to our in-depth look at communications with precision data converters. In this video, we describe digital communications and the basics of Serial Peripheral Interface, or SPI communication. We'll discuss the communication structure and the required digital lines, then we'll show different modes of SPI communication, and finally give an example of how SPI data is transmitted to and received by a peripheral device. 

Many precision analog devices have a digital interface between a microcontroller, known as a controller, and a controlled device, known as a peripheral. Using precision ADCs as an example, the peripheral ADC measures an input voltage, and the controller microcontroller reads the data through digital communications. With precision DACs as the second example, the controller microcontroller writes a digital word to the DAC to set an output voltage. In both types of devices, this communication may be bidirectional. 

Many precision data converters may require some configuration and programming. Digital communications are needed to write to and read from the device. For there to be communication between the two devices, a common standard is required so that both the controller and peripheral understand each other. 

Communications are made with transmissions of words in binary notation. These communication bits of 1s and 0s are often organized in groups of eight, known as a byte. For convenience, bytes can be organized into two digital hexadecimal numbers. Often, several bytes are used to send data back and forth between the microcontroller controller and peripheral device. Multiple bytes may be used to represent the output data for ADCs, output voltages for DACs, or to send commands and configurations to the data converter. 

Digital communications can take many forms, but there are two primary structures that are often used. First, the communications can be parallel where one line is used for each bit of data. For example, a single byte is transmitted over eight parallel digital lines at once. Second, the communications can be serial where all the data bits are on a single digital line. In a serial communication, bits are sent serially, one after another. 

Serial communications are more widely used in modern devices, reducing the number of communication lines between the controller and to the peripheral device. The figures here show the data going from the controller to the peripheral, but separate lines are required for transmitting data from the peripheral back to the controller. For precision data converters, most use forms of serial communication. 

Most TI devices use one of two different serial interface standards, using either 4-wire serial peripheral interface or a 2-wire I2C. This presentation discusses SPI in its implementation. I2C is discussed in a different presentation. 

The lines between the controller and the peripheral device are driven to one of two voltage levels. If the voltage is near 0, then the line is decoded as a digital 0. If the voltage is near the digital supply, then the line is decoded as a digital 1. Note that both the controller and the peripheral need to agree what these levels are so that the communication is decoded correctly. Digital outputs must be driven high enough to be decoded as a digital 1 and driven low enough to be decoded as a digital 0. 

The data sheet defines the minimum output voltage high level and the maximum output voltage for a low level for a digital output. Additionally, the data sheet defines the minimum input voltage that defines a high level and the maximum input voltage that defines a low level. Their communication standards define these levels based on the voltage of the digital supply. If the controller and peripheral digital supplies do not match, then there may be problems with communications. A voltage level translation device may be required to bridge the communications from one supply level to another. 

Communications also require a common timing between the controller and to the peripheral device. The two devices must agree on the timing, knowing when the voltage level should be read by the peripheral device to define when the bit transmission occurs. Often, a serial clock from the controller is used to define the timing of communication. Reading the bit may occur on the rising or falling edges of the serial clock. In this example, the data is read on the falling edge of the serial clock. Timing is important to the communications and is described in a different video. 

The most common serial interface used in precision data converters is a standard known as serial peripheral interface, abbreviated as SPI. There are two control lines for SPI. The controller, usually a microcontroller or DSP, controls the peripheral select and the serial clock used for data synchronization. A SPI bus can control multiple peripherals, but there can only be one controller. Each peripheral requires its own peripheral select line from the controller. 

Additionally, there are two data lines. One line sends data from the controller to the peripheral and another sends data from the peripheral to the controller. The data transmission may be full duplex, meaning that data can be transmitted in both directions at the same time, using the same SCLK pulses for clocking data. The next slides describe the four SPI lines. 

SS is the peripheral select. This line is used to select the peripheral device for communication. If there are multiple devices on the SPI bus, each device has its own peripheral select. Peripheral select is often used as active low, indicated by an overbar. 

When the device is selected, peripheral select goes low to activate communication. When the device is not selected, the peripheral select is set high. Peripheral select may also be labeled as SSEL, CS, CS bar, CE, nSS, or SS#. In many precision ADCs from TI, this chip select line is commonly labeled as CS bar, used as active low. In many TI precision DACs, this line is commonly labeled as SYNC bar, also active low. 

SCLK is the serial clock. As mentioned previously, SCLK is used by the controller to synchronize the data sent between the controller and the peripheral device. The SCLK originates from the controller and is sent to all peripheral devices. This serial clock may not always be in operation and may be idle as a high or low signal. Data is clocked into the controller or peripheral at either the rising edge or falling edge of the serial clock. The SCLK line may also be labeled as SCK. 

MOSI is the controller out, peripheral in. This line is used to send data from the controller to the peripheral device. The peripheral device reads the MOSI line based on synchronization from the SCLK. Again, this line may have different names depending on the device manufacturer. On the peripheral device, it may be known as SIMO, SDI, DI, DN, or SI. 

This line is connected to the controller device on some serial outline labeled as SDO, DO, or DOUT. In precision data converters, if there are registers that require configuration, the configuration data are sent on this line. If the device is not active, as the controller has not selected the device to be active with peripheral select, this line is deactivated, and the peripheral does not receive data on MOSI. In many precision data converters, TI commonly labels this digital input as DN. 

MISO is controller in, peripheral out. This line is used to send data from the peripheral device out to the controller. If the controller has not selected the device to be active with peripheral select, this line becomes high impedance, or Hi-Z, allowing for a system with multiple devices to share this line. 

The peripheral device sends data out on the MISO line and is synchronized with the SCLK. On the peripheral device, it may be known as SOMI, SDO, DO, DOUT, or SO. This line is connected to the controller device on some serial outline labeled as SDI, DI, or DN. In many precision data converters, TI commonly labels this digital output as DOUT. 

As previously mentioned, data from the controller and peripheral may be read on either the rising or falling edge of SCLK. Additionally, the clock polarity is important in defining the leading and trailing edges on which the data is clocked in and out of the device. This enables several modes of SPI communication. 

There are two parameters used to determine modes of operation. The first parameter, CPOL, determines the clock polarity for the serial clock. When CPOL equals 0, then the clock idles low. The leading edge is a rising edge, and the trailing edge is a falling edge. When CPOL is equal to 1, the clock idles high. The leading edge is a falling edge, and the trailing edge is a rising edge. 

The second parameter, CPHA, determines the clock phase for which the data is acquired. For the CPHA equal to 0, data is captured on the leading edge of the clock pulse. Data is set up on the trailing edge of SCLK for the first bit when SS bar is set low. For CPHA equal to 1, the data is captured on the trailing edge of SCLK. In both clock phase modes, data is set up on the previous clock edge. 

Combinations of CPOL and CPHA allow for four modes of operation of SPI. The table in this slide shows SPI mode 0 through 3. Each defines a different clock polarity and phase for SPI communication. Note that different manufacturers of SPI devices and microcontrollers may have different definitions of SPI mode numbers. Consult the data sheets for both the controller and peripherals to determine the clock polarity and phase information. 

SPI can be used to communicate with multiple devices. This can be done in two different ways. First, because SPI uses peripheral select lines, the controller can communicate with multiple devices. Each peripheral has its own peripheral select coming from the controller, while the remaining lines are shared. 

When peripheral select is selected for the device, the remaining SPI lines are active. When the peripheral select is not selected, the SPI lines are ignored. When not selected, each peripheral MOSI and SCLK line is ignored, and each MISO line becomes Hi-Z so that an active peripheral may drive the MISO without contention from other peripherals trying to drive the same line. 

For some systems, a single SPI drives one peripheral while other peripherals are daisy-chained together. In a daisy-chained system, SCLKs and peripheral selects may be shared by all peripherals. However, the controller connects to a single MOSI of the first peripheral. The MISO of the first peripheral connects to the MOSI of the next peripheral. This chains all of the peripherals together from one MISO to the next MOSI. 

For the last peripheral device, the MISO connects to the controller. All data from the devices are passed through the chain and collected at the end from the final peripheral. Not all devices are able to be controlled and read through a daisy-chained SPI connection. Devices must be specifically designed for this communication. 

Here is an example of SPI data communication. This comes from the communication of the ADS1118 precision ADC. The ADS1118 is a 16-bit ADC that uses SPI mode 1 with CPOL equal to 0 and CPHA equal to 1. Here, the SCLK idles low, and the data is clocked in and out of the device on the trailing edge of SCLK. 

In the 16-bit data transmission cycle, two bytes of data are clocked into a configuration register. At the same time, 16 bits of ADC data is clocked out of the device. The ADC has a 16-bit configuration register with settings showing in the table. These configuration register values program the device to the settings shown in the description common. For this example, the setting we want to write to the device is 81C3 and hexadecimal. 

Continuing with the example, this is the 16-bit data transmission cycle for the ADS1118 showing the SPI lines. Again, the SCLK idles low, and data is transmitted at the falling edge of SCLK. The write to the device is done on the MOSI, or on this device, the pin is labeled as DN. The configuration register is set to 81C3 and hexadecimal. 

At the same time, the ADC data is clocked out of the ADS1118. Here, a random output data word is clocked out of the device. Looking at the DOUT line, the binary output is read as E476 and hexadecimal. 

That concludes this video. Thank you for watching. Please try the quiz to check your understanding of this video's content. 

Question one. The following binary output is what value in hexadecimal? The correct answer is D, A6. 

Question two. The following diagram is CPOL equal to 0 and CPHA equal to 1. What hexadecimal byte is sent from the peripheral to the controller in this transaction? The correct answer is B, 26. 

Question three. The following diagram is CPOL equal to 0 and CPHA equal to 1. What hexadecimal byte is sent from the controller to the peripheral in this transaction? The correct answer is D, EC.