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  • 66AK2Hxx Multicore DSP+ARM® KeyStone II System-on-Chip (SoC)

    • SPRS866G November   2012  – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14

      PRODUCTION DATA.  

  • CONTENTS
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  • 66AK2Hxx Multicore DSP+ARM® KeyStone II System-on-Chip (SoC)
  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
      1. 1.3.1 Enhancements in KeyStone II
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Package Terminals
    2. 4.2 Pin Map
    3. 4.3 Terminal Functions
    4. 4.4 Pullup/Pulldown Resistors
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for PBGA Package [AAW]
    7. 5.7 Power Supply to Peripheral I/O Mapping
  6. 6 C66x CorePac
    1. 6.1 C66x DSP CorePac
    2. 6.2 Memory Architecture
      1. 6.2.1 L1P Memory
      2. 6.2.2 L1D Memory
      3. 6.2.3 L2 Memory
      4. 6.2.4 Multicore Shared Memory SRAM
      5. 6.2.5 L3 Memory
    3. 6.3 Memory Protection
    4. 6.4 Bandwidth Management
    5. 6.5 Power-Down Control
    6. 6.6 C66x CorePac Revision
    7. 6.7 C66x CorePac Register Descriptions
  7. 7 ARM CorePac
    1. 7.1 Features
    2. 7.2 System Integration
    3. 7.3 ARM Cortex-A15 Processor
      1. 7.3.1 Overview
      2. 7.3.2 Features
      3. 7.3.3 ARM Interrupt Controller
      4. 7.3.4 Endianess
    4. 7.4 CFG Connection
    5. 7.5 Main TeraNet Connection
    6. 7.6 Clocking and Reset
      1. 7.6.1 Clocking
      2. 7.6.2 Reset
  8. 8 Memory, Interrupts, and EDMA for 66AK2Hxx
    1. 8.1 Memory Map Summary for 66AK2Hxx
    2. 8.2 Memory Protection Unit (MPU) for 66AK2Hxx
      1. 8.2.1 MPU Registers
        1. 8.2.1.1 MPU Register Map
        2. 8.2.1.2 Device-Specific MPU Registers
          1. 8.2.1.2.1 Configuration Register (CONFIG)
      2. 8.2.2 MPU Programmable Range Registers
        1. 8.2.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
        2. 8.2.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
        3. 8.2.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
    3. 8.3 Interrupts for 66AK2Hxx
      1. 8.3.1 Interrupt Sources and Interrupt Controller
      2. 8.3.2 CIC Registers
        1. 8.3.2.1 CIC0 Register Map
        2. 8.3.2.2 CIC1 Register Map
        3. 8.3.2.3 CIC2 Register Map
      3. 8.3.3 Inter-Processor Register Map
      4. 8.3.4 NMI and LRESET
    4. 8.4 Enhanced Direct Memory Access (EDMA3) Controller for 66AK2Hxx
      1. 8.4.1 EDMA3 Device-Specific Information
      2. 8.4.2 EDMA3 Channel Controller Configuration
      3. 8.4.3 EDMA3 Transfer Controller Configuration
      4. 8.4.4 EDMA3 Channel Synchronization Events
  9. 9 System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix - Data Space
    3. 9.3 TeraNet Switch Fabric Connections Matrix - Configuration Space
    4. 9.4 Bus Priorities
  10. 10Device Boot and Configuration
    1. 10.1 Device Boot
      1. 10.1.1 Boot Sequence
      2. 10.1.2 Boot Modes Supported
        1. 10.1.2.1 Boot Device Field
        2. 10.1.2.2 Device Configuration Field
          1. 10.1.2.2.1 Sleep Boot Mode Configuration
          2. 10.1.2.2.2 I2C Boot Device Configuration
            1. 10.1.2.2.2.1 I2C Passive Mode
            2. 10.1.2.2.2.2 I2C Master Mode
          3. 10.1.2.2.3 SPI Boot Device Configuration
          4. 10.1.2.2.4 EMIF Boot Device Configuration
          5. 10.1.2.2.5 NAND Boot Device Configuration
        3. 10.1.2.3 Serial Rapid I/O Boot Device Configuration
        4. 10.1.2.4 Ethernet (SGMII) Boot Device Configuration
          1. 10.1.2.4.1 PCIe Boot Device Configuration
          2. 10.1.2.4.2 HyperLink Boot Device Configuration
          3. 10.1.2.4.3 UART Boot Device Configuration
        5. 10.1.2.5 Boot Parameter Table
          1. 10.1.2.5.1  EMIF16 Boot Parameter Table
          2. 10.1.2.5.2  SRIO Boot Parameter Table
          3. 10.1.2.5.3  Ethernet Boot Parameter Table
          4. 10.1.2.5.4  PCIe Boot Parameter Table
          5. 10.1.2.5.5  I2C Boot Parameter Table
          6. 10.1.2.5.6  SPI Boot Parameter Table
          7. 10.1.2.5.7  HyperLink Boot Parameter Table
          8. 10.1.2.5.8  UART Boot Parameter Table
          9. 10.1.2.5.9  NAND Boot Parameter Table
          10. 10.1.2.5.10 DDR3 Configuration Table
        6. 10.1.2.6 Second-Level Bootloaders
      3. 10.1.3 SoC Security
      4. 10.1.4 System PLL Settings
        1. 10.1.4.1 ARM CorePac System PLL Settings
    2. 10.2 Device Configuration
      1. 10.2.1 Device Configuration at Device Reset
      2. 10.2.2 Peripheral Selection After Device Reset
      3. 10.2.3 Device State Control Registers
        1. 10.2.3.1  Device Status (DEVSTAT) Register
        2. 10.2.3.2  Device Configuration Register
        3. 10.2.3.3  JTAG ID (JTAGID) Register Description
        4. 10.2.3.4  Kicker Mechanism (KICK0 and KICK1) Register
        5. 10.2.3.5  DSP Boot Address Register (DSP_BOOT_ADDRn)
        6. 10.2.3.6  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
        7. 10.2.3.7  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
        8. 10.2.3.8  Reset Status (RESET_STAT) Register
        9. 10.2.3.9  Reset Status Clear (RESET_STAT_CLR) Register
        10. 10.2.3.10 Boot Complete (BOOTCOMPLETE) Register
        11. 10.2.3.11 Power State Control (PWRSTATECTL) Register
        12. 10.2.3.12 NMI Event Generation to C66x CorePac (NMIGRx) Register
        13. 10.2.3.13 IPC Generation (IPCGRx) Registers
        14. 10.2.3.14 IPC Acknowledgment (IPCARx) Registers
        15. 10.2.3.15 IPC Generation Host (IPCGRH) Register
        16. 10.2.3.16 IPC Acknowledgment Host (IPCARH) Register
        17. 10.2.3.17 Timer Input Selection Register (TINPSEL)
        18. 10.2.3.18 Timer Output Selection Register (TOUTPSEL)
        19. 10.2.3.19 Reset Mux (RSTMUXx) Register
        20. 10.2.3.20 Device Speed (DEVSPEED) Register
        21. 10.2.3.21 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
        22. 10.2.3.22 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
        23. 10.2.3.23 ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
        24. 10.2.3.24 Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
        25. 10.2.3.25 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
        26. 10.2.3.26 System Endian Status Register (SYSENDSTAT)
        27. 10.2.3.27 SYNECLK_PINCTL Register
        28. 10.2.3.28 USB PHY Control (USB_PHY_CTLx) Registers
  11. 1166AK2Hxx Peripheral Information
    1. 11.1  Recommended Clock and Control Signal Transition Behavior
    2. 11.2  Power Supplies
      1. 11.2.1 Power-Up Sequencing
        1. 11.2.1.1 Core-Before-IO Power Sequencing
        2. 11.2.1.2 IO-Before-Core Power Sequencing
        3. 11.2.1.3 Prolonged Resets
        4. 11.2.1.4 Clocking During Power Sequencing
      2. 11.2.2 Power-Down Sequence
      3. 11.2.3 Power Supply Decoupling and Bulk Capacitor
      4. 11.2.4 SmartReflex
    3. 11.3  Power Sleep Controller (PSC)
      1. 11.3.1 Power Domains
      2. 11.3.2 Clock Domains
      3. 11.3.3 PSC Register Memory Map
    4. 11.4  Reset Controller
      1. 11.4.1 Power-on Reset
      2. 11.4.2 Hard Reset
      3. 11.4.3 Soft Reset
      4. 11.4.4 Local Reset
      5. 11.4.5 ARM CorePac Reset
      6. 11.4.6 Reset Priority
      7. 11.4.7 Reset Controller Register
      8. 11.4.8 Reset Electrical Data and Timing
    5. 11.5  Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers
      1. 11.5.1 Main PLL Controller Device-Specific Information
        1. 11.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 11.5.1.2 Local Clock Dividers
        3. 11.5.1.3 Module Clock Input
        4. 11.5.1.4 Main PLL Controller Operating Modes
        5. 11.5.1.5 Main PLL Stabilization, Lock, and Reset Times
      2. 11.5.2 PLL Controller Memory Map
        1. 11.5.2.1 PLL Secondary Control Register (SECCTL)
        2. 11.5.2.2 PLL Controller Divider Register (PLLDIV3 and PLLDIV4)
        3. 11.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
        4. 11.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
        5. 11.5.2.5 SYSCLK Status Register (SYSTAT)
        6. 11.5.2.6 Reset Type Status Register (RSTYPE)
        7. 11.5.2.7 Reset Control Register (RSTCTRL)
        8. 11.5.2.8 Reset Configuration Register (RSTCFG)
        9. 11.5.2.9 Reset Isolation Register (RSISO)
      3. 11.5.3 Main PLL Control Registers
      4. 11.5.4 ARM PLL Control Registers
      5. 11.5.5 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Electrical Data and Timing
    6. 11.6  DDR3A PLL and DDR3B PLL
      1. 11.6.1 DDR3A PLL and DDR3B PLL Control Registers
      2. 11.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information
      3. 11.6.3 DDR3 PLL Input Clock Electrical Data and Timing
    7. 11.7  PASS PLL
      1. 11.7.1 PASS PLL Local Clock Dividers
      2. 11.7.2 PASS PLL Control Registers
      3. 11.7.3 PASS PLL Device-Specific Information
      4. 11.7.4 PASS PLL Input Clock Electrical Data and Timing
    8. 11.8  External Interrupts
      1. 11.8.1 External Interrupts Electrical Data and Timing
    9. 11.9  DDR3A and DDR3B Memory Controllers
      1. 11.9.1 DDR3 Memory Controller Device-Specific Information
      2. 11.9.2 DDR3 Slew Rate Control
      3. 11.9.3 DDR3 Memory Controller Electrical Data and Timing
    10. 11.10 I2C Peripheral
      1. 11.10.1 I2C Device-Specific Information
      2. 11.10.2 I2C Peripheral Register Description
      3. 11.10.3 I2C Electrical Data and Timing
    11. 11.11 SPI Peripheral
      1. 11.11.1 SPI Electrical Data and Timing
    12. 11.12 HyperLink Peripheral
    13. 11.13 UART Peripheral
    14. 11.14 PCIe Peripheral
    15. 11.15 Packet Accelerator
    16. 11.16 Security Accelerator
    17. 11.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
    18. 11.18 SGMII and XFI Management Data Input/Output (MDIO)
    19. 11.19 Ten-Gigabit Ethernet (10GbE) Switch Subsystem
      1. 11.19.1 10GbE Supported Features
    20. 11.20 Timers
      1. 11.20.1 Timers Device-Specific Information
      2. 11.20.2 Timers Electrical Data and Timing
    21. 11.21 Serial RapidIO (SRIO) Port
      1. 11.21.1 Serial RapidIO Device-Specific Information
    22. 11.22 General-Purpose Input/Output (GPIO)
      1. 11.22.1 GPIO Device-Specific Information
      2. 11.22.2 GPIO Peripheral Register Description
      3. 11.22.3 GPIO Electrical Data and Timing
    23. 11.23 Semaphore2
    24. 11.24 Universal Serial Bus 3.0 (USB 3.0)
    25. 11.25 EMIF16 Peripheral
      1. 11.25.1 EMIF16 Electrical Data and Timing
    26. 11.26 Emulation Features and Capability
      1. 11.26.1 Chip-Level Features
        1. 11.26.1.1 ARM Subsystem Features
        2. 11.26.1.2 DSP Features
      2. 11.26.2 ICEPick Module
        1. 11.26.2.1 ICEPick Dynamic Tap Insertion
    27. 11.27 Debug Port (EMUx)
      1. 11.27.1 Concurrent Use of Debug Port
      2. 11.27.2 Master ID for Hardware and Software Messages
      3. 11.27.3 SoC Cross-Triggering Connection
      4. 11.27.4 Peripherals-Related Debug Requirement
      5. 11.27.5 Advanced Event Triggering (AET)
      6. 11.27.6 Trace
        1. 11.27.6.1 Trace Electrical Data and Timing
      7. 11.27.7 IEEE 1149.1 JTAG
        1. 11.27.7.1 IEEE 1149.1 JTAG Compatibility Statement
        2. 11.27.7.2 JTAG Electrical Data and Timing
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Related Links
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
  14. IMPORTANT NOTICE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • AAW|1517
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • SPRS866G_pm
  • sprs866g_oa
search No matches found.
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    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
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DATA SHEET

66AK2Hxx Multicore DSP+ARM® KeyStone II System-on-Chip (SoC)

1 Device Overview

1.1 Features

  • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed- and Floating-Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2 GHz
    • Memory
      • 32-KB L1P Per CorePac
      • 32-KB L1D Per CorePac
      • 1024-KB Local L2 Per CorePac
  • ARM CorePac
    • Four ARM® Cortex®-A15 MPCore™ Processors at up to 1.4 GHz
    • 4MB of L2 Cache Memory Shared by Four ARM Cores
    • Full Implementation of ARMv7-A Architecture Instruction Set
    • 32-KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low-Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 6MB of MSM SRAM Memory Shared by Eight DSP CorePacs and One ARM CorePac
    • Memory Protection Unit (MPU) for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 16k Multipurpose Hardware Queues With Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP, PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1-Gbps Wire Speed Throughput at 1.5 MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP, and WiMAX Air Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-Bit Hash), MD5
      • Up to 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
    • Ethernet Subsystem
      • Five-Port Switch (Four SGMII Ports)
  • Peripherals
    • Four Lanes of SRIO 2.1
      • Supports up to 5 GBaud
      • Supports Direct I/O, Message Passing
    • Two Lanes PCIe Gen2
      • Supports up to 5 GBaud
    • Two HyperLinks
      • Supports Connections to Other KeyStone™ Architecture Devices Providing Resource Scalability
      • Supports up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem (66AK2H14 Only)
      • Two XFI Ports
      • IEEE 1588 Support
    • Five Enhanced Direct Memory Access (EDMA) Modules
    • Two 72-Bit DDR3/DDR3L Interfaces With Speeds up to 1600 MHz
    • EMIF16 Interface
    • USB 3.0
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • Semaphore Module
    • 64-Bit Timers
      • Twenty 64-Bit Timers for 66AK2H14 and 66AK2H12
      • Fourteen 64-Bit Timers for 66AK2H06
    • Five On-Chip PLLs
  • Commercial Case Temperature:
    • 0ºC to 85ºC
  • Extended Case Temperature:
    • –40ºC to 100ºC

1.2 Applications

  • Mission Critical
  • Computing
  • Communications
  • Audio
  • Video Infrastructure
  • Imaging
  • Analytics
  • Networking
  • Media Processing

1.3 Description

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

1.3.1 Enhancements in KeyStone II

The KeyStone II architecture provides many major enhancements over the previous KeyStone I generation of devices. The KeyStone II architecture integrates a Cortex-A15 processor quad-core cluster. The external memory bandwidth has been doubled with the integration of dual DDR3 1600 EMIFs. MSMC internal memory bandwidth is quadrupled with MSMC architecture improvements such as cache coherency. MSMC also enbles memories to operate at the speed of the processor cores, which reduces latency and contention while providing high-bandwidth interconnections between processor cores and shared internal and external memory. Multicore Navigator supports twice the number of queues, descriptors, and packet DMA, four times the number of micro RISC engines, and a significant increase in the number of push/pops per second compared to the previous generation. The new peripherals that have been added include the USB 3.0 controller, and asynchronous EMIF controller for NAND/NOR memory access. The 3-port Gigabit Ethernet switch in KeyStone I has been replaced with a 5-port Gigabit Ethernet switch in KeyStone II. Time synchronization support has been enhanced to reduce software workload and support additional standards like IEEE 1588 Annex D/E and SyncE. The number of GPIOs and serial interface peripherals, like I2C and SPI, have been increased to enable more board-level control functionality.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE
66AK2H14 AAW 40.0 mm × 40.0 mm
66AK2H12 AAW 40.0 mm × 40.0 mm
66AK2H06 AAW 40.0 mm × 40.0 mm
(1) For more information, see Section 13, Mechanical, Packaging, and Orderable Information.

1.4 Functional Block Diagram

Figure 1-1, Figure 1-2, and Figure 1-3 show the functional block diagrams of the devices.

66AK2H14 66AK2H12 66AK2H06 Functional_Block_Diagram_66AK2H14.gif Figure 1-1 Functional Block Diagram for 66AK2H14
66AK2H14 66AK2H12 66AK2H06 Functional_Block_Diagram_66AK2H12.gif Figure 1-2 Functional Block Diagram for 66AK2H12
66AK2H14 66AK2H12 66AK2H06 Functional_Block_Diagram_66AK2H06.gif Figure 1-3 Functional Block Diagram for 66AK2H06

2 Revision History

Changes from F Revision (June 2017) to G Revision

  • Added DDR3L Interface to Features. Go
  • Updated DVDD15 power supply in Terminal Functions — Power and Ground table from 1.5 V to 1.35/1.5 V.Go
  • Updated DVDD15 entry in Recommended Operating Conditions table. Go
  • Updated DVDD15 power supply in Power Supply to Peripheral I/O Mapping table, from 1.5 V to 1.35/1.5 V.Go
  • Added DSP Boot Address Register (DSP_BOOT_ADDRn). Go
  • Updated DVDD15 value in Power Supply Rails table from 1.5 V to 1.35/1.5V.Go
  • Updated DDR3 value in DDR3 Memory Controller Device-Specific Information section from 1.5-V to 1.35-V / 1.5-V. Go
  • Updated Timers Device-Specific Information section. Go

3 Device Comparison

Table 3-1 provides a comparison of the 66AK2Hxx devices. The table lists the significant features of the devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count.

Table 3-1 Device Features Comparison

HARDWARE FEATURES 66AK2H14 66AK2H12 66AK2H06
Cores C66x DSP 8 8 4
ARM Cortex-A15 MPCore 4 4 2
Peripherals 10-GbE 2 – –
DDR3 memory controller (72-bit bus width) 2 2 2
16-bit ASYNC EMIF 1 1 1
EDMA3 (64 independent channels) 5 5 5
High-speed 1×/2×/4× Serial RapidIO port (4 lanes) 1 1 1
HyperLink (4 lanes) 2 2 2
I2C 3 3 3
SPI 3 3 3
PCIe (2 lanes) 1 1 1
USB 3.0 1 1 1
UART 2 2 2
10/100/1000 Ethernet 4 4 4
Management Data Input/Output (MDIO) 1 1 1
64-bit timers (configurable) Twenty 64-bit or Forty 32-bit Twenty 64-bit or Forty 32-bit Fourteen 64-bit or Twenty Eight 32-bit
General-Purpose Input/Output port (GPIO) 32 32 32
Accelerators Packet Accelerator 1 1 1
Security Accelerator(1) 1 1 1
On-Chip Memory Organization L1 program memory controller (C66x) 32KB per CorePac 32KB per CorePac 32KB per CorePac
L1 data memory controller (C66x) 32KB per CorePac 32KB per CorePac 32KB per CorePac
Shared L2 cache (C66x) 8192KB 8192KB 4096KB
L3 ROM (C66x) 128KB 128KB 128KB
L1 program memory controller (ARM Cortex-A15) 32KB per CorePac 32KB per CorePac 32KB per CorePac
L1 data memory controller (ARM Cortex-A15) 32KB per CorePac 32KB per CorePac 32KB per CorePac
Shared L2 cache (ARM Cortex-A15) 4096KB 4096KB 4096KB
L3 ROM (ARM Cortex-A15) 256KB 256KB 256KB
MSMC 6MB 6MB 6MB
C66x CorePac Revision ID CorePac Revision ID Register
(address location: 0181 2000h) 		0x0009_0000 (PG 1.0)
0x0009_0002 (PG 1.1)
0x0009_0003 (PG 2.0)
0x0009_0003 (PG 3.0)
0x0009_0003 (PG 3.1)		 0x0009_0000 (PG 1.0)
0x0009_0002 (PG 1.1)
0x0009_0003 (PG 2.0)
0x0009_0003 (PG 3.0)
0x0009_0003 (PG 3.1)		 0x0009_0000 (PG 1.0)
0x0009_0002 (PG 1.1)
0x0009_0003 (PG 2.0)
0x0009_0003 (PG 3.0)
0x0009_0003 (PG 3.1)
JTAG BSDL_ID JTAGID Register
(address location: 0x02620018) 		0x0b98102f (PG 1.0)
0x1b98102f (PG 1.1)
0x2b98102f (PG 2.0)
0x3b98102f (PG 3.0)
0xbb98102f (PG 3.1)		 0x0b98102f (PG 1.0)
0x1b98102f (PG 1.1)
0x2b98102f (PG 2.0)
0x3b98102f (PG 3.0)
0xbb98102f (PG 3.1)		 0x0b98102f (PG 1.0)
0x1b98102f (PG 1.1)
0x2b98102f (PG 2.0)
0x3b98102f (PG 3.0)
0xbb98102f (PG 3.1)
Frequency C66x Up to 1.2 GHz Up to 1.2 GHz Up to 1.2 GHz
ARM Cortex-A15 Up to 1.4 GHz Up to 1.4 GHz Up to 1.4 GHz
Voltage Core (V) SmartReflex™ variable supply SmartReflex™ variable supply SmartReflex™ variable supply
I/O (V) 0.85 V, 1.0 V, 1.35 V, 1.5 V, 1.8 V and 3.3 V 0.85 V, 1.0 V, 1.35 V, 1.5 V, 1.8 V and 3.3 V 0.85 V, 1.0 V, 1.35 V, 1.5 V, 1.8 V and 3.3 V
BGA Package 40 mm × 40 mm 1517-pin flip-chip plastic BGA (AAW) 1517-pin flip-chip plastic BGA (AAW) 1517-pin flip-chip plastic BGA (AAW)
Process Technology µm 0.028 µm 0.028 µm 0.028 µm
(1) The Security Accelerator function is subject to export control and will be enabled only for approved device shipments.

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

    Digital Signal Processors From sensors to servers, TI has the right DSPs for every application.
    66AK2x Multicore DSP + ARM Processors Describes the features, applications, and products available on these processors.
    Companion Products for 66AK2Hxx Review products that are frequently purchased or used in conjunction with this product.

4 Terminal Configuration and Functions

4.1 Package Terminals

Figure 4-1 shows the AAW ball grid array package (bottom view). The 14 pins that serve the 10-GbE function (XFI) in the 66AK2H14 are reserved in the 66AK2H12/06 devices.

66AK2H14 66AK2H12 66AK2H06 AAW_1517-Pin_BGA_Package_(Bottom_View).gif Figure 4-1 AAW 1517-Pin BGA Package (Bottom View)

4.2 Pin Map

The following figures show the 66AK2Hxx pin assignments in four quadrants (A, B, C, and D). The 14 pins serving the 10-GbE function (XFI) in the 66AK2H14 device are reserved in the 66AK2H12/06 devices.

66AK2H14 66AK2H12 66AK2H06 Pin_Map_Panels.gif Figure 4-2 Pin Map Panels (Bottom View)
1 2 3 4 5 6 7 8 9 10
AW (NOPIN) VSS VSS HYP1CLKP HYP1CLKN VSS HYP0RXN3 HYP0RXP3 VSS HYP0RXN0
AV VSS VSS HYP1RXN3 HYP1RXP3 VSS HYP1RXN1 HYP1RXP1 VSS HYP0RXN2 HYP0RXP2
AU VSS VSS VSS HYP1RXN2 HYP1RXP2 VSS HYP1RXN0 HYP1RXP0 VSS HYP0RXN1
AT RSV190 VSS HYP1TXN3 HYP1TXP3 VSS HYP1TXN0 HYP1TXP0 VSS HYP0CLKP HYP0CLKN
AR RSV189 RSV186 VSS HYP1TXN2 HYP1TXP2 VSS HYP0TXN3 HYP0TXP3 VSS HYP0TXN1
AP TSRXCLKOUT0N RSV187 TSRXCLKOUT1N VSS HYP1TXN1 HYP1TXP1 VSS HYP0TXN2 HYP0TXP2 VSS
AN TSRXCLKOUT0P VSS TSRXCLKOUT1P RSV002 VSS VSS VSS VSS VSS RSV019
AM TSREFCLKP ALTCORECLKP VSS RSV003 CVDD HYP1REFRES RSV020 VSS HYP0REFRES VSS
AL TSREFCLKN ALTCORECLKN SYSCLKP CORECLKSEL VSS CVDD VSS CVDD VSS VDDAHV
AK SYSCLKOUT VSS SYSCLKN POR RSV012 VSS CVDD VSS CVDD VSS
AJ HYP0TXPMDAT HYP0RXPMCLK HYP0TXFLCLK HYP0RXFLDAT HYP0RXFLCLK VSS VSS CVDD VSS CVDD
AH HYP1TXPMCLK HYP1TXFLDAT HYP1TXFLCLK HYP1RXFLCLK HYP0TXPMCLK VSS VSS VSS CVDD VSS
AG TDI HYP1RXFLDAT HYP0RXPMDAT VSS HYP0TXFLDAT DVDD18 VSS CVDD VSS CVDD
AF TDO HYP1TXPMDAT HYP1RXPMCLK HYP1RXPMDAT BOOTCOMPLETE VSS DVDD18 VSS CVDD VSS
AE TCK TMS VSS LRESET HOUT DVDD18 VSS CVDD VSS CVDD
AD TRST RESET RESETFULL LRESETNMIEN NMI VSS DVDD18 VSS CVDD VSS
AC TSPUSHEVT1 TSPUSHEVT0 TSSYNCEVT RSV188 RESETSTAT DVDD18 VSS CVDD VSS CVDD
AB TSCOMPOUT EMU01 EMU14 EMU10 DVDD18 VSS DVDD18 VSS CVDD VSS
AA USBRESREF EMU00 EMU11 EMU18 VSS DVDD18 VSS CVDD VSS CVDD
Y USBRX0M VSS EMU02 EMU03 DVDD18 VSS DVDD18 VSS CVDD VSS
W USBRX0P USBCLKP EMU04 EMU05 VSS DVDD18 VSS CVDD VSS CVDD
V USBTX0M USBCLKM VSS EMU06 DVDD18 VSS DVDD18 VSS CVDD VSS
U USBTX0P USBDP EMU08 EMU07 EMU12 DVDD18 VSS CVDD VSS CVDD
T USBVBUS USBDM EMU09 EMU13 EMU16 VSS DVDD18 VSS CVDD VSS
R USBID0 VSS EMU15 EMU17 VSS DVDD18 VSS CVDD VSS CVDD
P RSV001 RSV000 SDA0 SCL2 VSS VSS CVDD VSS CVDD VSS
N SCL0 SDA1 SDA2 SCL1 VSS CVDD VSS CVDD VSS CVDD
M TIMI1 TIMI0 TIMO0 TIMO1 UART1RTS VSS CVDD VSS CVDD VSS
L UART0CTS UART1RXD USBDRVVBUS UART0RTS VSS CVDD VSS DVDD15 VSS DVDD15
K UART1CTS UART0TXD UART1TXD UART0RXD VSS VSS DVDD15 VSS DVDD15 VSS
J VSS VSS VSS VSS VSS DVDD15 VSS DVDD15 VSS DVDD15
H DDR3AD04 DDR3AD01 DDR3AD13 VSS DDR3AD17 VSS DVDD15 VSS DVDD15 DDR3ARQ1
G DDR3AD00 DDR3AD03 DDR3AD10 DDR3AD16 DDR3AD20 DDR3AD29 DDR3AD30 DDR3AA02 DDR3AA01 DDR3AA03
F DDR3AD02 DDR3AD06 DDR3ADQM1 DDR3AD09 DDR3AD19 DDR3AD26 DDR3AD25 DDR3AA05 DDR3AA04 DDR3AA10
E DDR3ADQS0P DDR3AD05 VSS DDR3AD08 VSS DDR3ADQM3 VSS DDR3AA00 VSS DDR3AA12
D DDR3ADQS0N DDR3AD07 DDR3AD14 DDR3AD15 DDR3AD18 DDR3AD21 DDR3AD31 DDR3AA09 DDR3AA07 DDR3AA15
C VSS DDR3ADQM0 DDR3ADQS1N VSS DDR3AD22 VSS DDR3AD24 VSS DDR3AA06 VSS
B VSS VSS DDR3ADQS1P DDR3AD12 DDR3ADQS2N DDR3AD23 DDR3ADQS3P DDR3AD28 DDR3AA08 DDR3AA14
A (NOPIN) VSS VSS DDR3AD11 DDR3ADQS2P DDR3ADQM2 DDR3ADQS3N DDR3AD27 DDR3AA11 DDR3AA13
1 2 3 4 5 6 7 8 9 10
Figure 4-3 66AK2Hxx Pin Map Left Side Panel (A) — Bottom View
11 12 13 14 15 16 17 18 19 20
AW HYP0RXP0 VSS RSV167 RSV168 VSS RSV161 RSV162 VSS XFIRXP1 XFIRXN1
AV VSS RSV171 RSV172 VSS RSV165 RSV166 VSS XFIRXP0 XFIRXN0 VSS
AU HYP0RXP1 VSS RSV169 RSV170 VSS RSV163 RSV164 VSS XFICLKP XFICLKN
AT VSS RSV183 RSV184 VSS RSV177 RSV178 VSS XFITXP0 XFITXN0 VSS
AR HYP0TXP1 VSS RSV181 RSV182 VSS RSV175 RSV176 VSS XFITXP1 XFITXN1
AP HYP0TXN0 HYP0TXP0 VSS RSV179 RSV180 VSS RSV173 RSV174 VSS VSS
AN VSS VSS VSS VSS VSS XFIREFRES0 VSS VSS RSV026 VSS
AM RSV099 VSS VSS RSV025 RSV185 RSV024 VSS VSS XFIREFRES1 VSS
AL VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS VDDAHV
AK VDDAHV VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS
AJ VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV
AH VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS
AG VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV
AF AVDDA1 VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS
AE VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD
AD VNWA2 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD1 VSS
AC VSS CVDD VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD
AB CVDD VSS VDDUSB VSS CVDD VSS CVDD VSS CVDD VSS
AA VSS VP VSS DVDD33 VSS CVDD VSS CVDD VSS CVDD
Y VPTX VSS VPH VSS CVDD VSS CVDD VSS CVDD VSS
W VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD VSS CVDD
V VNWA4 VSS CVDD1 VSS CVDD VSS CVDD1 VSS CVDD VSS
U VSS CVDD VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD1
T CVDD VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS
R VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD
P AVDDA6 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS
N VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS AVDDA2
M DVDD15 VSS AVDDA7 VSS AVDDA8 VSS DVDD15 AVDDA9 DVDD15 AVDDA10
L VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15
K DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS
J VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15
H DVDD15 VSS DVDD15 VSS DVDD15 DDR3ARQ0 DVDD15 VSS DVDD15 VSS
G DDR3ABA2 DDR3ACKE0 DDR3AODT1 DDR3AVREFSSTL DDR3ACB07 DDR3AD33 DDR3AD35 DDR3AD42 DDR3AD44 DDR3AD51
F DDR3ACE1 DDR3AWE RSV029 DDR3ACB05 DDR3ACB03 DDR3AD34 DDR3AD38 DDR3AD47 DDR3AD43 DDR3AD54
E VSS DDR3AODT0 VSS DDR3ADQM8 VSS DDR3AD32 VSS DDR3AD39 VSS DDR3AD53
D DDR3ACE0 RSV027 RSV028 DDR3ACB06 DDR3ACB04 DDR3AD36 DDR3AD37 DDR3AD46 DDR3AD41 DDR3AD50
C DDR3ABA1 VSS DDR3ACAS VSS DDR3ACB01 VSS DDR3ADQM4 VSS DDR3AD40 VSS
B DDR3ABA0 DDR3ACLKOUTN0 DDR3ACLKOUTN1 DDR3ARESET DDR3ADQS8P DDR3ACB02 DDR3ADQS4N DDR3AD45 DDR3ADQS5P DDR3AD49
A DDR3ACKE1 DDR3ACLKOUTP0 DDR3ACLKOUTP1 DDR3ARAS DDR3ADQS8N DDR3ACB00 DDR3ADQS4P DDR3ADQM5 DDR3ADQS5N DDR3AD48
11 12 13 14 15 16 17 18 19 20
Figure 4-4 66AK2Hxx Pin Map Left Center Panel (B) — Bottom View
21 22 23 24 25 26 27 28 29 30
VSS RIORXN2 RIORXP2 VSS SGMII3RXN SGMII3RXP VSS SGMII0RXN SGMII0RXP VSS AW
RIORXN3 RIORXP3 VSS RIORXN0 RIORXP0 VSS SGMII1RXN SGMII1RXP VSS PCIERXN1 AV
VSS RIORXN1 RIORXP1 VSS SGMII2RXN SGMII2RXP VSS SGMII0TXN SGMII0TXP VSS AU
RIOTXN3 RIOTXP3 VSS RIOTXN0 RIOTXP0 VSS SGMII1TXN SGMII1TXP VSS PCIETXN0 AT
VSS VSS RIOTXN1 RIOTXP1 VSS SGMII2TXN SGMII2TXP VSS PCIETXN1 PCIETXP1 AR
VSS RIOTXN2 RIOTXP2 VSS SGMII3TXN SGMII3TXP VSS VSS VSS VSS AP
VSS VSS VSS VSS VSS VSS VSS VSS VSS PACLKSEL AN
RIOREFRES VSS RSV021 SGMIIREFRES RSV023 PCIEREFRES DVDD18 RSV022 DVDD18 RSV192 AM
VSS VDDAHV VSS VDDAHV VSS DVDD18 VSS DVDD18 VSS CVDD AL
VDDAHV VSS VDDAHV VSS VDDAHV VSS DVDD18 VSS CVDD VSS AK
VSS VDDALV VSS VDDALV VSS DVDD18 VSS CVDD VSS DVDD15 AJ
VDDALV VSS VDDALV VSS VDDALV VSS CVDD VSS AVDDA4 VSS AH
VSS VDDALV VSS VNWA1 VSS AVDDA5 VSS CVDD VSS DVDD15 AG
VDDALV VSS VDDALV VSS CVDD VSS CVDD VSS DVDD15 VSS AF
VSS CVDD VSS CVDD VSS CVDD VSS AVDDA15 VSS DVDD15 AE
CVDD VSS CVDD VSS CVDD VSS CVDD AVDDA14 DVDD15 VSS AD
VSS CVDD VSS CVDD VSS CVDD VSS AVDDA13 VSS DVDD15 AC
CVDD VSS CVDD VSS CVDD VSS CVDD AVDDA12 DVDD15 VSS AB
VSS CVDD VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 AA
CVDD VSS CVDD VSS CVDD VSS CVDD AVDDA11 DVDD15 VSS Y
VSS CVDDT1 VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 W
CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS DVDD15 VSS V
VSS CVDDT1 VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 U
CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS DVDD15 VSS T
VSS CVDDT1 VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 R
CVDD VSS CVDD VSS CVDD VSS CVDD VSS DVDD15 VSS P
VSS CVDD VSS CVDD VSS CVDD VSS AVDDA3 VSS DVDD18 N
VPP VSS VNWA3 VSS CVDD VSS CVDD VSS DVDD18 VSS M
VSS VPP VSS DVDD18 VSS DVDD18 VSS CVDD VSS DVDD18 L
DVDD15 VSS DVDD15 VSS DVDD18 VSS DVDD18 VSS CVDD VSS K
VSS DVDD15 VSS VSS VSS DVDD18 VSS DVDD18 VSS CVDD J
DVDD15 DDR3ARQ2 DVDD15 VSS DVDD18 VSS DVDD18 VSS VSS VSS H
DDR3AD55 DDR3AD57 VSS CORESEL3 VSS RSV018 VSS SPI2DOUT VSS GPIO09 G
DDR3AD62 DDR3AD59 RSV013 CORESEL0 SPI0SCS0 RSV017 SPI1DIN SPI2DIN GPIO00 GPIO12 F
VSS DDR3AD60 RSV014 CORESEL1 SPI2SCS3 SPI0SCS2 SPI1SCS3 VSS GPIO05 GPIO11 E
DDR3ADQM6 DDR3AD63 DDR3AD58 CORESEL2 SPI2CLK SPI0SCS3 SPI1SCS2 SPI2SCS1 GPIO02 GPIO06 D
DDR3AD52 VSS DDR3AD56 VSS SPI0SCS1 VSS SPI1SCS1 SPI1CLK VSS GPIO07 C
DDR3ADQS6N DDR3AD61 DDR3ADQS7N RSV004 DDR3ACLKP SPI0CLK SPI1SCS0 SPI2SCS0 GPIO04 GPIO01 B
DDR3ADQS6P DDR3ADQM7 DDR3ADQS7P RSV005 DDR3ACLKN SPI0DIN SPI0DOUT SPI1DOUT SPI2SCS2 GPIO08 A
21 22 23 24 25 26 27 28 29 30
Figure 4-5 66AK2Hxx Pin Map Right Center Panel (C) — Bottom View
31 32 33 34 35 36 37 38 39
PCIECLKP PCIECLKN VSS SRIOSGMIICLKP SRIOSGMIICLKN RSV81 VSS VSS (NOPIN) AW
PCIERXP1 VSS PASSCLKP PASSCLKN VSS RSV79 RSV77 VSS VSS AV
PCIERXN0 PCIERXP0 VSS RSV008 RSV80 RSV76 RSV78 VCNTL4 VSS AU
PCIETXP0 VSS XFIMDIO RSV009 RSV75 VSS RSV74 VCNTL3 VCNTL0 AT
VSS MDIO VSS XFIMDCLK VCNTL5 VCNTL2 VCNTL1 DDR3BCLKP DDR3BCLKN AR
MDCLK RSV193 RSV195 RSV191 VD VCL VSS RSV006 RSV007 AP
VSS RSV194 DDR3BD58 DDR3BD56 VSS DDR3BD57 DDR3BD63 DDR3BDQS7P DDR3BDQS7N AN
CVDD VSS VSS DDR3BD59 DDR3BD60 DDR3BD62 VSS DDR3BD61 DDR3BDQM7 AM
VSS DVDD15 DDR3BD55 DDR3BD52 VSS DDR3BD53 DDR3BD54 DDR3BDQS6N DDR3BDQS6P AL
DVDD15 DDR3BRQ2 VSS DDR3BDQM6 DDR3BD51 DDR3BD50 VSS DDR3BD49 DDR3BD48 AK
VSS VSS DDR3BD41 DDR3BD43 VSS DDR3BD44 DDR3BD47 DDR3BDQS5N DDR3BDQS5P AJ
DVDD15 DDR3BD40 VSS DDR3BD37 DDR3BD38 DDR3BD42 VSS DDR3BD46 DDR3BD45 AH
VSS DDR3BD39 DDR3BDQM4 DDR3BD35 VSS DDR3BD36 DDR3BD32 DDR3BD34 DDR3BDQM5 AG
DVDD15 DDR3BCB00 VSS DDR3BCB01 DDR3BCB03 DDR3BD33 VSS DDR3BDQS4P DDR3BDQS4N AF
VSS DDR3BCB02 DDR3BCB04 DDR3BCB07 VSS DDR3BCB05 DDR3BDQM8 DDR3BDQS8N DDR3BDQS8P AE
DVDD15 DDR3BRAS VSS DDR3BODT1 RSV030 DDR3BCB06 VSS DDR3BCLKOUTP0 DDR3BCLKOUTN0 AD
DDR3BVREFSSTL DDR3BRESET DDR3BODT0 RSV031 VSS DDR3BCAS DDR3BWE DDR3BCLKOUTN1 DDR3BCLKOUTP1 AC
DVDD15 RSV032 VSS DDR3BCE0 DDR3BBA2 VSS VSS DDR3BCKE1 DDR3BCKE0 AB
DDR3BRQ0 DDR3BA00 DDR3BA08 DDR3BBA1 VSS DDR3BCE1 DDR3BBA0 DDR3BA14 DDR3BA11 AA
DVDD15 DDR3BA09 VSS DDR3BA03 DDR3BA12 DDR3BA15 VSS DDR3BA10 DDR3BA13 Y
VSS DDR3BA02 DDR3BA01 DDR3BA04 VSS DDR3BA06 DDR3BA07 DDR3BD27 DDR3BD28 W
DVDD15 DDR3BD30 VSS DDR3BA05 DDR3BD24 DDR3BD31 VSS DDR3BDQS3N DDR3BDQS3P V
VSS DDR3BDQM3 DDR3BD29 DDR3BD26 VSS DDR3BD25 DDR3BD21 DDR3BD23 DDR3BDQM2 U
DVDD15 DDR3BD08 VSS DDR3BD16 DDR3BD18 DDR3BD22 VSS DDR3BDQS2N DDR3BDQS2P T
VSS DDR3BD09 DDR3BD14 DDR3BD17 VSS DDR3BD20 DDR3BD19 DDR3BD12 DDR3BD11 R
DVDD15 DDR3BRQ1 VSS DDR3BDQM1 DDR3BD10 DDR3BD15 VSS DDR3BDQS1N DDR3BDQS1P P
VSS DDR3BD13 DDR3BD04 DDR3BD01 VSS DDR3BD06 DDR3BD05 DDR3BD07 DDR3BDQM0 N
DVDD15 EMIFD00 VSS EMIFD13 EMIFD15 EMIFD14 DDR3BD02 DDR3BDQS0P DDR3BDQS0N M
VSS DVDD15 EMIFD02 EMIFD03 EMIFD12 EMIFD11 VSS DDR3BD00 DDR3BD03 L
DVDD18 VSS EMIFA07 EMIFA16 VSS EMIFD10 EMIFD06 EMIFD09 EMIFD08 K
VSS DVDD18 VSS EMIFA05 EMIFA18 EMIFA21 EMIFD01 EMIFD05 EMIFD07 J
CVDD VSS EMIFBE1 EMIFBE0 EMIFA06 EMIFA12 VSS EMIFA22 EMIFD04 H
VSS EMIFCE1 EMIFCE0 EMIFCE2 VSS EMIFA02 EMIFA09 EMIFA14 EMIFA19 G
GPIO10 RSV016 EMIFRNW EMIFA00 EMIFA17 EMIFWE EMIFA01 EMIFA10 EMIFA15 F
GPIO25 GPIO14 RSV015 EMIFA04 EMIFA13 EMIFCE3 EMIFOE EMIFWAIT0 EMIFA03 E
GPIO22 GPIO27 GPIO21 VSS EMIFA11 EMIFA23 VSS RSV011 EMIFWAIT1 D
GPIO18 VSS GPIO28 GPIO29 EMIFA08 EMIFA20 ARMCLKP RSV010 VSS C
GPIO15 GPIO19 GPIO24 GPIO31 GPIO23 GPIO30 ARMCLKN VSS VSS B
GPIO13 GPIO17 GPIO20 GPIO26 GPIO03 GPIO16 VSS VSS (NOPIN) A
31 32 33 34 35 36 37 38 39
Figure 4-6 66AK2Hxx Pin Map Right Side Panel (D) — Bottom View

4.3 Terminal Functions

The terminal functions table (Table 4-2) identifies the external signal names, the associated pin (ball) numbers, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and gives functional pin descriptions. This table is arranged by function. The power terminal functions table (Table 4-3) lists the various power supply pins and ground pins and gives functional pin descriptions. Table 4-4 shows all pins arranged by signal name. Table 4-5 shows all pins arranged by ball number.

There are 17 pins that have a secondary function as well as a primary function. The secondary function is indicated with a dagger (†).

For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and pullup/pulldown resistors, see Section 10.2.

Use the symbol definitions in Table 4-1 when reading Table 4-2.

Table 4-1 I/O Functional Symbol Definitions

FUNCTIONAL SYMBOL DEFINITION Table 4-2 COLUMN HEADING
IPD or IPU Internal 100-µA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Hardware Design Guide for KeyStone II Devices. IPD/IPU
A Analog signal Type
GND Ground Type
I Input terminal Type
O Output terminal Type
S Supply voltage Type
Z Three-state terminal or high impedance Type

Table 4-2 Terminal Functions — Signals and Control by Function

SIGNAL NAME BALL NO. TYPE IPD/IPU DESCRIPTION
Boot Configuration Pins
ARMAVSSHARED† G24 I Down Boot strapped pin to share ARM AVS with SoC. Pin shared with CORESEL3.
AVSIFSEL0† M2 I Down Default value (Boot Strapped) for SR PINMUX register (SR_PINCTL). Pins shared with TIMI0 and TIMI1.
AVSIFSEL1† M1 I Down
BOOTMODE_RSVD† B31 I Down BOOTMODE reserved pin. Pin shared with GPIO15.
BOOTMODE00† B30 I Down User-defined BOOTMODE pins

See Section 10.1.2 for more details.

(† Pins are secondary functions and are shared with GPIO[01:13])

BOOTMODE01† D29 I Down
BOOTMODE02† A35 I Down
BOOTMODE03† B29 I Down
BOOTMODE04† E29 I Down
BOOTMODE05† D30 I Down
BOOTMODE06† C30 I Down
BOOTMODE07† A30 I Down
BOOTMODE08† G30 I Down
BOOTMODE09† F31 I Down
BOOTMODE10† E30 I Down
BOOTMODE11† F30 I Down
BOOTMODE12† A31 I Down
BOOTMODE13† F24 I User-defined BOOTMODE pins

See Section 10.1.2 for more details.

(† Pins are secondary functions and are shared with CORESEL[0:2])

BOOTMODE14† E24 I
BOOTMODE15† D24 I
BOOTCOMPLETE AF5 OZ Down Boot progress indication output
DDR3A_REMAP_EN† A36 I Down Control ARM remapping of DDR3A address space in the lower 4GB (32b space) Mode select. Secondary function. Pin shared with GPIO16.
LENDIAN† F29 I Up Little-endian configuration pin. Pin shared with GPIO00.
MAINPLLODSEL† E32 I Down Main PLL Output divider select. Pin shared with GPIO14.
Clock / Reset
ALTCORECLKN AL2 I Alternate clock input to Main PLL
ALTCORECLKP AM2 I
ARMCLKN B37 I Reference clock to drive ARM CorePac PLL
ARMCLKP C37 I
CORECLKSEL AL4 I Down Core clock select to select between SYSCLK(N|p) and ALTCORECCLK to the main PLL
CORESEL0 F24 I Down Select for the target core for LRESET and NMI
CORESEL1 E24 I Down
CORESEL2 D24 I Down
CORESEL3 G24 I Down
DDR3ACLKN A25 I DDR3A reference clock input to DDR PLL
DDR3ACLKP B25 I
DDR3BCLKN AR39 I DDR3B reference clock input to DDR PLL
DDR3BCLKP AR38 I
HOUT AE5 OZ Up Interrupt output pulse created by IPCGRH
HYP0CLKN AT10 I HyperLink reference clock to drive HyperLink0 SerDes
HYP0CLKP AT9 I
LRESET AE4 I Up Warm reset
LRESETNMIEN AD4 I Up Enable for core selects
HYP1CLKN AW5 I HyperLink reference clock to drive HyperLink 1 SerDes
HYP1CLKP AW4 I
NMI AD5 I Up Nonmaskable interrupt
PACLKSEL AN30 I Down PA clock select to choose between core clock and PASSCLK pins
PASSCLKN AV34 I Packet Accelerator subsystem reference clock
PASSCLKP AV33 I
PCIECLKN AW32 I PCIe clock input to drive PCIe SerDes
PCIECLKP AW31 I
POR AK4 I Power-on reset
RESETFULL AD3 I Up Full reset
RESET AD2 I Up Warm reset of nonisolated portion of the device
RESETSTAT AC5 O Up Reset status output
SRIOSGMIICLKN AW35 I RapidIO/SGMII reference clock to drive the RapidIO and SGMII SerDes
SRIOSGMIICLKP AW34 I
SYSCLKN AK3 I System clock input to Main PLL (Main PLL optional vs. ALTCORECLK)
SYSCLKP AL3 I
SYSCLKOUT AK1 OZ Down System clock output to be used as a general-purpose output clock for debug purposes
TSREFCLKN AL1 I External precision clock source for SyncE
TSREFCLKP AM1 I
TSRXCLKOUT0N AP1 O SerDes recovered clock output for SyncE.
TSRXCLKOUT0P AN1 O
TSRXCLKOUT1N AP3 O SerDes recovered clock output for SyncE.
TSRXCLKOUT1P AN3 O
DDR3A
DDR3ADQM0 C2 OZ DDR3A EMIF data masks
DDR3ADQM1 F3 OZ
DDR3ADQM2 A6 OZ
DDR3ADQM3 E6 OZ
DDR3ADQM4 C17 OZ
DDR3ADQM5 A18 OZ
DDR3ADQM6 D21 OZ
DDR3ADQM7 A22 OZ
DDR3ADQM8 E14 OZ
DDR3ADQS0P E1 IOZ DDR3A EMIF data strobe
DDR3ADQS0N D1 IOZ
DDR3ADQS1P B3 IOZ
DDR3ADQS1N C3 IOZ
DDR3ADQS2P A5 IOZ
DDR3ADQS2N B5 IOZ
DDR3ADQS3P B7 IOZ
DDR3ADQS3N A7 IOZ
DDR3ADQS4P A17 IOZ
DDR3ADQS4N B17 IOZ
DDR3ADQS5P B19 IOZ
DDR3ADQS5N A19 IOZ
DDR3ADQS6P A21 IOZ
DDR3ADQS6N B21 IOZ
DDR3ADQS7P A23 IOZ
DDR3ADQS7N B23 IOZ
DDR3ADQS8P B15 IOZ
DDR3ADQS8N A15 IOZ
DDR3ACB00 A16 IOZ DDR3A EMIF check bits
DDR3ACB01 C15 IOZ
DDR3ACB02 B16 IOZ
DDR3ACB03 F15 IOZ
DDR3ACB04 D15 IOZ
DDR3ACB05 F14 IOZ
DDR3ACB06 D14 IOZ
DDR3ACB07 G15 IOZ
DDR3AD00 G1 IOZ DDR3A EMIF data bus
DDR3AD01 H2 IOZ
DDR3AD02 F1 IOZ
DDR3AD03 G2 IOZ
DDR3AD04 H1 IOZ
DDR3AD05 E2 IOZ
DDR3AD06 F2 IOZ
DDR3AD07 D2 IOZ
DDR3AD08 E4 IOZ
DDR3AD09 F4 IOZ
DDR3AD10 G3 IOZ
DDR3AD11 A4 IOZ
DDR3AD12 B4 IOZ
DDR3AD13 H3 IOZ
DDR3AD14 D3 IOZ
DDR3AD15 D4 IOZ
DDR3AD16 G4 IOZ DDR3A EMIF data bus
DDR3AD17 H5 IOZ
DDR3AD18 D5 IOZ
DDR3AD19 F5 IOZ
DDR3AD20 G5 IOZ
DDR3AD21 D6 IOZ
DDR3AD22 C5 IOZ
DDR3AD23 B6 IOZ
DDR3AD24 C7 IOZ
DDR3AD25 F7 IOZ
DDR3AD26 F6 IOZ
DDR3AD27 A8 IOZ
DDR3AD28 B8 IOZ
DDR3AD29 G6 IOZ
DDR3AD30 G7 IOZ
DDR3AD31 D7 IOZ
DDR3AD32 E16 IOZ DDR3A EMIF data bus
DDR3AD33 G16 IOZ
DDR3AD34 F16 IOZ
DDR3AD35 G17 IOZ
DDR3AD36 D16 IOZ
DDR3AD37 D17 IOZ
DDR3AD38 F17 IOZ
DDR3AD39 E18 IOZ
DDR3AD40 C19 IOZ
DDR3AD41 D19 IOZ
DDR3AD42 G18 IOZ
DDR3AD43 F19 IOZ
DDR3AD44 G19 IOZ
DDR3AD45 B18 IOZ
DDR3AD46 D18 IOZ
DDR3AD47 F18 IOZ
DDR3AD48 A20 IOZ
DDR3AD49 B20 IOZ DDR3A EMIF data bus
DDR3AD50 D20 IOZ
DDR3AD51 G20 IOZ
DDR3AD52 C21 IOZ
DDR3AD53 E20 IOZ
DDR3AD54 F20 IOZ
DDR3AD55 G21 IOZ
DDR3AD56 C23 IOZ
DDR3AD57 G22 IOZ
DDR3AD58 D23 IOZ
DDR3AD59 F22 IOZ
DDR3AD60 E22 IOZ
DDR3AD61 B22 IOZ
DDR3AD62 F21 IOZ
DDR3AD63 D22 IOZ
DDR3ACE0 D11 OZ DDR3A EMIF chip enable
DDR3ACE1 F11 OZ DDR3A EMIF chip enable
DDR3ABA0 B11 OZ DDR3A EMIF bank address
DDR3ABA1 C11 OZ
DDR3ABA2 G11 OZ
DDR3AA00 E8 OZ DDR3A EMIF address bus
DDR3AA01 G9 OZ
DDR3AA02 G8 OZ
DDR3AA03 G10 OZ
DDR3AA04 F9 OZ
DDR3AA05 F8 OZ
DDR3AA06 C9 OZ
DDR3AA07 D9 OZ
DDR3AA08 B9 OZ
DDR3AA09 D8 OZ
DDR3AA10 F10 OZ
DDR3AA11 A9 OZ
DDR3AA12 E10 OZ
DDR3AA13 A10 OZ
DDR3AA14 B10 OZ
DDR3AA15 D10 OZ
DDR3ACAS C13 OZ DDR3A EMIF column address strobe
DDR3ARAS A14 OZ DDR3A EMIF row address strobe
DDR3AWE F12 OZ DDR3A EMIF write enable
DDR3ACKE0 G12 OZ DDR3A EMIF clock enable0
DDR3ACKE1 A11 OZ DDR3A EMIF clock enable1
DDR3ACLKOUTP0 A12 OZ DDR3A EMIF output clocks to drive SDRAMs (one clock pair per SDRAM) for Rank0
DDR3ACLKOUTN0 B12 OZ
DDR3ACLKOUTP1 A13 OZ DDR3A EMIF output clocks to drive SDRAMs (one clock pair per SDRAM) for Rank1
DDR3ACLKOUTN1 B13 OZ
DDR3AODT0 E12 OZ DDR3A EMIF on die termination outputs used to set termination on the SDRAMs for Rank0
DDR3AODT1 G13 OZ DDR3A EMIF on die termination outputs used to set termination on the SDRAMs for Rank1
DDR3ARESET B14 OZ DDR3A reset signal
DDR3ARZQ0 H16 A PTV compensation pin for DDR3A
DDR3ARZQ1 H10 A PTV compensation pin for DDR3A
DDR3ARZQ2 H22 A PTV compensation pin for DDR3A
DDR3B
DDR3BDQM0 N39 OZ DDR3B EMIF data masks
DDR3BDQM1 P34 OZ
DDR3BDQM2 U39 OZ
DDR3BDQM3 U32 OZ
DDR3BDQM4 AG33 OZ
DDR3BDQM5 AG39 OZ
DDR3BDQM6 AK34 OZ
DDR3BDQM7 AM39 OZ
DDR3BDQM8 AE37 OZ
DDR3BDQS0P M38 IOZ DDR3B EMIF data strobe
DDR3BDQS0N M39 IOZ
DDR3BDQS1P P39 IOZ
DDR3BDQS1N P38 IOZ
DDR3BDQS2P T39 IOZ
DDR3BDQS2N T38 IOZ
DDR3BDQS3P V39 IOZ
DDR3BDQS3N V38 IOZ
DDR3BDQS4P AF38 IOZ
DDR3BDQS4N AF39 IOZ
DDR3BDQS5P AJ39 IOZ
DDR3BDQS5N AJ38 IOZ
DDR3BDQS6P AL39 IOZ
DDR3BDQS6N AL38 IOZ
DDR3BDQS7P AN38 IOZ
DDR3BDQS7N AN39 IOZ
DDR3BDQS8P AE39 IOZ
DDR3BDQS8N AE38 IOZ
DDR3BCB00 AF32 IOZ DDR3B EMIF check bits
DDR3BCB01 AF34 IOZ
DDR3BCB02 AE32 IOZ
DDR3BCB03 AF35 IOZ
DDR3BCB04 AE33 IOZ
DDR3BCB05 AE36 IOZ
DDR3BCB06 AD36 IOZ
DDR3BCB07 AE34 IOZ
DDR3BD00 L38 IOZ DDR3B EMIF data bus
DDR3BD01 N34 IOZ
DDR3BD02 M37 IOZ
DDR3BD03 L39 IOZ
DDR3BD04 N33 IOZ
DDR3BD05 N37 IOZ
DDR3BD06 N36 IOZ
DDR3BD07 N38 IOZ
DDR3BD08 T32 IOZ
DDR3BD09 R32 IOZ
DDR3BD10 P35 IOZ
DDR3BD11 R39 IOZ
DDR3BD12 R38 IOZ
DDR3BD13 N32 IOZ
DDR3BD14 R33 IOZ
DDR3BD15 P36 IOZ
DDR3BD16 T34 IOZ DDR3B EMIF data bus
DDR3BD17 R34 IOZ
DDR3BD18 T35 IOZ
DDR3BD19 R37 IOZ
DDR3BD20 R36 IOZ
DDR3BD21 U37 IOZ
DDR3BD22 T36 IOZ
DDR3BD23 U38 IOZ
DDR3BD24 V35 IOZ
DDR3BD25 U36 IOZ
DDR3BD26 U34 IOZ
DDR3BD27 W38 IOZ
DDR3BD28 W39 IOZ
DDR3BD29 U33 IOZ
DDR3BD30 V32 IOZ
DDR3BD31 V36 IOZ
DDR3BD32 AG37 IOZ DDR3B EMIF data bus
DDR3BD33 AF36 IOZ
DDR3BD34 AG38 IOZ
DDR3BD35 AG34 IOZ
DDR3BD36 AG36 IOZ
DDR3BD37 AH34 IOZ
DDR3BD38 AH35 IOZ
DDR3BD39 AG32 IOZ
DDR3BD40 AH32 IOZ
DDR3BD41 AJ33 IOZ
DDR3BD42 AH36 IOZ
DDR3BD43 AJ34 IOZ
DDR3BD44 AJ36 IOZ
DDR3BD45 AH39 IOZ
DDR3BD46 AH38 IOZ DDR3B EMIF data bus
DDR3BD47 AJ37 IOZ
DDR3BD48 AK39 IOZ
DDR3BD49 AK38 IOZ
DDR3BD50 AK36 IOZ
DDR3BD51 AK35 IOZ
DDR3BD52 AL34 IOZ
DDR3BD53 AL36 IOZ
DDR3BD54 AL37 IOZ
DDR3BD55 AL33 IOZ
DDR3BD56 AN34 IOZ
DDR3BD57 AN36 IOZ
DDR3BD58 AN33 IOZ
DDR3BD59 AM34 IOZ
DDR3BD60 AM35 IOZ
DDR3BD61 AM38 IOZ
DDR3BD62 AM36 IOZ
DDR3BD63 AN37 IOZ
DDR3BCE0 AB34 OZ DDR3B EMIF chip enable
DDR3BCE1 AA36 OZ DDR3B EMIF chip enable
DDR3BBA0 AA37 OZ DDR3B EMIF bank address
DDR3BBA1 AA34 OZ
DDR3BBA2 AB35 OZ
DDR3BA00 AA32 OZ DDR3B EMIF address bus
DDR3BA01 W33 OZ
DDR3BA02 W32 OZ
DDR3BA03 Y34 OZ
DDR3BA04 W34 OZ
DDR3BA05 V34 OZ
DDR3BA06 W36 OZ
DDR3BA07 W37 OZ
DDR3BA08 AA33 OZ
DDR3BA09 Y32 OZ
DDR3BA10 Y38 OZ
DDR3BA11 AA39 OZ
DDR3BA12 Y35 OZ
DDR3BA13 Y39 OZ
DDR3BA14 AA38 OZ
DDR3BA15 Y36 OZ
DDR3BCAS AC36 OZ DDR3B EMIF column address strobe
DDR3BRAS AD32 OZ DDR3B EMIF row address strobe
DDR3BWE AC37 OZ DDR3B EMIF write enable
DDR3BCKE0 AB39 OZ DDR3B EMIF clock enable0
DDR3BCKE1 AB38 OZ DDR3B EMIF clock enable1
DDR3BCLKOUTP0 AD38 OZ DDR3B EMIF output clocks to drive SDRAM (one clock pair for Rank0)
DDR3BCLKOUTN0 AD39 OZ
DDR3BCLKOUTP1 AC39 OZ DDR3B EMIF output clocks to drive SDRAM (one clock pair for Rank1)
DDR3BCLKOUTN1 AC38 OZ
DDR3BODT0 AC33 OZ DDR3B EMIF on-die termination outputs used to set termination on the SDRAMs
DDR3BODT1 AD34 OZ DDR3B EMIF on-die termination outputs used to set termination on the SDRAMs
DDR3BRESET AC32 OZ DDR3B reset signal
DDR3BRZQ0 AA31 A PTV compensation pin for DDR3B
DDR3BRZQ1 P32 A PTV compensation pin for DDR3B
DDR3BRZQ2 AK32 A PTV compensation pin for DDR3B
EMIF16
EMIFRW F33 O Up EMIF control signals
EMIFCE0 G33 O Up
EMIFCE1 G32 O Up
EMIFCE2 G34 O Up
EMIFCE3 E36 O Up
EMIFOE E37 O Up
EMIFWE F36 O Up
EMIFBE0 H34 O Up
EMIFBE1 H33 O Up
EMIFWAIT0 E38 I Down
EMIFWAIT1 D39 I Down
EMIFA00 F34 O Down EMIF address
EMIFA01 F37 O Down
EMIFA02 G36 O Down
EMIFA03 E39 O Down
EMIFA04 E34 O Down
EMIFA05 J34 O Down
EMIFA06 H35 O Down
EMIFA07 K33 O Down
EMIFA08 C35 O Down
EMIFA09 G37 O Down
EMIFA10 F38 O Down
EMIFA11 D35 O Down
EMIFA12 H36 O Down
EMIFA13 E35 O Down
EMIFA14 G38 O Down
EMIFA15 F39 O Down
EMIFA16 K34 O Down EMIF address
EMIFA17 F35 O Down
EMIFA18 J35 O Down
EMIFA19 G39 O Down
EMIFA20 C36 O Down
EMIFA21 J36 O Down
EMIFA22 H38 O Down
EMIFA23 D36 O Down
EMIFD00 M32 IOZ Down EMIF data
EMIFD01 J37 IOZ Down
EMIFD02 L33 IOZ Down
EMIFD03 L34 IOZ Down
EMIFD04 H39 IOZ Down
EMIFD05 J38 IOZ Down
EMIFD06 K37 IOZ Down
EMIFD07 J39 IOZ Down
EMIFD08 K39 IOZ Down
EMIFD09 K38 IOZ Down
EMIFD10 K36 IOZ Down
EMIFD11 L36 IOZ Down
EMIFD12 L35 IOZ Down
EMIFD13 M34 IOZ Down
EMIFD14 M36 IOZ Down
EMIFD15 M35 IOZ Down
EMU
EMU00 AA2 IOZ Up Emulation and trace port
EMU01 AB2 IOZ Up
EMU02 Y3 IOZ Up
EMU03 Y4 IOZ Up
EMU04 W3 IOZ Up
EMU05 W4 IOZ Up
EMU06 V4 IOZ Up
EMU07 U4 IOZ Up
EMU08 U3 IOZ Up
EMU09 T3 IOZ Up
EMU10 AB4 IOZ Up
EMU11 AA3 IOZ Up
EMU12 U5 IOZ Up
EMU13 T4 IOZ Up
EMU14 AB3 IOZ Up
EMU15 R3 IOZ Up
EMU16 T5 IOZ Up
EMU17 R4 IOZ Up
EMU18 AA4 IOZ Up
EMU19† A32 IOZ Down Emulation and trace port

(† Pins shared with GPIO[17:31])

EMU20† C31 IOZ Down
EMU21† B32 IOZ Down
EMU22† A33 IOZ Down
EMU23† D33 IOZ Down
EMU24† D31 IOZ Down
EMU25† B35 IOZ Down
EMU26† B33 IOZ Down
EMU27† E31 IOZ Down
EMU28† A34 IOZ Down
EMU29† D32 IOZ Down
EMU30† C33 IOZ Down
EMU31† C34 IOZ Down
EMU32† B36 IOZ Down
EMU33† B34 IOZ Down
General-Purpose Input/Output (GPIO)
GPIO00 F29 IOZ Up GPIO
GPIO01 B30 IOZ Down
GPIO02 D29 IOZ Down
GPIO03 A35 IOZ Down
GPIO04 B29 IOZ Down
GPIO05 E29 IOZ Down
GPIO06 D30 IOZ Down
GPIO07 C30 IOZ Down
GPIO08 A30 IOZ Down
GPIO09 G30 IOZ Down
GPIO10 F31 IOZ Down
GPIO11 E30 IOZ Down
GPIO12 F30 IOZ Down
GPIO13 A31 IOZ Down
GPIO14 E32 IOZ Down
GPIO15 B31 IOZ Down
GPIO16 A36 IOZ Down GPIO
GPIO17 A32 IOZ Down
GPIO18 C31 IOZ Down
GPIO19 B32 IOZ Down
GPIO20 A33 IOZ Down
GPIO21 D33 IOZ Down
GPIO22 D31 IOZ Down
GPIO23 B35 IOZ Down
GPIO24 B33 IOZ Down
GPIO25 E31 IOZ Down
GPIO26 A34 IOZ Down
GPIO27 D32 IOZ Down
GPIO28 C33 IOZ Down
GPIO29 C34 IOZ Down
GPIO30 B36 IOZ Down
GPIO31 B34 IOZ Down
HyperLink0
HYP0RXN0 AW10 I HyperLink0 receive data
HYP0RXP0 AW11 I
HYP0RXN1 AU10 I
HYP0RXP1 AU11 I
HYP0RXN2 AV9 I
HYP0RXP2 AV10 I
HYP0RXN3 AW7 I
HYP0RXP3 AW8 I
HYP0TXN0 AP11 O HyperLink0 transmit data
HYP0TXP0 AP12 O
HYP0TXN1 AR10 O
HYP0TXP1 AR11 O
HYP0TXN2 AP8 O
HYP0TXP2 AP9 O
HYP0TXN3 AR7 O
HYP0TXP3 AR8 O
HYP0RXFLCLK AJ5 O Down HyperLink0 sideband signals
HYP0RXFLDAT AJ4 O Down
HYP0TXFLCLK AJ3 I Down
HYP0TXFLDAT AG5 I Down
HYP0RXPMCLK AJ2 I Down
HYP0RXPMDAT AG3 I Down
HYP0TXPMCLK AH5 O Down
HYP0TXPMDAT AJ1 O Down
HYP0REFRES AM9 A HyperLink0 SerDes reference resistor input (3 kΩ ±1%)
HyperLink1
HYP1RXN0 AU7 I HyperLink1 receive data
HYP1RXP0 AU8 I
HYP1RXN1 AV6 I
HYP1RXP1 AV7 I
HYP1RXN2 AU4 I
HYP1RXP2 AU5 I
HYP1RXN3 AV3 I
HYP1RXP3 AV4 I
HYP1TXN0 AT6 O HyperLink1 transmit data
HYP1TXP0 AT7 O
HYP1TXN1 AP5 O
HYP1TXP1 AP6 O
HYP1TXN2 AR4 O
HYP1TXP2 AR5 O
HYP1TXN3 AT3 O
HYP1TXP3 AT4 O
HYP1RXFLCLK AH4 O Down HyperLink1 sideband signals
HYP1RXFLDAT AG2 O Down
HYP1TXFLCLK AH3 I Down
HYP1TXFLDAT AH2 I Down
HYP1RXPMCLK AF3 I Down
HYP1RXPMDAT AF4 I Down
HYP1TXPMCLK AH1 O Down
HYP1TXPMDAT AF2 O Down
HYP1REFRES AM6 A HyperLink1 SerDes reference resistor input (3 kΩ ±1%)
I2C
SCL0 N1 IOZ I2C0 clock
SCL1 N4 IOZ I2C1 clock
SCL2 P4 IOZ I2C2 clock
SDA0 P3 IOZ I2C0 data
SDA1 N2 IOZ I2C1 data
SDA2 N3 IOZ I2C2 data
JTAG
TCK AE1 I Up JTAG clock input
TDI AG1 I Up JTAG data input
TDO AF1 OZ Up JTAG data output
TMS AE2 I Up JTAG test mode input
TRST AD1 I Down JTAG reset
MDIO
MDCLK AP31 O Down MDIO clock
MDIO AR32 IOZ Up MDIO data
PCIe
PCIERXN0 AU31 I PCIexpress lane 0 receive data
PCIERXP0 AU32 I
PCIERXN1 AV30 I PCIexpress lane 1 receive data
PCIERXP1 AV31 I
PCIETXN0 AT30 O PCIexpress lane 0 transmit data
PCIETXP0 AT31 O
PCIETXN1 AR29 O PCIexpress lane 1 transmit data
PCIETXP1 AR30 O
PCIEREFRES AM26 A PCIexpress SerDes reference resistor input (3 kΩ ±1%)
Serial RapidIO
RIORXN0 AV24 I Serial RapidIO lane 0 receive data
RIORXP0 AV25 I
RIORXN1 AU22 I Serial RapidIO lane 1 receive data
RIORXP1 AU23 I
RIORXN2 AW22 I Serial RapidIO lane 2 receive data
RIORXP2 AW23 I
RIORXN3 AV21 I Serial RapidIO lane 3 receive data
RIORXP3 AV22 I
RIOTXN0 AT24 O Serial RapidIO lane 0 transmit data
RIOTXP0 AT25 O
RIOTXN1 AR23 O Serial RapidIO lane 1 transmit data
RIOTXP1 AR24 O
RIOTXN2 AP22 O Serial RapidIO lane 2 transmit data
RIOTXP2 AP23 O
RIOTXN3 AT21 O Serial RapidIO lane 3 transmit data
RIOTXP3 AT22 O
RIOREFRES AM21 A Serial RapidIO SerDes reference resistor input (3 kΩ ±1%)
SGMII
SGMII0RXN AW28 I Ethernet MAC SGMII port 0 receive data
SGMII0RXP AW29 I
SGMII0TXN AU28 O Ethernet MAC SGMII port 0 transmit data
SGMII0TXP AU29 O
SGMII1RXN AV27 I Ethernet MAC SGMII port 1 receive data
SGMII1RXP AV28 I
SGMII1TXN AT27 O Ethernet MAC SGMII port 1 transmit data
SGMII1TXP AT28 O
SGMII2RXN AU25 I Ethernet MAC SGMII port 2 receive data
SGMII2RXP AU26 I
SGMII2TXN AR26 O Ethernet MAC SGMII port 2 transmit data
SGMII2TXP AR27 O
SGMII3RXN AW25 I Ethernet MAC SGMII port 3 receive data
SGMII3RXP AW26 I
SGMII3TXN AP25 O Ethernet MAC SGMII port 3 transmit data
SGMII3TXP AP26 O
SGMIIREFRES AM24 A SGMII SerDes reference resistor input (3 kΩ ±1%)
SmartReflex
VCL AP36 IOZ Voltage control I2C clock
VCNTL0 AT39 OZ Voltage control outputs to variable core power supply
VCNTL1 AR37 OZ
VCNTL2 AR36 OZ
VCNTL3 AT38 OZ
VCNTL4 AU38 OZ
VCNTL5 AR35 OZ
VD AP35 IOZ Voltage control I2C data
SPI0
SPI0CLK B26 OZ Down SPI0 clock
SPI0DIN A26 I Down SPI0 data in
SPI0DOUT A27 OZ Down SPI0 data out
SPI0SCS0 F25 OZ Up SPI0 interface enable 0
SPI0SCS1 C25 OZ Up SPI0 interface enable 1
SPI0SCS2 E26 OZ Up SPI0 interface enable 2
SPI0SCS3 D26 OZ Up SPI0 interface enable 3
SPI1
SPI1CLK C28 OZ Down SPI1 clock
SPI1DIN F27 I Down SPI1 data in
SPI1DOUT A28 OZ Down SPI1 data out
SPI1SCS0 B27 OZ Up SPI1 interface enable 0
SPI1SCS1 C27 OZ Up SPI1 interface enable 1
SPI1SCS2 D27 OZ Up SPI1 interface enable 2
SPI1SCS3 E27 OZ Up SPI1 interface enable 3
SPI2
SPI2CLK D25 OZ Down SPI2 clock
SPI2DIN F28 I Down SPI2 data in
SPI2DOUT G28 OZ Down SPI2 data out
SPI2SCS0 B28 OZ Up SPI2 interface enable 0
SPI2SCS1 D28 OZ Up SPI2 interface enable 1
SPI2SCS2 A29 OZ Up SPI2 interface enable 2
SPI2SCS3 E25 OZ Up SPI2 interface enable 3
Sync-Ethernet / IEEE 1588
TSCOMPOUT AB1 O Down IEEE 1588 compare output.
TSPUSHEVT0 AC2 IOZ Down PPS push event from GPS for IEEE 1588
TSPUSHEVT1 AC1 IOZ Down Push event from BCN for IEEE 1588
TSSYNCEVT AC3 O Down IEEE 1588 sync event output.
Timer
TIMI0 M2 I Down Timer inputs
TIMI1 M1 I Down
TIMO0 M3 OZ Down Timer outputs
TIMO1 M4 OZ Down
UART0
UART0CTS L1 I Down UART0
UART0RTS L4 OZ Down
UART0RXD K4 I Down
UART0TXD K2 OZ Down
UART1
UART1CTS K1 I Down UART1
UART1RTS M5 OZ Down
UART1RXD L2 I Down
UART1TXD K3 OZ Down
USB
USBCLKM V2 I USB ref clock
USBCLKP W2 I
USBDM T2 IOZ USB D-
USBDP U2 IOZ USB D+
USBDRVVBUS L3 O Down Used to enable an external charge pump to provide +5V on the VBUS pin of the USB connector.
USBID0 R1 A USB ID
USBRX0M Y1 I USB receive data
USBRX0P W1 I
USBTX0M V1 O USB transmit data
USBTX0P U1 O
USBVBUS T1 A Connect to VBUS pin on USB connector through protection switch
USBRESREF AA1 P Reference resistor connection for USB PHY
XFI (66AK2H14 only)
XFICLKP AU19 I XFI reference clock to drive the XFI SerDes
XFICLKN AU20 I
XFIMDCLK AR34 O Down XFI MDIO clock
XFIMDIO AT33 IOZ Up XFI MDIO data
XFIRXN0 AV19 I Ethernet MAC XFI port 0 receive data
XFIRXP0 AV18 I
XFITXN0 AT19 O Ethernet MAC XFI port 0 transmit data
XFITXP0 AT18 O
XFIRXN1 AW20 I Ethernet MAC XFI port 1 receive data
XFIRXP1 AW19 I
XFITXN1 AR20 O Ethernet MAC XFI port 1 transmit data
XFITXP1 AR19 O
XFIREFRES0 AN16 A XFI SerDes reference resistor input (3 kΩ ±1%)
XFIREFRES1 AM19 A XFI SerDes reference resistor input (3 kΩ ±1%)
Reserved
RSV000 P2 OZ Down Reserved — leave unconnected
RSV001 P1 OZ Down Reserved — leave unconnected
RSV002 AN4 O Reserved — leave unconnected
RSV003 AM4 O Reserved — leave unconnected
RSV004 B24 O Reserved — leave unconnected
RSV005 A24 O Reserved — leave unconnected
RSV006 AP38 O Reserved — leave unconnected
RSV007 AP39 O Reserved — leave unconnected
RSV008 AU34 O Reserved — leave unconnected
RSV009 AT34 O Reserved — leave unconnected
RSV010 C38 O Reserved — leave unconnected
RSV011 D38 O Reserved — leave unconnected
RSV012 AK5 OZ Down Reserved — leave unconnected
RSV013 F23 A GND
RSV014 E23 A Reserved — leave unconnected
RSV015 E33 A Reserved — leave unconnected
RSV016 F32 A Reserved — leave unconnected
RSV017 F26 A Reserved — leave unconnected
RSV018 G26 A Reserved — leave unconnected
RSV019 AN10 A Reserved — leave unconnected
RSV020 AM7 A Reserved — leave unconnected
RSV021 AM23 A Reserved — leave unconnected
RSV022 AM28 A Reserved — leave unconnected
RSV023 AM25 A Reserved — leave unconnected
RSV024 AM16 A Reserved — leave unconnected
RSV025 AM14 A Reserved — leave unconnected
RSV026 AN19 A Reserved — leave unconnected
RSV027 D12 OZ Reserved — leave unconnected
RSV028 D13 OZ Reserved — leave unconnected
RSV029 F13 A Reserved — leave unconnected
RSV030 AD35 OZ Reserved — leave unconnected
RSV031 AC34 OZ Reserved — leave unconnected
RSV032 AB32 A Reserved — leave unconnected
RSV060 (66AK2H12/06 only) AV19 I Reserved — leave unconnected
RSV061 (66AK2H12/06 only) AV18 I Reserved — leave unconnected
RSV062 (66AK2H12/06 only) AT19 O Reserved — leave unconnected
RSV063 (66AK2H12/06 only) AT18 O Reserved — leave unconnected
RSV064 (66AK2H12/06 only) AW20 I Reserved — leave unconnected
RSV065 (66AK2H12/06 only) AW19 I Reserved — leave unconnected
RSV066 (66AK2H12/06 only) AR20 O Reserved — leave unconnected
RSV067 (66AK2H12/06 only) AR19 O Reserved — leave unconnected
RSV068 (66AK2H12/06 only) AN16 A Reserved — leave unconnected
RSV069 (66AK2H12/06 only) AM19 A Reserved — leave unconnected
RSV070 (66AK2H12/06 only) AU19 I Reserved — leave unconnected
RSV071 (66AK2H12/06 only) AU20 I Reserved — leave unconnected
RSV072 (66AK2H12/06 only) AT33 IOZ Up Reserved — leave unconnected
RSV073 (66AK2H12/06 only) AR34 O Down Reserved — leave unconnected
RSV074 AT37 IOZ Reserved — leave unconnected
RSV075 AT35 IOZ Reserved — leave unconnected
RSV076 AU36 OZ Reserved — leave unconnected
RSV077 AV37 OZ Reserved — leave unconnected
RSV078 AU37 OZ Reserved — leave unconnected
RSV079 AV36 OZ Reserved — leave unconnected
RSV080 AU35 OZ Reserved — leave unconnected
RSV081 AW36 OZ Reserved — leave unconnected
RSV099 AM11 A Reserved — leave unconnected
RSV161 AW16 I Reserved — leave unconnected
RSV162 AW17 I Reserved — leave unconnected
RSV163 AU16 I Reserved — leave unconnected
RSV164 AU17 I Reserved — leave unconnected
RSV165 AV15 I Reserved — leave unconnected
RSV166 AV16 I Reserved — leave unconnected
RSV167 AW13 I Reserved — leave unconnected
RSV168 AW14 I Reserved — leave unconnected
RSV169 AU13 I Reserved — leave unconnected
RSV170 AU14 I Reserved — leave unconnected
RSV171 AV12 I Reserved — leave unconnected
RSV172 AV13 I Reserved — leave unconnected
RSV173 AP17 O Reserved — leave unconnected
RSV174 AP18 O Reserved — leave unconnected
RSV175 AR16 O Reserved — leave unconnected
RSV176 AR17 O Reserved — leave unconnected
RSV177 AT15 O Reserved — leave unconnected
RSV178 AT16 O Reserved — leave unconnected
RSV179 AP14 O Reserved — leave unconnected
RSV180 AP15 O Reserved — leave unconnected
RSV181 AR13 O Reserved — leave unconnected
RSV182 AR14 O Reserved — leave unconnected
RSV183 AT12 O Reserved — leave unconnected
RSV184 AT13 O Reserved — leave unconnected
RSV185 AM15 A Reserved — leave unconnected
RSV186 AR2 I Reserved — leave unconnected
RSV187 AP2 I Reserved — leave unconnected
RSV188 AC4 OZ Down Reserved — leave unconnected
RSV189 AR1 I Reserved — leave unconnected
RSV190 AT1 I Reserved — leave unconnected
RSV191 AP34 I Down Reserved — leave unconnected
RSV192 AM30 I Down Reserved — leave unconnected
RSV193 AP32 OZ Down Reserved — leave unconnected
RSV194 AN32 OZ Down Reserved — leave unconnected
RSV195 AP33 IOZ Up Reserved — leave unconnected

Table 4-3 Terminal Functions — Power and Ground

SUPPLY BALL NO. VOLTS DESCRIPTION
AVDDA1 AF11 1.8 V C66x CorePac PLL supply
AVDDA2 N20 1.8 V DDR3A PLL supply
AVDDA3 N28 1.8 V ARM CorePac PLL supply
AVDDA4 AH29 1.8 V DDR3B PLL supply
AVDDA5 AG26 1.8 V Network Coprocessor PLL supply
AVDDA6 P11 1.8 V DDRA DLL supply
AVDDA7 M13 1.8 V DDRA DLL supply
AVDDA8 M15 1.8 V DDRA DLL supply
AVDDA9 M18 1.8 V DDRA DLL supply
AVDDA10 M20 1.8 V DDRA DLL supply
AVDDA11 Y28 1.8 V DDRB DLL supply
AVDDA12 AB28 1.8 V DDRB DLL supply
AVDDA13 AC28 1.8 V DDRB DLL supply
AVDDA14 AD28 1.8 V DDRB DLL supply
AVDDA15 AE28 1.8 V DDRB DLL supply
CVDD H31, J30, K29, L6, L28, M7, M9, M25, M27, N6, N8, N10, N12, N14, N16, N18, N22, N24, N26, P7, P9, P13, P15, P17, P19, P21, P23, P25, P27, R8, R10, R12, R14, R16, R18, R20, R24, R26, T9, T11, T15, T17, T19, T23, T25, T27, U8, U10, U12, U18, U24, U26, V9, V15, V19, V23, V25, V27, W8, W10, W12, W14, W18, W20, W24, W26, Y9, Y15, Y17, Y19, Y21, Y23, Y25, Y27, AA8, AA10, AA16, AA18, AA20, AA22, AA24, AA26, AB9, AB11, AB15, AB17, AB19, AB21, AB23, AB25, AB27, AC8, AC10, AC12, AC14, AC16, AC20, AC22, AC24, AC26, AD9, AD13, AD15, AD21, AD23, AD25, AD27, AE8, AE10, AE12, AE14, AE16, AE18, AE20, AE22, AE24, AE26, AF9, AF25, AF27, AG8, AG10, AG28, AH9, AH27, AJ8, AJ10, AJ28, AK7, AK9, AK29, AL6 , AL8, AL30, AM5, AM31 AVS SmartReflex DSP core supply voltage.
CVDD1 T13, T21, U14, U16, U20, V13, V17, V21, W16, AC18, AD17, AD19 0.95 V Core supply voltage for memory array
CVDDT1 R22, U22, W22 0.95 V Cortex-A15 processor fixed core memory supply voltage
DDR3AVREFSSTL G14 0.75 V 0.75-V DDR3A reference voltage
DDR3BVREFSSTL AC31 0.75 V 0.75-V DDR3B reference voltage
DVDD15 H7, H9, H11, H13, H15, H17, H19, H21, H23, J6, J8, J10, J12, J14, J16, J18, J20, J22, K7, K9, K11, K13, K15, K17, K19, K21, K23, L8, L10, L12, L14, L16, L18, L20, L32, M11, M17, M19, M31, P29, P31, R28, R30, T29, T31, U28, U30, V29, V31, W28, W30, Y29, Y31, AA28, AA30, AB29, AB31, AC30, AD29, AD31, AE30, AF29, AF31, AG30, AH31, AJ30, AK31, AL32 1.35 V / 1.5 V 1.35-V / 1.5-V DDR IO supply
DVDD18 H25, H27, J26, J28, J32, K25, K27, K31, L24, L26, L30, M29, N30, R6, T7, U6, V5, V7, W6, Y5, Y7, AA6, AB5, AB7, AC6, AD7, AE6, AF7, AG6, AJ26, AK27, AL26, AL28, AM27, AM29 1.8 V 1.8-V IO supply
DVDD33 AA14 3.3 V 3.3-V USB supply
VDDAHV AK11, AK13, AK15, AK17, AK19, AK21, AK23, AK25, AL10, AL12, AL14, AL16, AL18, AL20, AL22, AL24 1.8 V SerDes IO supply
VDDALV AF13, AF15, AF17, AF19, AF21, AF23, AG12, AG14, AG16, AG18, AG20, AG22, AH11, AH13, AH15, AH17, AH19, AH21, AH23, AH25, AJ12, AJ14, AJ16, AJ18, AJ20, AJ22, AJ24 0.85 V SerDes low voltage
VDDUSB AB13 0.85 V SerDes digiital IO supply
VNWA1 AG24 0.95 V Fixed Nwell supply
VNWA2 AD11 0.95 V Fixed Nwell supply
VNWA3 M23 0.95 V Fixed Nwell supply
VNWA4 V11 0.95 V Fixed Nwell supply
VP AA12 0.85 V Filtered .85 V USB supply
VPH Y13 3.3 V Filtered 3.3 V USB supply
VPP L22, M21 Leave unconnected
VPTX Y11 0.85 V Filtered 0.85-V USB supply
VSS A2, A3, A37, A38, B1, B2, B38, B39, C1, C4, C6, C8, C10, C12, C14, C16, C18, C20, C22, C24, C26, C29, C32, C39, D34, D37, E3, E5, E7, E9, E11, E13, E15, E17, E19, E21, E28, G23, G25, G27, G29, G31, G35, H4, H6, H8, H12, H14, H18, H20, H24, H26, H28, H29, H30, H32, H37, J1, J2, J3, J4, J5, J7, J9, J11, J13, J15, J17, J19, J21, J23, J24, J25, J27, J29, J31, J33, K5, K6, K8, K10, K12, K14, K16, K18, K20, K22, K24, K26, K28, K30, K32, K35, L5, L7, L9, L11, L13, L15, L17, L19, L21, L23, L25, L27, L29, L31, L37, M6, M8, M10, M12, M14, M16, M22, M24, M26, M28, M30, M33, N5, N7, N9, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N31, N35, P5, P6, P8, P10, P12, P14, P16, P18, P20, P22, P24, P26, P28, P30, P33, P37, R2, R5, R7, R9, R11, R13, R15, R17, R19, R21, R23, R25, R27, R29, R31, R35, T6, T8, T10, T12, T14, T16, T18, T20, T22, T24, T26, T28, T30, T33, T37, U7, U9, U11, U13, U15, U17, U19, U21, U23, U25, U27, U29, U31, U35, V3, V6, V8, V10, V12, V14, V16, V18, V20, V22, V24, V26, V28, V30, V33, V37, W5, W7, W9, W11, W13, W15, W17, W19, W21, W23, W25, W27, W29, W31, W35, Y2, Y6, Y8, Y10, Y12, Y14, Y16, Y18, Y20, Y22, Y24, Y26, Y30, Y33, Y37, AA5, AA7, AA9, AA11, AA13, AA15, AA17, AA19, AA21, AA23, AA25, AA27, AA29, AA35, AB6, AB8, AB10, AB12, AB14, AB16, AB18, AB20, AB22, AB24, AB26, AB30, AB33, AB36, AB37, AC7, AC9, AC11, AC13, AC15, AC17, AC19, AC21, AC23, AC25, AC27, AC29, AC35, AD6, AD8, AD10, AD12, AD14, AD16, AD18, AD20, AD22, AD24, AD26, AD30, AD33, AD37, AE3, AE7, AE9, AE11, AE13, AE15, AE17, AE19, AE21, AE23, AE25, AE27, AE29, AE31, AE35, AF6, AF8, AF10, AF12, AF14, AF16, AF18, AF20, AF22, AF24, AF26, AF28, AF30, AF33, AF37, AG4, AG7, AG9, AG11, AG13, AG15, AG17, AG19, AG21, AG23, AG25, AG27, AG29, AG31, AG35, AH6, AH7, AH8, AH10, AH12, AH14, AH16, AH18, AH20, AH22, AH24, AH26, AH28, AH30, AH33, AH37, AJ6, AJ7, AJ9, AJ11, AJ13, AJ15, AJ17, AJ19, AJ21, AJ23, AJ25, AJ27, AJ29, AJ31, AJ32, AJ35, AK2, AK6, AK8, AK10, AK12, AK14, AK16, AK18, AK20, AK22, AK24, AK26, AK28, AK30, AK33, AK37, AL5, AL7, AL9, AL11, AL13, AL15, AL17, AL19, AL21, AL23, AL25, AL27, AL29, AL31, AL35, AM3, AM8, AM10, AM12, AM13, AM17, AM18, AM20, AM22, AM32, AM33, AM37, AN2, AN5, AN6, AN7, AN8, AN9, AN11, AN12, AN13, AN14, AN15, AN17, AN18, AN20, AN21, AN22, AN23, AN24, AN25, AN26, AN27, AN28, AN29, AN31, AN35, AP4, AP7, AP10, AP13, AP16, AP19, AP20, AP21, AP24, AP27, AP28, AP29, AP30, AP37, AR3, AR6, AR9, AR12, AR15, AR18, AR21, AR22, AR25, AR28, AR31, AR33, AT2, AT5, AT8, AT11, AT14, AT17, AT20, AT23, AT26, AT29, AT32, AT36, AU1, AU2, AU3, AU6, AU9, AU12, AU15, AU18, AU21, AU24, AU27, AU30, AU33, AU39, AV1, AV2, AV5, AV8, AV11, AV14, AV17, AV20, AV23, AV26, AV29 , AV32, AV35, AV38, AV39, AW2, AW3, AW6, AW9, AW12, AW15, AW18, AW21, AW24, AW27, AW30, AW33, AW37, AW38 GND Ground

Table 4-4 Terminal Functions — By Signal Name

SIGNAL NAME BALL NUMBER SIGNAL NAME BALL NUMBER SIGNAL NAME BALL NUMBER
(nopin) A1 CVDD H31, J30, K29, L6, L28, M7, M9, M25, M27, N6, N8, N10, N12, N14, N16, N18, N22, N24, N26, P7, P9, P13, P15, P17, P19, P21, P23, P25, P27, R8, R10, R12 DDR3ACB05 F14
(nopin) A39 DDR3ACB06 D14
(nopin) AW1 DDR3ACB07 G15
(nopin) AW39 DDR3ACE0 D11
ALTCORECLKN AL2 CVDD R14, R16, R18, R20, R24, R26, T9, T11, T15, T17, T19, T23, T25, T27, U8, U10, U12, U18, U24, U26, V9, V15, V19, V23, V25, V27, W8, W10, W12, W14, W18 DDR3ACE1 F11
ALTCORECLKP AM2 DDR3ACKE0 G12
ARMCLKN B37 DDR3ACKE1 A11
ARMCLKP C37 DDR3ACLKN A25
ARMAVSSHARED† G24 CVDD W20, W24, W26, Y9, Y15, Y17, Y19, Y21, Y23, Y25, Y27, AA8, AA10, AA16, AA18, AA20, AA22, AA24, AA26, AB9, AB11, AB15, AB17, AB19, AB21, AB23, AB25 DDR3ACLKOUTN0 B12
AVDDA1 AF11 DDR3ACLKOUTN1 B13
AVDDA2 N20 DDR3ACLKOUTP0 A12
AVDDA3 N28 DDR3ACLKOUTP1 A13
AVDDA4 AH29 CVDD AB27, AC8, AC10, AC12, AC14, AC16, AC20, AC22, AC24, AC26, AD9, AD13, AD15, AD21, AD23, AD25, AD27, AE8, AE10, AE12, AE14, AE16, AE18, AE20 DDR3ACLKP B25
AVDDA5 AG26 DDR3AD00 G1
AVDDA6 P11 DDR3AD01 H2
AVDDA7 M13 DDR3AD02 F1
AVDDA8 M15 CVDD AE22, AE24, AE26, AF9, AF25, AF27, AG8, AG10, AG28, AH9, AH27, AJ8, AJ10, AJ28, AK7, AK9, AK29, AL6, , AL8, AL30, AM5, AM31 DDR3AD03 G2
AVDDA9 M18 DDR3AD04 H1
AVDDA10 M20 DDR3AD05 E2
AVDDA11 Y28 DDR3AD06 F2
AVDDA12 AB28 CVDD1 T13, T21, U14, U16, U20, V13, V17, V21, W16, AC18, AD17, AD19 DDR3AD07 D2
AVDDA13 AC28 DDR3AD08 E4
AVDDA14 AD28 CVDDT1 R22, U22, W22 DDR3AD09 F4
AVDDA15 AE28 DDR3A_REMAP_EN† A36 DDR3AD10 G3
AVSIFSEL0† M2 DDR3AA00 E8 DDR3AD11 A4
AVSIFSEL1† M1 DDR3AA01 G9 DDR3AD12 B4
BOOTMODE_RSVD† B31 DDR3AA02 G8 DDR3AD13 H3
BOOTMODE00† B30 DDR3AA03 G10 DDR3AD14 D3
BOOTMODE01† D29 DDR3AA04 F9 DDR3AD15 D4
BOOTMODE02† A35 DDR3AA05 F8 DDR3AD16 G4
BOOTMODE03† B29 DDR3AA06 C9 DDR3AD17 H5
BOOTMODE04† E29 DDR3AA07 D9 DDR3AD18 D5
BOOTMODE05† D30 DDR3AA08 B9 DDR3AD19 F5
BOOTMODE06† C30 DDR3AA09 D8 DDR3AD20 G5
BOOTMODE07† A30 DDR3AA10 F10 DDR3AD21 D6
BOOTMODE08† G30 DDR3AA11 A9 DDR3AD22 C5
BOOTMODE09† F31 DDR3AA12 E10 DDR3AD23 B6
BOOTMODE10† E30 DDR3AA13 A10 DDR3AD24 C7
BOOTMODE11† F30 DDR3AA14 B10 DDR3AD25 F7
BOOTMODE12† A31 DDR3AA15 D10 DDR3AD26 F6
BOOTMODE13† F24 DDR3ABA0 B11 DDR3AD27 A8
BOOTMODE14† E24 DDR3ABA1 C11 DDR3AD28 B8
BOOTMODE15† D24 DDR3ABA2 G11 DDR3AD29 G6
BOOTCOMPLETE AF5 DDR3ACAS C13 DDR3AD30 G7
CORECLKSEL AL4 DDR3ACB00 A16 DDR3AD31 D7
CORESEL0 F24 DDR3ACB01 C15 DDR3AD32 E16
CORESEL1 E24 DDR3ACB02 B16 DDR3AD33 G16
CORESEL2 D24 DDR3ACB03 F15 DDR3AD34 F16
CORESEL3 G24 DDR3ACB04 D15 DDR3AD35 G17
DDR3AD36 D16 DDR3ADQS7P A23 DDR3BD02 M37
DDR3AD37 D17 DDR3ADQS8N A15 DDR3BD03 L39
DDR3AD38 F17 DDR3ADQS8P B15 DDR3BD04 N33
DDR3AD39 E18 DDR3AODT0 E12 DDR3BD05 N37
DDR3AD40 C19 DDR3AODT1 G13 DDR3BD06 N36
DDR3AD41 D19 DDR3ARAS A14 DDR3BD07 N38
DDR3AD42 G18 DDR3ARESET B14 DDR3BD08 T32
DDR3AD43 F19 DDR3ARZQ0 H16 DDR3BD09 R32
DDR3AD44 G19 DDR3ARZQ1 H10 DDR3BD10 P35
DDR3AD45 B18 DDR3ARZQ2 H22 DDR3BD11 R39
DDR3AD46 D18 DDR3AVREFSSTL G14 DDR3BD12 R38
DDR3AD47 F18 DDR3AWE F12 DDR3BD13 N32
DDR3AD48 A20 DDR3BA00 AA32 DDR3BD14 R33
DDR3AD49 B20 DDR3BA01 W33 DDR3BD15 P36
DDR3AD50 D20 DDR3BA02 W32 DDR3BD16 T34
DDR3AD51 G20 DDR3BA03 Y34 DDR3BD17 R34
DDR3AD52 C21 DDR3BA04 W34 DDR3BD18 T35
DDR3AD53 E20 DDR3BA05 V34 DDR3BD19 R37
DDR3AD54 F20 DDR3BA06 W36 DDR3BD20 R36
DDR3AD55 G21 DDR3BA07 W37 DDR3BD21 U37
DDR3AD56 C23 DDR3BA08 AA33 DDR3BD22 T36
DDR3AD57 G22 DDR3BA09 Y32 DDR3BD23 U38
DDR3AD58 D23 DDR3BA10 Y38 DDR3BD24 V35
DDR3AD59 F22 DDR3BA11 AA39 DDR3BD25 U36
DDR3AD60 E22 DDR3BA12 Y35 DDR3BD26 U34
DDR3AD61 B22 DDR3BA13 Y39 DDR3BD27 W38
DDR3AD62 F21 DDR3BA14 AA38 DDR3BD28 W39
DDR3AD63 D22 DDR3BA15 Y36 DDR3BD29 U33
DDR3ADQM0 C2 DDR3BBA0 AA37 DDR3BD30 V32
DDR3ADQM1 F3 DDR3BBA1 AA34 DDR3BD31 V36
DDR3ADQM2 A6 DDR3BBA2 AB35 DDR3BD32 AG37
DDR3ADQM3 E6 DDR3BCAS AC36 DDR3BD33 AF36
DDR3ADQM4 C17 DDR3BCB00 AF32 DDR3BD34 AG38
DDR3ADQM5 A18 DDR3BCB01 AF34 DDR3BD35 AG34
DDR3ADQM6 D21 DDR3BCB02 AE32 DDR3BD36 AG36
DDR3ADQM7 A22 DDR3BCB03 AF35 DDR3BD37 AH34
DDR3ADQM8 E14 DDR3BCB04 AE33 DDR3BD38 AH35
DDR3ADQS0N D1 DDR3BCB05 AE36 DDR3BD39 AG32
DDR3ADQS0P E1 DDR3BCB06 AD36 DDR3BD40 AH32
DDR3ADQS1N C3 DDR3BCB07 AE34 DDR3BD41 AJ33
DDR3ADQS1P B3 DDR3BCE0 AB34 DDR3BD42 AH36
DDR3ADQS2N B5 DDR3BCE1 AA36 DDR3BD43 AJ34
DDR3ADQS2P A5 DDR3BCKE0 AB39 DDR3BD44 AJ36
DDR3ADQS3N A7 DDR3BCKE1 AB38 DDR3BD45 AH39
DDR3ADQS3P B7 DDR3BCLKN AR39 DDR3BD46 AH38
DDR3ADQS4N B17 DDR3BCLKOUTN0 AD39 DDR3BD47 AJ37
DDR3ADQS4P A17 DDR3BCLKOUTN1 AC38 DDR3BD48 AK39
DDR3ADQS5N A19 DDR3BCLKOUTP0 AD38 DDR3BD49 AK38
DDR3ADQS5P B19 DDR3BCLKOUTP1 AC39 DDR3BD50 AK36
DDR3ADQS6N B21 DDR3BCLKP AR38 DDR3BD51 AK35
DDR3ADQS6P A21 DDR3BD00 L38 DDR3BD52 AL34
DDR3ADQS7N B23 DDR3BD01 N34 DDR3BD53 AL36
DDR3BD54 AL37 DVDD15 L32, M11, M17, M19, M31, P29, P31, R28, R30, T29, T31, U28, U30, V29, V31, W28, W30, Y29, Y31, AA28, AA30, AB29, AB31, AC30, AD29, AD31, AE30, AF29 EMIFD09 K38
DDR3BD55 AL33 EMIFD10 K36
DDR3BD56 AN34 EMIFD11 L36
DDR3BD57 AN36 EMIFD12 L35
DDR3BD58 AN33 DVDD15 AF31, AG30, AH31, AJ30, AK31, AL32 EMIFD13 M34
DDR3BD59 AM34 EMIFD14 M36
DDR3BD60 AM35 DVDD18 H25, H27, J26, J28, J32, K25, K27, K31, L24, L26, L30, M29, N30, R6, T7, U6, V5, V7, W6, Y5, Y7, AA6, AB5, AB7, AC6, AD7, AE6, AF7, AG6, AJ26, AK27, AL26, AL28, AM27, AM29 EMIFD15 M35
DDR3BD61 AM38 EMIFOE E37
DDR3BD62 AM36 EMIFRNW F33
DDR3BD63 AN37 EMIFWAIT0 E38
DDR3BDQM0 N39 DVDD33 AA14 EMIFWAIT1 D39
DDR3BDQM1 P34 EMIFA00 F34 EMIFWE F36
DDR3BDQM2 U39 EMIFA01 F37 EMU00 AA2
DDR3BDQM3 U32 EMIFA02 G36 EMU01 AB2
DDR3BDQM4 AG33 EMIFA03 E39 EMU02 Y3
DDR3BDQM5 AG39 EMIFA04 E34 EMU03 Y4
DDR3BDQM6 AK34 EMIFA05 J34 EMU04 W3
DDR3BDQM7 AM39 EMIFA06 H35 EMU05 W4
DDR3BDQM8 AE37 EMIFA07 K33 EMU06 V4
DDR3BDQS0N M39 EMIFA08 C35 EMU07 U4
DDR3BDQS0P M38 EMIFA09 G37 EMU08 U3
DDR3BDQS1N P38 EMIFA10 F38 EMU09 T3
DDR3BDQS1P P39 EMIFA11 D35 EMU10 AB4
DDR3BDQS2N T38 EMIFA12 H36 EMU11 AA3
DDR3BDQS2P T39 EMIFA13 E35 EMU12 U5
DDR3BDQS3N V38 EMIFA14 G38 EMU13 T4
DDR3BDQS3P V39 EMIFA15 F39 EMU14 AB3
DDR3BDQS4N AF39 EMIFA16 K34 EMU15 R3
DDR3BDQS4P AF38 EMIFA17 F35 EMU16 T5
DDR3BDQS5N AJ38 EMIFA18 J35 EMU17 R4
DDR3BDQS5P AJ39 EMIFA19 G39 EMU18 AA4
DDR3BDQS6N AL38 EMIFA20 C36 GPIO00 F29
DDR3BDQS6P AL39 EMIFA21 J36 GPIO01 B30
DDR3BDQS7N AN39 EMIFA22 H38 GPIO02 D29
DDR3BDQS7P AN38 EMIFA23 D36 GPIO03 A35
DDR3BDQS8N AE38 EMIFBE0 H34 GPIO04 B29
DDR3BDQS8P AE39 EMIFBE1 H33 GPIO05 E29
DDR3BODT0 AC33 EMIFCE0 G33 GPIO06 D30
DDR3BODT1 AD34 EMIFCE1 G32 GPIO07 C30
DDR3BRAS AD32 EMIFCE2 G34 GPIO08 A30
DDR3BRESET AC32 EMIFCE3 E36 GPIO09 G30
DDR3BRZQ0 AA31 EMIFD00 M32 GPIO10 F31
DDR3BRZQ1 P32 EMIFD01 J37 GPIO11 E30
DDR3BRZQ2 AK32 EMIFD02 L33 GPIO12 F30
DDR3BVREFSSTL AC31 EMIFD03 L34 GPIO13 A31
DDR3BWE AC37 EMIFD04 H39 GPIO14 E32
DVDD15 H7, H9, H11, H13, H15, H17, H19, H21, H23, J6, J8, J10, J12, J14, J16, J18, J20, J22, K7, K9, K11, K13, K15, K17, K19, K21, K23, L8, L10, L12, L14, L16, L18, L20 EMIFD05 J38 GPIO15 B31
EMIFD06 K37 GPIO16 A36
EMIFD07 J39 GPIO17 A32
EMIFD08 K39 GPIO18 C31
GPIO19 B32 HYP1RXP0 AU8 RIORXP2 AW23
GPIO20 A33 HYP1RXP1 AV7 RIORXP3 AV22
GPIO21 D33 HYP1RXP2 AU5 RIOTXN0 AT24
GPIO22 D31 HYP1RXP3 AV4 RIOTXN1 AR23
GPIO23 B35 HYP1RXPMCLK AF3 RIOTXN2 AP22
GPIO24 B33 HYP1RXPMDAT AF4 RIOTXN3 AT21
GPIO25 E31 HYP1TXFLCLK AH3 RIOTXP0 AT25
GPIO26 A34 HYP1TXFLDAT AH2 RIOTXP1 AR24
GPIO27 D32 HYP1TXN0 AT6 RIOTXP2 AP23
GPIO28 C33 HYP1TXN1 AP5 RIOTXP3 AT22
GPIO29 C34 HYP1TXN2 AR4 RSV000 P2
GPIO30 B36 HYP1TXN3 AT3 RSV001 P1
GPIO31 B34 HYP1TXP0 AT7 RSV002 AN4
HOUT AE5 HYP1TXP1 AP6 RSV003 AM4
HYP0CLKN AT10 HYP1TXP2 AR5 RSV004 B24
HYP0CLKP AT9 HYP1TXP3 AT4 RSV005 A24
HYP0REFRES AM9 HYP1TXPMCLK AH1 RSV006 AP38
HYP0RXFLCLK AJ5 HYP1TXPMDAT AF2 RSV007 AP39
HYP0RXFLDAT AJ4 LENDIAN† F29 RSV008 AU34
HYP0RXN0 AW10 LRESETNMIEN AD4 RSV009 AT34
HYP0RXN1 AU10 LRESET AE4 RSV010 C38
HYP0RXN2 AV9 MAINPLLODSEL† E32 RSV011 D38
HYP0RXN3 AW7 MDCLK AP31 RSV012 AK5
HYP0RXP0 AW11 MDIO AR32 RSV013 F23
HYP0RXP1 AU11 NMI AD5 RSV014 E23
HYP0RXP2 AV10 PACLKSEL AN30 RSV015 E33
HYP0RXP3 AW8 PASSCLKN AV34 RSV016 F32
HYP0RXPMCLK AJ2 PASSCLKP AV33 RSV017 F26
HYP0RXPMDAT AG3 PCIECLKN AW32 RSV018 G26
HYP0TXFLCLK AJ3 PCIECLKP AW31 RSV019 AN10
HYP0TXFLDAT AG5 PCIEREFRES AM26 RSV020 AM7
HYP0TXN0 AP11 PCIERXN0 AU31 RSV021 AM23
HYP0TXN1 AR10 PCIERXN1 AV30 RSV022 AM28
HYP0TXN2 AP8 PCIERXP0 AU32 RSV023 AM25
HYP0TXN3 AR7 PCIERXP1 AV31 RSV024 AM16
HYP0TXP0 AP12 PCIETXN0 AT30 RSV025 AM14
HYP0TXP1 AR11 PCIETXN1 AR29 RSV026 AN19
HYP0TXP2 AP9 PCIETXP0 AT31 RSV027 D12
HYP0TXP3 AR8 PCIETXP1 AR30 RSV028 D13
HYP0TXPMCLK AH5 POR AK4 RSV029 F13
HYP0TXPMDAT AJ1 RESETFULL AD3 RSV030 AD35
HYP1CLKN AW5 RESETSTAT AC5 RSV031 AC34
HYP1CLKP AW4 RESET AD2 RSV032 AB32
HYP1REFRES AM6 RIOREFRES AM21 RSV060
(66AK2H12/06 only) 		AV19
HYP1RXFLCLK AH4 RIORXN0 AV24 RSV061
(66AK2H12/06 only) 		AV18
HYP1RXFLDAT AG2 RIORXN1 AU22 RSV062
(66AK2H12/06 only) 		AT19
HYP1RXN0 AU7 RIORXN2 AW22 RSV063
(66AK2H12/06 only) 		AT18
HYP1RXN1 AV6 RIORXN3 AV21 RSV064
(66AK2H12/06 only) 		AW20
HYP1RXN2 AU4 RIORXP0 AV25 RSV065
(66AK2H12/06 only) 		AW19
HYP1RXN3 AV3 RIORXP1 AU23 RSV066
(66AK2H12/06 only) 		AR20
RSV067
(66AK2H12/06 only) 		AR19 RSV189 AR1 SPI2DIN F28
RSV068
(66AK2H12/06 only) 		AN16 RSV190 AT1 SPI2DOUT G28
RSV069
(66AK2H12/06 only) 		AM19 RSV191 AP34 SPI2SCS0 B28
RSV070
(66AK2H12/06 only)		 AU19 RSV192 AM30 SPI2SCS1 D28
RSV071
(66AK2H12/06 only) 		AU20 RSV193 AP32 SPI2SCS2 A29
RSV072
(66AK2H12/06 only) 		AT33 RSV194 AN32 SPI2SCS3 E25
RSV073
(66AK2H12/06 only) 		AR34 RSV195 AP33 SRIOSGMIICLKN AW35
RSV74 AT37 SCL0 N1 SRIOSGMIICLKP AW34
RSV75 AT35 SCL1 N4 SYSCLKN AK3
RSV76 AU36 SCL2 P4 SYSCLKOUT AK1
RSV77 AV37 SDA1 N2 SYSCLKP AL3
RSV78 AU37 SDA2 N3 TCK AE1
RSV79 AV36 SGMII0RXN AW28 TDI AG1
RSV80 AU35 SGMII0RXP AW29 TDO AF1
RSV81 AW36 SGMII0TXN AU28 TIMI0 M2
RSV099 AM11 SGMII0TXP AU29 TIMI1 M1
RSV161 AW16 SGMII1RXN AV27 TIMO0 M3
RSV162 AW17 SGMII1RXP AV28 TIMO1 M4
RSV163 AU16 SGMII1TXN AT27 TMS AE2
RSV164 AU17 SGMII1TXP AT28 TRST AD1
RSV165 AV15 SGMII2RXN AU25 TSCOMPOUT AB1
RSV166 AV16 SGMII2RXP AU26 TSPUSHEVT0 AC2
RSV167 AW13 SGMII2TXN AR26 TSPUSHEVT1 AC1
RSV168 AW14 SGMII2TXP AR27 TSREFCLKN AL1
RSV169 AU13 SGMII3RXN AW25 TSREFCLKP AM1
RSV171 AV12 SGMII3RXP AW26 TSRXCLKOUT0N AP1
RSV170 AU14 SGMII3TXN AP25 TSRXCLKOUT0P AN1
RSV172 AV13 SGMII3TXP AP26 TSRXCLKOUT1N AP3
RSV173 AP17 SGMIIREFRES AM24 TSRXCLKOUT1P AN3
RSV174 AP18 SPI0CLK B26 TSSYNCEVT AC3
RSV175 AR16 SPI0DIN A26 UART0CTS L1
RSV176 AR17 SPI0DOUT A27 UART0RTS L4
RSV177 AT15 SPI0SCS0 F25 UART0RXD K4
RSV178 AT16 SPI0SCS1 C25 UART0TXD K2
RSV179 AP14 SPI0SCS2 E26 UART1CTS K1
RSV180 AP15 SPI0SCS3 D26 UART1RTS M5
RSV181 AR13 SPI1CLK C28 UART1RXD L2
RSV182 AR14 SPI1DIN F27 UART1TXD K3
RSV183 AT12 SPI1DOUT A28 USBCLKM V2
RSV184 AT13 SPI1SCS0 B27 USBCLKP W2
RSV185 AM15 SPI1SCS1 C27 USBDM T2
RSV186 AR2 SPI1SCS2 D27 USBDP U2
RSV187 AP2 SPI1SCS3 E27 USBDRVVBUS L3
RSV188 AC4 SPI2CLK D25 USBID0 R1
USBRESREF AA1 VSS V14, V16, V18, V20, V22, V24, V26, V28, V30, V33, V37, W5, W7, W9, W11, W13, W15, W17, W19, W21, W23, W25, W27, W29, W31, W35, Y2, Y6, Y8, Y10 VDDAHV AK11, AK13, AK15, AK17, AK19, AK21, AK23, AK25, AL10, AL12, AL14, AL16, AL18, AL20, AL22, AL24
USBRX0M Y1
USBRX0P W1
USBTX0M V1 VDDALV AF13, AF15, AF17, AF19, AF21, AF23, AG12, AG14, AG16, AG18, AG20, AG22, AH11, AH13, AH15, AH17, AH19, AH21, AH23, AH25, AJ12, AJ14, AJ16, AJ18, AJ20, AJ22, AJ24
USBTX0P U1 VSS Y12, Y14, Y16, Y18, Y20, Y22, Y24, Y26, Y30, Y33, Y37, AA5, AA7, AA9, AA11, AA13, AA15, AA17, AA19, AA21, AA23, AA25, AA27, AA29, AA35, AB6, AB8
USBVBUS T1
VCL AP36
VCNTL0 AT39 VDDUSB AB13
VCNTL1 AR37 VSS AB10, AB12, AB14, AB16, AB18, AB20, AB22, AB24, AB26, AB30, AB33, AB36, AB37, AC7, AC9, AC11, AC13, AC15, AC17, AC19, AC21, AC23, AC25, AC27 VNWA1 AG24
VCNTL2 AR36 VSS AT23, AT26, AT29, AT32, AT36, AU1, AU2, AU3, AU6, AU9, AU12, AU15, AU18, AU21, AU24, AU27, AU30, AU33, AU39, AV1, AV2, AV5, AV8, AV11
VCNTL3 AT38
VCNTL4 AU38
VCNTL5 AR35 VSS AC29, AC35, AD6, AD8, AD10, AD12, AD14, AD16, AD18, AD20, AD22, AD24, AD26, AD30, AD33, AD37, AE3, AE7, AE9, AE11, AE13, AE15, AE17, AE19
VD AP35 VSS AV14, AV17, AV20, AV23, AV26, AV29 , AV32, AV35, AV38, AV39, AW2, AW3, AW6, AW9, AW12, AW15, AW18, AW21, AW24, AW27, AW30, AW33, AW37, AW38
VNWA2 AD11
VNWA3 M23
VNWA4 V11 VSS AE21, AE23, AE25, AE27, AE29, AE31, AE35, AF6, AF8, AF10, AF12, AF14, AF16, AF18, AF20, AF22, AF24, AF26, AF28, AF30, AF33, AF37, AG4, AG7
VP AA12 XFICLKN
(66AK2H14 only)		 AU20
VPH Y13
VPP L22, M21 XFICLKP
(66AK2H14 only)		 AU19
VPTX Y11 VSS AG9, AG11, AG13, AG15, AG17, AG19, AG21, AG23, AG25, AG27, AG29, AG31, AG35, AH6, AH7, AH8, AH10, AH12, AH14, AH16, AH18, AH20, AH22, AH24
VSS A2, A3, A37, A38, B1, B2, B38, B39, C1, C4, C6, C8, C10, C12, C14, C16, C18, C20, C22, C24, C26, C29, C32, C39, D34, D37, E3, E5, E7, E9, E11, E13, E15, E17, E19 XFIMDCLK
(66AK2H14 only)		 AR34
XFIMDIO
(66AK2H14 only)		 AT33
VSS AH26, AH28, AH30, AH33, AH37, AJ6, AJ7, AJ9, AJ11, AJ13, AJ15, AJ17, AJ19, AJ21, AJ23, AJ25, AJ27, AJ29, AJ31, AJ32, AJ35, AK2, AK6, AK8, AK10
VSS E21, E28, G23, G25, G27, G29, G31, G35, H4, H6, H8, H12, H14, H18, H20, H24, H26, H28, H29, H30, H32, H37, J1, J2, J3, J4, J5, J7, J9, J11, J13, J15, J17, J19 XFIREFRES0
(66AK2H14 only)		 AN16
XFIREFRES1
(66AK2H14 only)		 AM19
VSS AK12, AK14, AK16, AK18, AK20, AK22, AK24, AK26, AK28, AK30, AK33, AK37, AL5, AL7, AL9, AL11, AL13, AL15, AL17, AL19, AL21, AL23, AL25, AL27, AL29
VSS J21, J23, J24, J25, J27, J29, J31, J33, K5, K6, K8, K10, K12, K14, K16, K18, K20, K22, K24, K26, K28, K30, K32, K35, L5, L7, L9, L11, L13, L15, L17, L19, L21, L23 XFIRXN0
(66AK2H14 only)		 AV19
XFIRXN1
(66AK2H14 only)		 AW20
VSS AL31, AL35, AM3, AM8, AM10, AM12, AM13, AM17, AM18, AM20, AM22, AM32, AM33, AM37, AN2, AN5, AN6, AN7, AN8, AN9, AN11, AN12, AN13, AN14
VSS L25, L27, L29, L31, L37, M6, M8, M10, M12, M14, M16, M22, M24, M26, M28, M30, M33, N5, N7, N9, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29 XFIRXP0
(66AK2H14 only)		 AV18
XFIRXP1
(66AK2H14 only)		 AW19
VSS AN15, AN17, AN18, AN20, AN21, AN22, AN23, AN24, AN25, AN26, AN27, AN28, AN29, AN31, AN35, AP4, AP7, AP10, AP13, AP16, AP19, AP20, AP21, AP24
VSS N31, N35, P5, P6, P8, P10, P12, P14, P16, P18, P20, P22, P24, P26, P28, P30, P33, P37, R2, R5, R7, R9, R11, R13, R15, R17, R19, R21, R23, R25, R27, R29, R31, R35 XFITXN0
(66AK2H14 only)		 AT19
XFITXN1
(66AK2H14 only)		 AR20
VSS AP27, AP28, AP29, AP30, AP37, AR3, AR6, AR9, AR12, AR15, AR18, AR21, AR22, AR25, AR28, AR31, AR33, AT2, AT5, AT8, AT11, AT14, AT17, AT20
VSS T6, T8, T10, T12, T14, T16, T18, T20, T22, T24, T26, T28, T30, T33, T37, U7, U9, U11, U13, U15, U17, U19, U21, U23, U25, U27, U29, U31, U35, V3, V6, V8, V10, V12 XFITXP0
(66AK2H14 only)		 AT18
XFITXP1
(66AK2H14 only)		 AR19

Table 4-5 Terminal Functions — By  Ball Number

BALL NUMBER SIGNAL NAME BALL NUMBER SIGNAL NAME BALL NUMBER SIGNAL NAME
A1 (nopin) B6 DDR3AD23 C10 VSS
A2 VSS B7 DDR3ADQS3P C11 DDR3ABA1
A3 VSS B8 DDR3AD28 C12 VSS
A4 DDR3AD11 B9 DDR3AA08 C13 DDR3ACAS
A5 DDR3ADQS2P B10 DDR3AA14 C14 VSS
A6 DDR3ADQM2 B11 DDR3ABA0 C15 DDR3ACB01
A7 DDR3ADQS3N B12 DDR3ACLKOUTN0 C16 VSS
A8 DDR3AD27 B13 DDR3ACLKOUTN1 C17 DDR3ADQM4
A9 DDR3AA11 B14 DDR3ARESET C18 VSS
A10 DDR3AA13 B15 DDR3ADQS8P C19 DDR3AD40
A11 DDR3ACKE1 B16 DDR3ACB02 C20 VSS
A12 DDR3ACLKOUTP0 B17 DDR3ADQS4N C21 DDR3AD52
A13 DDR3ACLKOUTP1 B18 DDR3AD45 C22 VSS
A14 DDR3ARAS B19 DDR3ADQS5P C23 DDR3AD56
A15 DDR3ADQS8N B20 DDR3AD49 C24 VSS
A16 DDR3ACB00 B21 DDR3ADQS6N C25 SPI0SCS1
A17 DDR3ADQS4P B22 DDR3AD61 C26 VSS
A18 DDR3ADQM5 B23 DDR3ADQS7N C27 SPI1SCS1
A19 DDR3ADQS5N B24 RSV004 C28 SPI1CLK
A20 DDR3AD48 B25 DDR3ACLKP C29 VSS
A21 DDR3ADQS6P B26 SPI0CLK C30 GPIO07
A22 DDR3ADQM7 B27 SPI1SCS0 C30 BOOTMODE06†
A23 DDR3ADQS7P B28 SPI2SCS0 C31 GPIO18
A24 RSV005 B29 GPIO04 C31 EMU20†
A25 DDR3ACLKN B29 BOOTMODE03† C32 VSS
A26 SPI0DIN B30 GPIO01 C33 GPIO28
A27 SPI0DOUT B30 BOOTMODE00† C33 EMU30†
A28 SPI1DOUT B31 GPIO15 C34 GPIO29
A29 SPI2SCS2 B31 BOOTMODE_RSVD† C34 EMU31†
A30 GPIO08 B32 GPIO19 C35 EMIFA08
A30 BOOTMODE07† B32 EMU21† C36 EMIFA20
A31 GPIO13 B33 GPIO24 C37 ARMCLKP
A31 BOOTMODE12† B33 EMU26† C38 RSV010
A32 GPIO17 B34 GPIO31 C39 VSS
A32 EMU19† B34 EMU33† D1 DDR3ADQS0N
A33 GPIO20 B35 GPIO23 D2 DDR3AD07
A33 EMU22† B35 EMU25† D3 DDR3AD14
A34 GPIO26 B36 GPIO30 D4 DDR3AD15
A34 EMU28† B36 EMU32† D5 DDR3AD18
A35 GPIO03 B37 ARMCLKN D6 DDR3AD21
A35 BOOTMODE02† B38 VSS D7 DDR3AD31
A36 GPIO16 B39 VSS D8 DDR3AA09
A36 DDR3A_REMAP_EN† C1 VSS D9 DDR3AA07
A37 VSS C2 DDR3ADQM0 D10 DDR3AA15
A38 VSS C3 DDR3ADQS1N D11 DDR3ACE0
A39 (nopin) C4 VSS D12 RSV027
B1 VSS C5 DDR3AD22 D13 RSV028
B2 VSS C6 VSS D14 DDR3ACB06
B3 DDR3ADQS1P C7 DDR3AD24 D15 DDR3ACB04
B4 DDR3AD12 C8 VSS D16 DDR3AD36
B5 DDR3ADQS2N C9 DDR3AA06 D17 DDR3AD37
D18 DDR3AD46 E25 SPI2SCS3 F31 BOOTMODE09†
D19 DDR3AD41 E26 SPI0SCS2 F32 RSV016
D20 DDR3AD50 E27 SPI1SCS3 F33 EMIFRNW
D21 DDR3ADQM6 E28 VSS F34 EMIFA00
D22 DDR3AD63 E29 GPIO05 F35 EMIFA17
D23 DDR3AD58 E29 BOOTMODE04† F36 EMIFWE
D24 CORESEL2 E30 GPIO11 F37 EMIFA01
D25 SPI2CLK E30 BOOTMODE10† F38 EMIFA10
D26 SPI0SCS3 E31 GPIO25 F39 EMIFA15
D27 SPI1SCS2 E31 EMU27† G1 DDR3AD00
D28 SPI2SCS1 E32 GPIO14 G2 DDR3AD03
D29 GPIO02 E32 MAINPLLODSEL† G3 DDR3AD10
D29 BOOTMODE01† E33 RSV015 G4 DDR3AD16
D30 GPIO06 E34 EMIFA04 G5 DDR3AD20
D30 BOOTMODE05† E35 EMIFA13 G6 DDR3AD29
D31 GPIO22 E36 EMIFCE3 G7 DDR3AD30
D31 EMU24† E37 EMIFOE G8 DDR3AA02
D32 GPIO27 E38 EMIFWAIT0 G9 DDR3AA01
D32 EMU29† E39 EMIFA03 G10 DDR3AA03
D33 GPIO21 F1 DDR3AD02 G11 DDR3ABA2
D33 EMU23† F2 DDR3AD06 G12 DDR3ACKE0
D34 VSS F3 DDR3ADQM1 G13 DDR3AODT1
D35 EMIFA11 F4 DDR3AD09 G14 DDR3AVREFSSTL
D36 EMIFA23 F5 DDR3AD19 G15 DDR3ACB07
D37 VSS F6 DDR3AD26 G16 DDR3AD33
D38 RSV011 F7 DDR3AD25 G17 DDR3AD35
D39 EMIFWAIT1 F8 DDR3AA05 G18 DDR3AD42
E1 DDR3ADQS0P F9 DDR3AA04 G19 DDR3AD44
E2 DDR3AD05 F10 DDR3AA10 G20 DDR3AD51
E3 VSS F11 DDR3ACE1 G21 DDR3AD55
E4 DDR3AD08 F12 DDR3AWE G22 DDR3AD57
E5 VSS F13 RSV029 G23 VSS
E6 DDR3ADQM3 F14 DDR3ACB05 G24 CORESEL3
E7 VSS F15 DDR3ACB03 G24 ARMAVSSHARED†
E8 DDR3AA00 F16 DDR3AD34 G25 VSS
E9 VSS F17 DDR3AD38 G26 RSV018
E10 DDR3AA12 F18 DDR3AD47 G27 VSS
E11 VSS F19 DDR3AD43 G28 SPI2DOUT
E12 DDR3AODT0 F20 DDR3AD54 G29 VSS
E13 VSS F21 DDR3AD62 G30 GPIO09
E14 DDR3ADQM8 F22 DDR3AD59 G30 BOOTMODE08†
E15 VSS F23 RSV013 G31 VSS
E16 DDR3AD32 F24 CORESEL0 G32 EMIFCE1
E17 VSS F25 SPI0SCS0 G33 EMIFCE0
E18 DDR3AD39 F26 RSV017 G34 EMIFCE2
E19 VSS F27 SPI1DIN G35 VSS
E20 DDR3AD53 F28 SPI2DIN G36 EMIFA02
E21 VSS F29 GPIO00 G37 EMIFA09
E22 DDR3AD60 F30 GPIO12 G38 EMIFA14
E23 RSV014 F30 BOOTMODE11† G39 EMIFA19
E24 CORESEL1 F31 GPIO10 H1 DDR3AD04
H2 DDR3AD01 J13 VSS K24 VSS
H3 DDR3AD13 J14 DVDD15 K25 DVDD18
H4 VSS J15 VSS K26 VSS
H5 DDR3AD17 J16 DVDD15 K27 DVDD18
H6 VSS J17 VSS K28 VSS
H7 DVDD15 J18 DVDD15 K29 CVDD
H8 VSS J19 VSS K30 VSS
H9 DVDD15 J20 DVDD15 K31 DVDD18
H10 DDR3ARZQ1 J21 VSS K32 VSS
H11 DVDD15 J22 DVDD15 K33 EMIFA07
H12 VSS J23 VSS K34 EMIFA16
H13 DVDD15 J24 VSS K35 VSS
H14 VSS J25 VSS K36 EMIFD10
H15 DVDD15 J26 DVDD18 K37 EMIFD06
H16 DDR3ARZQ0 J27 VSS K38 EMIFD09
H17 DVDD15 J28 DVDD18 K39 EMIFD08
H18 VSS J29 VSS L1 UART0CTS
H19 DVDD15 J30 CVDD L2 UART1RXD
H20 VSS J31 VSS L3 USBDRVVBUS
H21 DVDD15 J32 DVDD18 L4 UART0RTS
H22 DDR3ARZQ2 J33 VSS L5 VSS
H23 DVDD15 J34 EMIFA05 L6 CVDD
H24 VSS J35 EMIFA18 L7 VSS
H25 DVDD18 J36 EMIFA21 L8 DVDD15
H26 VSS J37 EMIFD01 L9 VSS
H27 DVDD18 J38 EMIFD05 L10 DVDD15
H28 VSS J39 EMIFD07 L11 VSS
H29 VSS K1 UART1CTS L12 DVDD15
H30 VSS K2 UART0TXD L13 VSS
H31 CVDD K3 UART1TXD L14 DVDD15
H32 VSS K4 UART0RXD L15 VSS
H33 EMIFBE1 K5 VSS L16 DVDD15
H34 EMIFBE0 K6 VSS L17 VSS
H35 EMIFA06 K7 DVDD15 L18 DVDD15
H36 EMIFA12 K8 VSS L19 VSS
H37 VSS K9 DVDD15 L20 DVDD15
H38 EMIFA22 K10 VSS L21 VSS
H39 EMIFD04 K11 DVDD15 L22 VPP
J1 VSS K12 VSS L23 VSS
J2 VSS K13 DVDD15 L24 DVDD18
J3 VSS K14 VSS L25 VSS
J4 VSS K15 DVDD15 L26 DVDD18
J5 VSS K16 VSS L27 VSS
J6 DVDD15 K17 DVDD15 L28 CVDD
J7 VSS K18 VSS L29 VSS
J8 DVDD15 K19 DVDD15 L30 DVDD18
J9 VSS K20 VSS L31 VSS
J10 DVDD15 K21 DVDD15 L32 DVDD15
J11 VSS K22 VSS L33 EMIFD02
J12 DVDD15 K23 DVDD15 L34 EMIFD03
L35 EMIFD12 N6 CVDD P18 VSS
L36 EMIFD11 N7 VSS P19 CVDD
L37 VSS N8 CVDD P20 VSS
L38 DDR3BD00 N9 VSS P21 CVDD
L39 DDR3BD03 N10 CVDD P22 VSS
M1 TIMI1 N11 VSS P23 CVDD
M1 AVSIFSEL1† N12 CVDD P24 VSS
M2 TIMI0 N13 VSS P25 CVDD
M2 AVSIFSEL0† N14 CVDD P26 VSS
M3 TIMO0 N15 VSS P27 CVDD
M4 TIMO1 N16 CVDD P28 VSS
M5 UART1RTS N17 VSS P29 DVDD15
M6 VSS N18 CVDD P30 VSS
M7 CVDD N19 VSS P31 DVDD15
M8 VSS N20 AVDDA2 P32 DDR3BRZQ1
M9 CVDD N21 VSS P33 VSS
M10 VSS N22 CVDD P34 DDR3BDQM1
M11 DVDD15 N23 VSS P35 DDR3BD10
M12 VSS N24 CVDD P36 DDR3BD15
M13 AVDDA7 N25 VSS P37 VSS
M14 VSS N26 CVDD P38 DDR3BDQS1N
M15 AVDDA8 N27 VSS P39 DDR3BDQS1P
M16 VSS N28 AVDDA3 R1 USBID0
M17 DVDD15 N29 VSS R2 VSS
M18 AVDDA9 N30 DVDD18 R3 EMU15
M19 DVDD15 N31 VSS R4 EMU17
M20 AVDDA10 N32 DDR3BD13 R5 VSS
M21 VPP N33 DDR3BD04 R6 DVDD18
M22 VSS N34 DDR3BD01 R7 VSS
M23 VNWA3 N35 VSS R8 CVDD
M24 VSS N36 DDR3BD06 R9 VSS
M25 CVDD N37 DDR3BD05 R10 CVDD
M26 VSS N38 DDR3BD07 R11 VSS
M27 CVDD N39 DDR3BDQM0 R12 CVDD
M28 VSS P1 RSV001 R13 VSS
M29 DVDD18 P2 RSV000 R14 CVDD
M30 VSS P3 SDA0 R15 VSS
M31 DVDD15 P4 SCL2 R16 CVDD
M32 EMIFD00 P5 VSS R17 VSS
M33 VSS P6 VSS R18 CVDD
M34 EMIFD13 P7 CVDD R19 VSS
M35 EMIFD15 P8 VSS R20 CVDD
M36 EMIFD14 P9 CVDD R21 VSS
M37 DDR3BD02 P10 VSS R22 CVDDT1
M38 DDR3BDQS0P P11 AVDDA6 R23 VSS
M39 DDR3BDQS0N P12 VSS R24 CVDD
N1 SCL0 P13 CVDD R25 VSS
N2 SDA1 P14 VSS R26 CVDD
N3 SDA2 P15 CVDD R27 VSS
N4 SCL1 P16 VSS R28 DVDD15
N5 VSS P17 CVDD R29 VSS
R30 DVDD15 U3 EMU08 V15 CVDD
R31 VSS U4 EMU07 V16 VSS
R32 DDR3BD09 U5 EMU12 V17 CVDD1
R33 DDR3BD14 U6 DVDD18 V18 VSS
R34 DDR3BD17 U7 VSS V19 CVDD
R35 VSS U8 CVDD V20 VSS
R36 DDR3BD20 U9 VSS V21 CVDD1
R37 DDR3BD19 U10 CVDD V22 VSS
R38 DDR3BD12 U11 VSS V23 CVDD
R39 DDR3BD11 U12 CVDD V24 VSS
T1 USBVBUS U13 VSS V25 CVDD
T2 USBDM U14 CVDD1 V26 VSS
T3 EMU09 U15 VSS V27 CVDD
T4 EMU13 U16 CVDD1 V28 VSS
T5 EMU16 U17 VSS V29 DVDD15
T6 VSS U18 CVDD V30 VSS
T7 DVDD18 U19 VSS V31 DVDD15
T8 VSS U20 CVDD1 V32 DDR3BD30
T9 CVDD U21 VSS V33 VSS
T10 VSS U22 CVDDT1 V34 DDR3BA05
T11 CVDD U23 VSS V35 DDR3BD24
T12 VSS U24 CVDD V36 DDR3BD31
T13 CVDD1 U25 VSS V37 VSS
T14 VSS U26 CVDD V38 DDR3BDQS3N
T15 CVDD U27 VSS V39 DDR3BDQS3P
T16 VSS U28 DVDD15 W1 USBRX0P
T17 CVDD U29 VSS W2 USBCLKP
T18 VSS U30 DVDD15 W3 EMU04
T19 CVDD U31 VSS W4 EMU05
T20 VSS U32 DDR3BDQM3 W5 VSS
T21 CVDD1 U33 DDR3BD29 W6 DVDD18
T22 VSS U34 DDR3BD26 W7 VSS
T23 CVDD U35 VSS W8 CVDD
T24 VSS U36 DDR3BD25 W9 VSS
T25 CVDD U37 DDR3BD21 W10 CVDD
T26 VSS U38 DDR3BD23 W11 VSS
T27 CVDD U39 DDR3BDQM2 W12 CVDD
T28 VSS V1 USBTX0M W13 VSS
T29 DVDD15 V2 USBCLKM W14 CVDD
T30 VSS V3 VSS W15 VSS
T31 DVDD15 V4 EMU06 W16 CVDD1
T32 DDR3BD08 V5 DVDD18 W17 VSS
T33 VSS V6 VSS W18 CVDD
T34 DDR3BD16 V7 DVDD18 W19 VSS
T35 DDR3BD18 V8 VSS W20 CVDD
T36 DDR3BD22 V9 CVDD W21 VSS
T37 VSS V10 VSS W22 CVDDT1
T38 DDR3BDQS2N V11 VNWA4 W23 VSS
T39 DDR3BDQS2P V12 VSS W24 CVDD
U1 USBTX0P V13 CVDD1 W25 VSS
U2 USBDP V14 VSS W26 CVDD
W27 VSS Y39 DDR3BA13 AB12 VSS
W28 DVDD15 AA1 USBRESREF AB13 VDDUSB
W29 VSS AA2 EMU00 AB14 VSS
W30 DVDD15 AA3 EMU11 AB15 CVDD
W31 VSS AA4 EMU18 AB16 VSS
W32 DDR3BA02 AA5 VSS AB17 CVDD
W33 DDR3BA01 AA6 DVDD18 AB18 VSS
W34 DDR3BA04 AA7 VSS AB19 CVDD
W35 VSS AA8 CVDD AB20 VSS
W36 DDR3BA06 AA9 VSS AB21 CVDD
W37 DDR3BA07 AA10 CVDD AB22 VSS
W38 DDR3BD27 AA11 VSS AB23 CVDD
W39 DDR3BD28 AA12 VP AB24 VSS
Y1 USBRX0M AA13 VSS AB25 CVDD
Y2 VSS AA14 DVDD33 AB26 VSS
Y3 EMU02 AA15 VSS AB27 CVDD
Y4 EMU03 AA16 CVDD AB28 AVDDA12
Y5 DVDD18 AA17 VSS AB29 DVDD15
Y6 VSS AA18 CVDD AB30 VSS
Y7 DVDD18 AA19 VSS AB31 DVDD15
Y8 VSS AA20 CVDD AB32 RSV032
Y9 CVDD AA21 VSS AB33 VSS
Y10 VSS AA22 CVDD AB34 DDR3BCE0
Y11 VPTX AA23 VSS AB35 DDR3BBA2
Y12 VSS AA24 CVDD AB36 VSS
Y13 VPH AA25 VSS AB37 VSS
Y14 VSS AA26 CVDD AB38 DDR3BCKE1
Y15 CVDD AA27 VSS AB39 DDR3BCKE0
Y16 VSS AA28 DVDD15 AC1 TSPUSHEVT1
Y17 CVDD AA29 VSS AC2 TSPUSHEVT0
Y18 VSS AA30 DVDD15 AC3 TSSYNCEVT
Y19 CVDD AA31 DDR3BRZQ0 AC4 RSV188
Y20 VSS AA32 DDR3BA00 AC5 RESETSTAT
Y21 CVDD AA33 DDR3BA08 AC6 DVDD18
Y22 VSS AA34 DDR3BBA1 AC7 VSS
Y23 CVDD AA35 VSS AC8 CVDD
Y24 VSS AA36 DDR3BCE1 AC9 VSS
Y25 CVDD AA37 DDR3BBA0 AC10 CVDD
Y26 VSS AA38 DDR3BA14 AC11 VSS
Y27 CVDD AA39 DDR3BA11 AC12 CVDD
Y28 AVDDA11 AB1 TSCOMPOUT AC13 VSS
Y29 DVDD15 AB2 EMU01 AC14 CVDD
Y30 VSS AB3 EMU14 AC15 VSS
Y31 DVDD15 AB4 EMU10 AC16 CVDD
Y32 DDR3BA09 AB5 DVDD18 AC17 VSS
Y33 VSS AB6 VSS AC18 CVDD1
Y34 DDR3BA03 AB7 DVDD18 AC19 VSS
Y35 DDR3BA12 AB8 VSS AC20 CVDD
Y36 DDR3BA15 AB9 CVDD AC21 VSS
Y37 VSS AB10 VSS AC22 CVDD
Y38 DDR3BA10 AB11 CVDD AC23 VSS
AC24 CVDD AD36 DDR3BCB06 AF9 CVDD
AC25 VSS AD37 VSS AF10 VSS
AC26 CVDD AD38 DDR3BCLKOUTP0 AF11 AVDDA1
AC27 VSS AD39 DDR3BCLKOUTN0 AF12 VSS
AC28 AVDDA13 AE1 TCK AF13 VDDALV
AC29 VSS AE2 TMS AF14 VSS
AC30 DVDD15 AE3 VSS AF15 VDDALV
AC31 DDR3BVREFSSTL AE4 LRESET AF16 VSS
AC32 DDR3BRESET AE5 HOUT AF17 VDDALV
AC33 DDR3BODT0 AE6 DVDD18 AF18 VSS
AC34 RSV031 AE7 VSS AF19 VDDALV
AC35 VSS AE8 CVDD AF20 VSS
AC36 DDR3BCAS AE9 VSS AF21 VDDALV
AC37 DDR3BWE AE10 CVDD AF22 VSS
AC38 DDR3BCLKOUTN1 AE11 VSS AF23 VDDALV
AC39 DDR3BCLKOUTP1 AE12 CVDD AF24 VSS
AD1 TRST AE13 VSS AF25 CVDD
AD2 RESET AE14 CVDD AF26 VSS
AD3 RESETFULL AE15 VSS AF27 CVDD
AD4 LRESETNMIEN AE16 CVDD AF28 VSS
AD5 NMI AE17 VSS AF29 DVDD15
AD6 VSS AE18 CVDD AF30 VSS
AD7 DVDD18 AE19 VSS AF31 DVDD15
AD8 VSS AE20 CVDD AF32 DDR3BCB00
AD9 CVDD AE21 VSS AF33 VSS
AD10 VSS AE22 CVDD AF34 DDR3BCB01
AD11 VNWA2 AE23 VSS AF35 DDR3BCB03
AD12 VSS AE24 CVDD AF36 DDR3BD33
AD13 CVDD AE25 VSS AF37 VSS
AD14 VSS AE26 CVDD AF38 DDR3BDQS4P
AD15 CVDD AE27 VSS AF39 DDR3BDQS4N
AD16 VSS AE28 AVDDA15 AG1 TDI
AD17 CVDD1 AE29 VSS AG2 HYP1RXFLDAT
AD18 VSS AE30 DVDD15 AG3 HYP0RXPMDAT
AD19 CVDD1 AE31 VSS AG4 VSS
AD20 VSS AE32 DDR3BCB02 AG5 HYP0TXFLDAT
AD21 CVDD AE33 DDR3BCB04 AG6 DVDD18
AD22 VSS AE34 DDR3BCB07 AG7 VSS
AD23 CVDD AE35 VSS AG8 CVDD
AD24 VSS AE36 DDR3BCB05 AG9 VSS
AD25 CVDD AE37 DDR3BDQM8 AG10 CVDD
AD26 VSS AE38 DDR3BDQS8N AG11 VSS
AD27 CVDD AE39 DDR3BDQS8P AG12 VDDALV
AD28 AVDDA14 AF1 TDO AG13 VSS
AD29 DVDD15 AF2 HYP1TXPMDAT AG14 VDDALV
AD30 VSS AF3 HYP1RXPMCLK AG15 VSS
AD31 DVDD15 AF4 HYP1RXPMDAT AG16 VDDALV
AD32 DDR3BRAS AF5 BOOTCOMPLETE AG17 VSS
AD33 VSS AF6 VSS AG18 VDDALV
AD34 DDR3BODT1 AF7 DVDD18 AG19 VSS
AD35 RSV030 AF8 VSS AG20 VDDALV
AG21 VSS AH33 VSS AK6 VSS
AG22 VDDALV AH34 DDR3BD37 AK7 CVDD
AG23 VSS AH35 DDR3BD38 AK8 VSS
AG24 VNWA1 AH36 DDR3BD42 AK9 CVDD
AG25 VSS AH37 VSS AK10 VSS
AG26 AVDDA5 AH38 DDR3BD46 AK11 VDDAHV
AG27 VSS AH39 DDR3BD45 AK12 VSS
AG28 CVDD AJ1 HYP0TXPMDAT AK13 VDDAHV
AG29 VSS AJ2 HYP0RXPMCLK AK14 VSS
AG30 DVDD15 AJ3 HYP0TXFLCLK AK15 VDDAHV
AG31 VSS AJ4 HYP0RXFLDAT AK16 VSS
AG32 DDR3BD39 AJ5 HYP0RXFLCLK AK17 VDDAHV
AG33 DDR3BDQM4 AJ6 VSS AK18 VSS
AG34 DDR3BD35 AJ7 VSS AK19 VDDAHV
AG35 VSS AJ8 CVDD AK20 VSS
AG36 DDR3BD36 AJ9 VSS AK21 VDDAHV
AG37 DDR3BD32 AJ10 CVDD AK22 VSS
AG38 DDR3BD34 AJ11 VSS AK23 VDDAHV
AG39 DDR3BDQM5 AJ12 VDDALV AK24 VSS
AH1 HYP1TXPMCLK AJ13 VSS AK25 VDDAHV
AH2 HYP1TXFLDAT AJ14 VDDALV AK26 VSS
AH3 HYP1TXFLCLK AJ15 VSS AK27 DVDD18
AH4 HYP1RXFLCLK AJ16 VDDALV AK28 VSS
AH5 HYP0TXPMCLK AJ17 VSS AK29 CVDD
AH6 VSS AJ18 VDDALV AK30 VSS
AH7 VSS AJ19 VSS AK31 DVDD15
AH8 VSS AJ20 VDDALV AK32 DDR3BRZQ2
AH9 CVDD AJ21 VSS AK33 VSS
AH10 VSS AJ22 VDDALV AK34 DDR3BDQM6
AH11 VDDALV AJ23 VSS AK35 DDR3BD51
AH12 VSS AJ24 VDDALV AK36 DDR3BD50
AH13 VDDALV AJ25 VSS AK37 VSS
AH14 VSS AJ26 DVDD18 AK38 DDR3BD49
AH15 VDDALV AJ27 VSS AK39 DDR3BD48
AH16 VSS AJ28 CVDD AL1 TSREFCLKN
AH17 VDDALV AJ29 VSS AL2 ALTCORECLKN
AH18 VSS AJ30 DVDD15 AL3 SYSCLKP
AH19 VDDALV AJ31 VSS AL4 CORECLKSEL
AH20 VSS AJ32 VSS AL5 VSS
AH21 VDDALV AJ33 DDR3BD41 AL6 CVDD
AH22 VSS AJ34 DDR3BD43 AL7 VSS
AH23 VDDALV AJ35 VSS AL8 CVDD
AH24 VSS AJ36 DDR3BD44 AL9 VSS
AH25 VDDALV AJ37 DDR3BD47 AL10 VDDAHV
AH26 VSS AJ38 DDR3BDQS5N AL11 VSS
AH27 CVDD AJ39 DDR3BDQS5P AL12 VDDAHV
AH28 VSS AK1 SYSCLKOUT AL13 VSS
AH29 AVDDA4 AK2 VSS AL14 VDDAHV
AH30 VSS AK3 SYSCLKN AL15 VSS
AH31 DVDD15 AK4 POR AL16 VDDAHV
AH32 DDR3BD40 AK5 RSV012 AL17 VSS
AL18 VDDAHV AM27 DVDD18 AN36 DDR3BD57
AL19 VSS AM28 RSV022 AN37 DDR3BD63
AL20 VDDAHV AM29 DVDD18 AN38 DDR3BDQS7P
AL21 VSS AM30 RSV192 AN39 DDR3BDQS7N
AL22 VDDAHV AM31 CVDD AP1 TSRXCLKOUT0N
AL23 VSS AM32 VSS AP2 RSV187
AL24 VDDAHV AM33 VSS AP3 TSRXCLKOUT1N
AL25 VSS AM34 DDR3BD59 AP4 VSS
AL26 DVDD18 AM35 DDR3BD60 AP5 HYP1TXN1
AL27 VSS AM36 DDR3BD62 AP6 HYP1TXP1
AL28 DVDD18 AM37 VSS AP7 VSS
AL29 VSS AM38 DDR3BD61 AP8 HYP0TXN2
AL30 CVDD AM39 DDR3BDQM7 AP9 HYP0TXP2
AL31 VSS AN1 TSRXCLKOUT0P AP10 VSS
AL32 DVDD15 AN2 VSS AP11 HYP0TXN0
AL33 DDR3BD55 AN3 TSRXCLKOUT1P AP12 HYP0TXP0
AL34 DDR3BD52 AN4 RSV002 AP13 VSS
AL35 VSS AN5 VSS AP14 RSV179
AL36 DDR3BD53 AN6 VSS AP15 RSV180
AL37 DDR3BD54 AN7 VSS AP16 VSS
AL38 DDR3BDQS6N AN8 VSS AP17 RSV173
AL39 DDR3BDQS6P AN9 VSS AP18 RSV174
AM1 TSREFCLKP AN10 RSV019 AP19 VSS
AM2 ALTCORECLKP AN11 VSS AP20 VSS
AM3 VSS AN12 VSS AP21 VSS
AM4 RSV003 AN13 VSS AP22 RIOTXN2
AM5 CVDD AN14 VSS AP23 RIOTXP2
AM6 HYP1REFRES AN15 VSS AP24 VSS
AM7 RSV020 AN16
(66AK2H14 only) 		XFIREFRES0 AP25 SGMII3TXN
AM8 VSS AP26 SGMII3TXP
AM9 HYP0REFRES AN16
(66AK2H12/06 only) 		RSV068 AP27 VSS
AM10 VSS AP28 VSS
AM11 RSV099 AN17 VSS AP29 VSS
AM12 VSS AN18 VSS AP30 VSS
AM13 VSS AN19 RSV026 AP31 MDCLK
AM14 RSV025 AN20 VSS AP32 RSV193
AM15 RSV185 AN21 VSS AP33 RSV195
AM16 RSV024 AN22 VSS AP34 RSV191
AM17 VSS AN23 VSS AP35 VD
AM18 VSS AN24 VSS AP36 VCL
AM19
(66AK2H14 only) 		XFIREFRES1 AN25 VSS AP37 VSS
AN26 VSS AP38 RSV006
AM19
(66AK2H12/06 only) 		RSV069 AN27 VSS AP39 RSV007
AN28 VSS AR1 RSV189
AM20 VSS AN29 VSS AR2 RSV186
AM21 RIOREFRES AN30 PACLKSEL AR3 VSS
AM22 VSS AN31 VSS AR4 HYP1TXN2
AM23 RSV021 AN32 RSV194 AR5 HYP1TXP2
AM24 SGMIIREFRES AN33 DDR3BD58 AR6 VSS
AM25 RSV023 AN34 DDR3BD56 AR7 HYP0TXN3
AM26 PCIEREFRES AN35 VSS AR8 HYP0TXP3
AR9 VSS AT12 RSV183 AU15 VSS
AR10 HYP0TXN1 AT13 RSV184 AU16 RSV163
AR11 HYP0TXP1 AT14 VSS AU17 RSV164
AR12 VSS AT15 RSV177 AU18 VSS
AR13 RSV181 AT16 RSV178 AU19
(66AK2H12/06 only)		 RSV070
AR14 RSV182 AT17 VSS
AR15 VSS AT18
(66AK2H14 only)		 XFITXP0 AU19
(66AK2H14 only)		 XFICLKP
AR16 RSV175
AR17 RSV176 AT18
(66AK2H12/06 only)		 RSV063 AU20
(66AK2H12/06 only)		 RSV071
AR18 VSS
AR19
(66AK2H14 only)		 XFITXP1 AT19
(66AK2H14 only)		 XFITXN0 AU20
(66AK2H14 only)		 XFICLKN
AR19
(66AK2H12/06 only)		 RSV067 AT19
(66AK2H12/06 only)		 RSV062 AU21 VSS
AU22 RIORXN1
AR20
(66AK2H14 only)		 XFITXN1 AT20 VSS AU23 RIORXP1
AT21 RIOTXN3 AU24 VSS
AR20
(66AK2H12/06 only)		 RSV066 AT22 RIOTXP3 AU25 SGMII2RXN
AT23 VSS AU26 SGMII2RXP
AR21 VSS AT24 RIOTXN0 AU27 VSS
AR22 VSS AT25 RIOTXP0 AU28 SGMII0TXN
AR23 RIOTXN1 AT26 VSS AU29 SGMII0TXP
AR24 RIOTXP1 AT27 SGMII1TXN AU30 VSS
AR25 VSS AT28 SGMII1TXP AU31 PCIERXN0
AR26 SGMII2TXN AT29 VSS AU32 PCIERXP0
AR27 SGMII2TXP AT30 PCIETXN0 AU33 VSS
AR28 VSS AT31 PCIETXP0 AU34 RSV008
AR29 PCIETXN1 AT32 VSS AU35 RSV80
AR30 PCIETXP1 AT33
(66AK2H14 only)		 XFIMDIO AU36 RSV76
AR31 VSS AU37 RSV78
AR32 MDIO AT33
(66AK2H12/06 only)		 RSV072 AU38 VCNTL4
AR33 VSS AU39 VSS
AR34
(66AK2H14 only)		 XFIMDCLK AT34 RSV009 AV1 VSS
AT35 RSV75 AV2 VSS
AR34
(66AK2H12/06 only)		 RSV073 AT36 VSS AV3 HYP1RXN3
AT37 RSV74 AV4 HYP1RXP3
AR35 VCNTL5 AT38 VCNTL3 AV5 VSS
AR36 VCNTL2 AT39 VCNTL0 AV6 HYP1RXN1
AR37 VCNTL1 AU1 VSS AV7 HYP1RXP1
AR38 DDR3BCLKP AU2 VSS AV8 VSS
AR39 DDR3BCLKN AU3 VSS AV9 HYP0RXN2
AT1 RSV190 AU4 HYP1RXN2 AV10 HYP0RXP2
AT2 VSS AU5 HYP1RXP2 AV11 VSS
AT3 HYP1TXN3 AU6 VSS AV12 RSV171
AT4 HYP1TXP3 AU7 HYP1RXN0 AV13 RSV172
AT5 VSS AU8 HYP1RXP0 AV14 VSS
AT6 HYP1TXN0 AU9 VSS AV15 RSV165
AT7 HYP1TXP0 AU10 HYP0RXN1 AV16 RSV166
AT8 VSS AU11 HYP0RXP1 AV17 VSS
AT9 HYP0CLKP AU12 VSS AV18
(66AK2H14 only)		 XFIRXP0
AT10 HYP0CLKN AU13 RSV169
AT11 VSS AU14 RSV170
AV18
(66AK2H12/06 only)		 RSV061 AV38 VSS AW20
(66AK2H14 only)		 XFIRXN1
AV39 VSS
AV19
(66AK2H14 only)		 XFIRXN0 AW1 (nopin) AW20
(66AK2H12/06 only)		 RSV064
AW2 VSS
AV19
(66AK2H12/06 only)		 RSV060 AW3 VSS AW21 VSS
AW4 HYP1CLKP AW22 RIORXN2
AV20 VSS AW5 HYP1CLKN AW23 RIORXP2
AV21 RIORXN3 AW6 VSS AW24 VSS
AV22 RIORXP3 AW7 HYP0RXN3 AW25 SGMII3RXN
AV23 VSS AW8 HYP0RXP3 AW26 SGMII3RXP
AV24 RIORXN0 AW9 VSS AW27 VSS
AV25 RIORXP0 AW10 HYP0RXN0 AW28 SGMII0RXN
AV26 VSS AW11 HYP0RXP0 AW29 SGMII0RXP
AV27 SGMII1RXN AW12 VSS AW30 VSS
AV28 SGMII1RXP AW13 RSV167 AW31 PCIECLKP
AV29 VSS AW14 RSV168 AW32 PCIECLKN
AV30 PCIERXN1 AW15 VSS AW33 VSS
AV31 PCIERXP1 AW16 RSV161 AW34 SRIOSGMIICLKP
AV32 VSS AW17 RSV162 AW35 SRIOSGMIICLKN
AV33 PASSCLKP AW18 VSS AW36 RSV81
AV34 PASSCLKN AW19
(66AK2H14 only)		 XFIRXP1 AW37 VSS
AV35 VSS AW38 VSS
AV36 RSV79 AW19
(66AK2H12/06 only)		 RSV065 AW39 (nopin)
AV37 RSV77

4.4 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.

An external pullup/pulldown resistor needs to be used in the following situations:

  • Device Configuration Pins: If the pin is both routed out and not driven (in Hi-Z state), an external pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.
  • Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail.

For the device configuration pins (listed in Table 10-29), if they are both routed out and are not driven (in Hi-Z state), it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

  • Consider the total amount of current that may pass through the pullup or pulldown resistor. Be sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors.
  • Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device; which, by definition, have margin to the VIL and VIH levels.
  • Select a pullup/pulldown resistor with the largest possible value that still ensures that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net.
  • For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin).
  • Remember to include tolerances when selecting the resistor value.
  • For pullup resistors, also remember to include tolerances on the DVDD rail.

For most systems:

  • A 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.
  • A 20-kΩ resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For more detailed information on input current (II), and the low-level and high-level input voltages (VIL and VIH) for the 66AK2Hxx device, see Section 5.5. To determine which pins on the device include internal pullup/pulldown resistors, see Table 4-3.

 
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