Refer to the PDF data sheet for device specific package drawings
The ADC128S102 device is a low-power, eight-channel CMOS 12-bit analog-to-digital converter specified for conversion throughput rates of 50 kSPS to 1 MSPS. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. The device can be configured to accept up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is compatible with several standards, such as SPI, QSPI, MICROWIRE, and many common DSP serial interfaces.
The ADC128S102 may be operated with independent analog and digital supplies. The analog supply (VA) can range from 2.7 V to 5.25 V, and the digital supply (VD) can range from 2.7 V to VA. Normal power consumption using a 3-V or 5-V supply is 2.3 mW and 10.7 mW, respectively. The power-down feature reduces the power consumption to 0.06 µW using a 3-V supply and 0.25 µW using a 5-V supply.
Changes from O Revision (November 2016) to P Revision
Changes from N Revision (September 2015) to O Revision
Changes from H Revision (October 2009) to N Revision
Changes from G Revision (October 2009) to H Revision
Changes from F Revision (June 2009) to G Revision
Changes from E Revision (April 2009) to F Revision
Changes from D Revision (January 2009) to E Revision
Changes from C Revision (November 2008) to D Revision
Changes from B Revision (August 2008) to C Revision
Changes from A Revision (August 2008) to B Revision
MIN | MAX | UNIT | ||
---|---|---|---|---|
VA | Analog supply voltage | –0.3 | 6.5 | V |
VD | Digital supply voltage(4) | –0.3 | VA + 0.3 | V |
Voltage on any pin to GND | –0.3 | VA + 0.3 | V | |
Input current at any pin (2) | ±10 | mA | ||
Power dissipation TA = 25°C | See (3) | |||
Package input current(2) | ±20 mA | mA | ||
Soldering temperature, 10 seconds | 260 | °C | ||
Junction temperature | 175 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) | ±8000 | V |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Operating temperature | –55 | 125 | °C | |
VA supply voltage | 2.7 | 5.25 | V | |
VD supply voltage | 2.7 | VA | V | |
Digital input voltage | 0 | VA | V | |
Analog input voltage | 0 | VA | V | |
Clock frequency | 0.8 | 16 | MHz |
THERMAL METRIC(1) | ACD128S102QML-SP | UNIT | |
---|---|---|---|
NAC (CFP) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 127 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 11.2 | °C/W |
PARAMETER | TEST CONDITIONS | SUBGROUP | MIN | TYP(1) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
STATIC CONVERTER CHARACTERISTICS | ||||||||
Resolution with no missing codes | 12 | Bits | ||||||
INL | Integral non-linearity (end point method) | VA = VD = 3 V | [1, 2, 3] | –1 | ±0.6 | 1.1 | LSB | |
VA = VD = 5 V | [1, 2, 3] | –1.25 | ±0.9 | 1.4 | LSB | |||
DNL | Differential non-linearity | VA = VD = 3 V | [1, 2, 3] | 0.5 | 0.9 | LSB | ||
[1, 2, 3] | –0.7 | –0.3 | LSB | |||||
VA = VD = 5 V | [1, 2, 3] | 0.9 | 1.5 | LSB | ||||
[1, 2, 3] | –0.9 | −0.5 | LSB | |||||
VOFF | Offset error | VA = VD = 3 V | [1, 2, 3] | –2.3 | 0.8 | 2.3 | LSB | |
VA = VD = 5 V | [1, 2, 3] | –2.3 | 1.1 | 2.3 | LSB | |||
OEM | Offset error match | VA = VD = 3 V | [1, 2, 3] | –1.5 | ±0.1 | 1.5 | LSB | |
VA = VD = 5 V | [1, 2, 3] | –1.5 | ±0.3 | 1.5 | LSB | |||
FSE | Full scale error | VA = VD = 3 V | [1, 2, 3] | –2 | 0.8 | 2 | LSB | |
VA = VD = 5 V | [1, 2, 3] | –2 | 0.3 | 2 | LSB | |||
FSEM | Full scale error match | VA = VD = 3 V | [1, 2, 3] | –1.5 | ±0.1 | 1.5 | LSB | |
VA = VD = 5 V | [1, 2, 3] | –1.5 | ±0.3 | 1.5 | LSB | |||
DYNAMIC CONVERTER CHARACTERISTICS | ||||||||
FPBW | Full power bandwidth (–3 dB) | VA = VD = 3 V | 6.8 | MHz | ||||
VA = VD = 5 V | 10 | MHz | ||||||
SINAD | Signal-to-noise plus distortion ratio | VA = VD = 3 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | 68 | 72 | dB | ||
VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | 68 | 72 | dB | ||||
SNR | Signal-to-noise ratio | VA = VD = 3 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | 69 | 72 | dB | ||
VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | 68.5 | 72 | dB | ||||
THD | Total harmonic distortion | VA = VD = 3 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | –86 | –74 | dB | ||
VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | –87 | –74 | dB | ||||
SFDR | Spurious-free dynamic range | VA = VD = 3 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | 75 | 91 | dB | ||
VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | 75 | 90 | dB | ||||
ENOB | Effective number of bits | VA = VD = 3 V, fIN = 40.2 kHz |
[4, 5, 6] | 11.1 | 11.6 | Bits | ||
VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | 11.1 | 11.6 | Bits | ||||
ISO | Channel-to-channel isolation | VA = VD = 3 V, fIN = 20 kHz |
84 | dB | ||||
VA = VD = 5 V, fIN = 20 kHz, −0.02 dBFS |
85 | dB | ||||||
IMD | Intermodulation distortion, second order terms | VA = VD = 3 V, fa = 19.5 kHz, fb = 20.5 kHz |
[4, 5, 6] | –93 | –78 | dB | ||
VA = VD = 5 V, fa = 19.5 kHz, fb = 20.5 kHz |
[4, 5, 6] | –93 | –78 | dB | ||||
Intermodulation distortion, third order terms | VA = VD = 3 V, fa = 19.5 kHz, fb = 20.5 kHz |
[4, 5, 6] | –91 | –70 | dB | |||
VA = VD = 5 V, fa = 19.5 kHz, fb = 20.5 kHz |
[4, 5, 6] | –91 | –70 | dB | ||||
ANALOG INPUT CHARACTERISTICS | ||||||||
VIN | Input range | 0 to VA | V | |||||
IDCL | DC leakage current | [1, 2, 3] | ±0.01 | ±1 | µA | |||
CINA | Input capacitance | Track mode, see (2) | 38 | pF | ||||
Hold mode, see (2) | 4.5 | pF | ||||||
DIGITAL INPUT CHARACTERISTICS | ||||||||
VIH | Input high voltage | VA = VD = 2.7 V to 3.6 V | [1, 2, 3] | 2.1 | V | |||
VA = VD = 4.75 V to 5.25 V | [1, 2, 3] | 2.4 | V | |||||
VIL | Input low voltage | VA = VD = 2.7 V to 5.25 V | [1, 2, 3] | 0.8 | V | |||
IIN | Input current | VIN = 0 V or VD | [1, 2, 3] | ±1 | ±1 | µA | ||
CIND | Digital input capacitance | See (2) | 3.5 | pF | ||||
DIGITAL OUTPUT CHARACTERISTICS | ||||||||
VOH | Output high voltage | ISOURCE = 200 µA, VA = VD = 2.7 V to 5.25 V |
[1, 2, 3] | VD –0.5 | V | |||
VOL | Output low voltage | ISINK = 200 µA to 1 mA, VA = VD = 2.7 V to 5.25 V |
[1, 2, 3] | 0.4 | V | |||
IOZH, IOZL | Hi-impedance output leakage current | VA = VD = 2.7 V to 5.25 V | [1, 2, 3] | ±0.01 | ±1 | µA | ||
COUT | Hi-impedance output capacitance | See (2) | 3.5 | pF | ||||
Output coding | Straight (Natural) Binary | |||||||
POWER SUPPLY CHARACTERISTICS (CL = 10 pF) | ||||||||
VA, VD | Analog and digital supply voltages | VA ≥ VD | [1, 2, 3] | 2.7 | V | |||
[1, 2, 3] | 5.25 | V | ||||||
IA + ID | Total supply current, normal mode ( CS low) |
VA = VD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS, fIN = 40 kHz |
[1, 2, 3] | 0.9 | 1.5 | mA | ||
VA = VD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS, fIN = 40 kHz |
[1, 2, 3] | 2.2 | 3.1 | mA | ||||
Total supply current, shutdown mode (CS high) |
VA = VD = 2.7 V to 3.6 V, fSCLK = 0 kSPS |
[1, 2, 3] | 0.11 | 1 | μA | |||
VA = VD = 4.75 V to 5.25 V, fSCLK = 0 kSPS |
[1, 2, 3] | 0.12 | 1.4 | μA | ||||
PC | Power consumption, normal mode ( CS low) |
VA = VD = 3 V fSAMPLE = 1 MSPS, fIN = 40 kHz |
[1, 2, 3] | 2.7 | 4.5 | mW | ||
VA = VD = 5 V fSAMPLE = 1 MSPS, fIN = 40 kHz |
[1, 2, 3] | 11.0 | 15.5 | mW | ||||
Power consumption, shutdown mode (CS high) |
VA = VD = 3 V fSCLK = 0 kSPS |
[1, 2, 3] | 0.33 | 3 | µW | |||
VA = VD = 5 V fSCLK = 0 kSPS |
[1, 2, 3] | 0.6 | 7 | µW | ||||
AC ELECTRICAL CHARACTERISTICS | ||||||||
fSCLKMIN | Minimum clock frequency | VA = VD = 2.7 V to 5.25 V | [9, 10, 11] | 0.8 | MHz | |||
fSCLK | Maximum clock frequency | VA = VD = 2.7 V to 5.25 V | [9, 10, 11] | 16 | MHz | |||
fS | Sample rate continuous mode | VA = VD = 2.7 V to 5.25 V | [9, 10, 11] | 50 | kSPS | |||
[9, 10, 11] | 1 | MSPS | ||||||
tCONVERT | Conversion (hold) time | VA = VD = 2.7 V to 5.25 V | [9, 10, 11] | 13 | SCLK cycles | |||
DC | SCLK duty cycle | VA = VD = 2.7 V to 5.25 V | MIN | 40% | ||||
MAX | 60% | |||||||
tACQ | Acquisition (track) time | VA = VD = 2.7 V to 5.25 V | [9, 10, 11] | 3 | SCLK cycles | |||
Throughput time | Acquisition time + conversion time VA = VD = 2.7 V to 5.25 V |
[9, 10, 11] | 16 | SCLK cycles | ||||
tAD | Aperture delay | VA = VD = 2.7 V to 5.25 V | 4 | ns |
PARAMETER | TEST CONDITIONS | SUBGROUP | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
IA + ID | Total supply current shutdown mode (CS high) | VA = VD = 2.7 V to 3.6 V, fSCLK = 0 kSPS |
[1] | 30 | µA | ||
VA = VD = 4.75 V to 5.25 V, fSCLK = 0 kSPS |
[1] | 100 | µA | ||||
IOZH, IOZL | Hi-impedance output leakage current | VA = VD = 2.7 V to 5.25 V | [1] | ±10 | µA |
SUBGROUP | MIN | NOM(1) | MAX | UNIT | |||
---|---|---|---|---|---|---|---|
tCSH | CS hold time after SCLK rising edge | See (2) | [9, 10, 11] | 10 | 0 | ns | |
tCSS | CS setup time prior to SCLK rising edge | See (2) | [9, 10, 11] | 10 | 4.5 | ns | |
tEN | CS falling edge to DOUT enabled | [9, 10, 11] | 5 | 30 | ns | ||
tDACC | DOUT access time after SCLK falling edge | [9, 10, 11] | 17 | 27 | ns | ||
tDHLD | DOUT hold time after SCLK falling edge | [9, 10, 11] | 7 | ns | |||
tDS | DIN setup time prior to SCLK rising edge | [9, 10, 11] | 10 | ns | |||
tDH | DIN hold time after SCLK rising edge | [9, 10, 11] | 10 | ns | |||
tCH | SCLK high time | 0.4 × tSCLK | ns | ||||
tCL | SCLK low time | 0.4 × tSCLK | ns | ||||
tDIS | CS rising edge to DOUT high-impedance | DOUT falling | [9, 10, 11] | 2.4 | 20 | ns | |
DOUT rising | [9, 10, 11] | 0.9 | 20 | ns |
SUBGROUP | DESCRIPTION | TEMP (°C) |
---|---|---|
1 | Static tests at | 25 |
2 | Static tests at | 125 |
3 | Static tests at | –55 |
4 | Dynamic tests at | 25 |
5 | Dynamic tests at | 125 |
6 | Dynamic tests at | –55 |
7 | Functional tests at | 25 |
8A | Functional tests at | 125 |
8B | Functional tests at | –55 |
9 | Switching tests at | 25 |
10 | Switching tests at | 125 |
11 | Switching tests at | –55 |
12 | Setting time at | 25 |
13 | Setting time at | 125 |
14 | Setting time at | –55 |