Data Sheet
ADC12DLx500 0.5, 1.5, 2.5GSPS Dual-Channel or 1, 3, 5GSPS Single-Channel,12-Bit Analog-to-Digital Converters (ADC) With LVDS Interface
1 Features
- ADC core:
- 12-Bit resolution
- Up to 1GSPS, 3GSPS, 5GSPS in single-channel mode
- Up to 500MSPS, 1.5GSPS, 2.5GSPS in dual-channel mode
- Internal dither for low-magnitude, high-order harmonics
- Low-latency LVDS interface:
- Total latency: < 10ns
- Up to 48 data pairs at 1.6Gbps
- Four DDR data clocks
- Strobe signals simplify synchronization
- Noise floor (no input, VFS = 1VPP-DIFF):
- Dual-channel mode: -143.5, -148, -149.8dBFS/Hz
- Single-channel mode: -146.2, -150.3, -152.2dBFS/Hz
- Buffered analog inputs with VCMI of
0V:
- Analog input bandwidth (–3dB): 8GHz
- Full-scale input voltage (VFS, default): 0.8VPP
- Noiseless aperture delay (TAD) adjustment:
- Precise sampling control: 19fs step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- Power consumption: 2.6, 2.8, 3W
2 Applications
- Oscilloscopes and digitizers
- Electronic Warfare (SIGINT, ELINT)
- Time-of-flight and LIDAR distance measurement
- Microwave backhaul
- Automotive radar testers
- Spectrometry
3 Description
The ADC12DL500, ADC12DL1500 and ADC12DL2500 are a family of analog-to-digital converters (ADC) that can sample up to 500MSPS, 1.5GSPS, and 2.5GSPS in dual-channel mode and up to 1GSPS, 3GSPS, and 5GSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and sample rate (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications.
The devices uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (TAD) adjustment and SYSREF windowing.
Package Information
| PART NUMBER | PACKAGE(1) | PACKAGE SIZE(2) |
|---|---|---|
| ADC12DL500 ADC12DL1500 ADC12DL2500 | FCBGA (256) | 17mm × 17mm |
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
ADC12DLx500 Frequency Response4 Pin Configuration and Functions
Figure 4-1 ACF Package, 256-Ball Flip
Chip BGA
(Top View)
(Top View)
Table 4-1 Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| A1 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| A2 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| A3 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| A4 | INA+ | I | Channel A analog input positive connection. The differential full-scale input range is determined by the FS_RANGE_A register; see the Full-Scale Voltage (VFS) Adjustment section. This input is terminated to AGND through a 50-Ω termination resistor. The input common-mode voltage must typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used. |
| A5 | INA– | I | Channel A analog input negative connection. See INA+ (pin A4) for detailed description. This input is terminated to ground through a 50Ω termination resistor. This pin can be left disconnected if not used. |
| A6 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| A7 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| A8 | ORA1 | O | Fast overrange detection status for channel A for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this pin disconnected if not used. |
| A9 | DA0+ | O | LVDS output for bit 0 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. |
| A10 | DA0– | O | LVDS output for bit 0 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. |
| A11 | DA6+ | O | LVDS output for bit 6 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. |
| A12 | DA6– | O | LVDS output for bit 6 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. |
| A13 | DC0+ | O | LVDS output for bit 0 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. |
| A14 | DC0– | O | LVDS output for bit 0 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. |
| A15 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| A16 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| B1 | CALSTAT | O | Foreground calibration status output or device alarm output. Functionality is programmed through CAL_STATUS_SEL. This pin can be left disconnected if not used. |
| B2 | CALTRIG | I | Foreground calibration trigger input. This pin is only used if hardware calibration triggering is selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG. Tie this pin to GND if not used. |
| B3 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| B4 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| B5 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| B6 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| B7 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| B8 | ORA0 | O | Fast overrange detection status for channel A for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this pin disconnected if not used. |
| B9 | DA1+ | O | LVDS output for bit 1 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. |
| B10 | DA1– | O | LVDS output for bit 1 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. |
| B11 | DA7+ | O | LVDS output for bit 7 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. |
| B12 | DA7– | O | LVDS output for bit 7 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. |
| B13 | DC1+ | O | LVDS output for bit 1 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. |
| B14 | DC1– | O | LVDS output for bit 1 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. |
| B15 | DC7+ | O | LVDS output for bit 7 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. |
| B16 | DC7– | O | LVDS output for bit 7 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. |
| C1 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| C2 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| C3 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| C4 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| C5 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| C6 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| C7 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| C8 | ORB1 | O | Fast overrange detection status for channel B for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this pin disconnected if not used. |
| C9 | DA2+ | O | LVDS output for bit 2 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. |
| C10 | DA2– | O | LVDS output for bit 2 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. |
| C11 | DA8+ | O | LVDS output for bit 8 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. |
| C12 | DA8– | O | LVDS output for bit 8 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. |
| C13 | DC2+ | O | LVDS output for bit 2 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. |
| C14 | DC2– | O | LVDS output for bit 2 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. |
| C15 | DC8+ | O | LVDS output for bit 8 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. |
| C16 | DC8– | O | LVDS output for bit 8 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. |
| D1 | TMSTP+ | I | Timestamp input positive connection or differential LVDS SYNC
positive connection. This input is used as the timestamp input, used
to mark a specific sample, when TIMESTAMP_EN is set 1. This
differential input is used as the SYNC signal input when SYNC_SEL is
set to 1. This input can be used as both a timestamp and
differential SYNC input at the same time, allowing feedback of the
SYNC signal using the timestamp mechanism. TMSTP± uses active low
signaling when used as the LVDS SYNC signal. For additional usage
information, see the Timestamp section. TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to TMSTP–) has an internal untrimmed 100Ω differential termination and can be AC-coupled when TMSTP_LVPECL_EN is set to 0. The termination changes to 50Ω to ground on each input pin (TMSTP+ and TMSTP–) and can be DC-coupled when TMSTP_LVPECL_EN is set to 1. This pin is not self-biased and therefore must be externally biased for both AC-coupled and DC-coupled configurations. The common-mode voltage must be within the range provided in the Recommended Operating Conditions table when both AC-coupled and DC-coupled. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for the LVDS SYNC signal and timestamp is not required. |
| D2 | BG | O | Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited capacitive loads, as specified in the Recommended Operating Conditions table. See the Analog Reference Voltage section for more details. This pin can be left disconnected if not used. |
| D3 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| D4 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| D5 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| D6 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| D7 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| D8 | ORB0 | O | Fast overrange detection status for channel B for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this pin disconnected if not used. |
| D9 | DA3+ | O | LVDS output for bit 3 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. |
| D10 | DA3– | O | LVDS output for bit 3 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. |
| D11 | DA9+ | O | LVDS output for bit 9 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. |
| D12 | DA9– | O | LVDS output for bit 9 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. |
| D13 | DC3+ | O | LVDS output for bit 3 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. |
| D14 | DC3– | O | LVDS output for bit 3 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. |
| D15 | DC9+ | O | LVDS output for bit 9 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. |
| D16 | DC9– | O | LVDS output for bit 9 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. |
| E1 | TMSTP– | I | Timestamp input negative connection or differential LVDS SYNC negative connection. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for the LVDS SYNC signal and timestamp is not required. |
| E2 | SYNCSE | I | LVDS interface SYNC signal, single-ended active low input used to control sending strobe signals for synchronization or digital interface test patterns. The Digital Interface Test Patterns section describes using the SYNC signal in more detail. The choice of single-ended or differential SYNC (using the TMSTP+ and TMSTP– pins) is selected by programming SYNC_SEL. Tie this pin to ground if differential SYNC (TMSTP±) is used as the SYNC signal. |
| E3 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| E4 | VA11 | I | 1.1V analog supply |
| E5 | VA11 | I | 1.1V analog supply |
| E6 | VA11 | I | 1.1V analog supply |
| E7 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| E8 | VD11 | I | 1.1V digital supply |
| E9 | DA4+ | O | LVDS output for bit 4 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. |
| E10 | DA4– | O | LVDS output for bit 4 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. |
| E11 | DA10+ | O | LVDS output for bit 10 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. |
| E12 | DA10– | O | LVDS output for bit 10 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. |
| E13 | DC4+ | O | LVDS output for bit 4 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. |
| E14 | DC4– | O | LVDS output for bit 4 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. |
| E15 | DC10+ | O | LVDS output for bit 10 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. |
| E16 | DC10– | O | LVDS output for bit 10 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. |
| F1 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| F2 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| F3 | VA11 | I | 1.1V analog supply |
| F4 | VA11 | I | 1.1V analog supply |
| F5 | VA11 | I | 1.1V analog supply |
| F6 | VA11 | I | 1.1V analog supply |
| F7 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| F8 | VD11 | I | 1.1-V digital supply |
| F9 | DA5+ | O | LVDS output for bit 5 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. |
| F10 | DA5– | O | LVDS output for bit 5 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. |
| F11 | DA11+ | O | LVDS output for bit 11 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. |
| F12 | DA11– | O | LVDS output for bit 11 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. |
| F13 | DC5+ | O | LVDS output for bit 5 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. |
| F14 | DC5– | O | LVDS output for bit 5 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. |
| F15 | DC11+ | O | LVDS output for bit 11 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. |
| F16 | DC11– | O | LVDS output for bit 11 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. |
| G1 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| G2 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| G3 | VA19 | I | 1.9V analog supply |
| G4 | VA19 | I | 1.9V analog supply |
| G5 | VA19 | I | 1.9V analog supply |
| G6 | VA19 | I | 1.9V analog supply |
| G7 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| G8 | VD11 | I | 1.1-V digital supply |
| G9 | DACLK+ | O | LVDS output for data clock of LVDS bus A. Positive connection. This pin can be left disconnected if not used. |
| G10 | DACLK– | O | LVDS output for data clock of LVDS bus A. Negative connection. This pin can be left disconnected if not used. |
| G11 | VLVDS | I | 1.1V to 1.9V LVDS digital interface supply |
| G12 | VLVDS | I | 1.1V to 1.9V LVDS digital interface supply |
| G13 | DC6+ | O | LVDS output for bit 6 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. |
| G14 | DC6– | O | LVDS output for bit 6 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. |
| G15 | DCCLK+ | O | LVDS output for data clock of LVDS bus C. Positive connection. This pin can be left disconnected if not used. |
| G16 | DCCLK– | O | LVDS output for data clock of LVDS bus C. Negative connection. This pin can be left disconnected if not used. |
| H1 | CLK+ | I | Device (sampling) clock positive input. TI strongly recommends that the clock signal be AC-coupled to this input for best performance. In single-channel mode, the analog input signal is sampled on both rising and falling edges. In-dual channel mode, the analog signal is sampled on the rising edge. This differential input has an internal untrimmed 100Ω differential termination and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN is set to 0. |
| H2 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| H3 | VA19 | I | 1.9V analog supply |
| H4 | VA19 | I | 1.9V analog supply |
| H5 | VA19 | I | 1.9V analog supply |
| H6 | VA19 | I | 1.9V analog supply |
| H7 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| H8 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| H9 | DASTR+ | O | LVDS output for data strobe of LVDS bus A. Positive connection. This pin can be left disconnected if not used. |
| H10 | DASTR– | O | LVDS output for data strobe of LVDS bus A. Negative connection. This pin can be left disconnected if not used. |
| H11 | VLVDS | I | 1.1V to 1.9V LVDS digital interface supply |
| H12 | VLVDS | I | 1.1V to 1.9V LVDS digital interface supply |
| H13 | VLVDS | I | 1.1V to 1.9V LVDS digital interface supply |
| H14 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| H15 | DCSTR+ | O | LVDS output for data strobe of LVDS bus C. Positive connection. This pin can be left disconnected if not used. |
| H16 | DCSTR– | O | LVDS output for data strobe of LVDS bus C. Negative connection. This pin can be left disconnected if not used. |
| J1 | CLK– | I | Device (sampling) clock negative input. TI strongly recommends that the clock signal be AC-coupled to this input for best performance. |
| J2 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| J3 | VA19 | I | 1.9V analog supply |
| J4 | VA19 | I | 1.9V analog supply |
| J5 | VA19 | I | 1.9V analog supply |
| J6 | VA19 | I | 1.9V analog supply |
| J7 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| J8 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| J9 | DBSTR+ | O | LVDS output for data strobe of LVDS bus B. Positive connection. This pin can be left disconnected if not used. |
| J10 | DBSTR– | O | LVDS output for data strobe of LVDS bus B. Negative connection. This pin can be left disconnected if not used. |
| J11 | VLVDS | I | 1.1V to 1.9V LVDS digital interface supply |
| J12 | VLVDS | I | 1.1V to 1.9V LVDS digital interface supply |
| J13 | VLVDS | I | 1.1V to 1.9V LVDS digital interface supply |
| J14 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| J15 | DDSTR+ | O | LVDS output for data strobe of LVDS bus D. Positive connection. This pin can be left disconnected if not used. |
| J16 | DDSTR– | O | LVDS output for data strobe of LVDS bus D. Negative connection. This pin can be left disconnected if not used. |
| K1 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| K2 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| K3 | VA19 | I | 1.9V analog supply |
| K4 | VA19 | I | 1.9V analog supply |
| K5 | VA19 | I | 1.9V analog supply |
| K6 | VA19 | I | 1.9V analog supply |
| K7 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| K8 | VD11 | I | 1.1V digital supply |
| K9 | DBCLK+ | O | LVDS output for data clock of LVDS bus B. Positive connection. This pin can be left disconnected if not used. |
| K10 | DBCLK– | O | LVDS output for data clock of LVDS bus B. Negative connection. This pin can be left disconnected if not used. |
| K11 | VLVDS | I | 1.1V to 1.9V LVDS digital interface supply |
| K12 | VLVDS | I | 1.1V to 1.9V LVDS digital interface supply |
| K13 | DD6+ | O | LVDS output for bit 6 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. |
| K14 | DD6– | O | LVDS output for bit 6 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. |
| K15 | DDCLK+ | O | LVDS output for data clock of LVDS bus D. Positive connection. This pin can be left disconnected if not used. |
| K16 | DDCLK– | O | LVDS output for data clock of LVDS bus D. Negative connection. This pin can be left disconnected if not used. |
| L1 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| L2 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| L3 | VA11 | I | 1.1V analog supply |
| L4 | VA11 | I | 1.1V analog supply |
| L5 | VA11 | I | 1.1V analog supply |
| L6 | VA11 | I | 1.1V analog supply |
| L7 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| L8 | VD11 | I | 1.1-V digital supply |
| L9 | DB5+ | O | LVDS output for bit 5 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. |
| L10 | DB5– | O | LVDS output for bit 5 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. |
| L11 | DB11+ | O | LVDS output for bit 11 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. |
| L12 | DB11– | O | LVDS output for bit 11 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. |
| L13 | DD5+ | O | LVDS output for bit 5 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. |
| L14 | DD5– | O | LVDS output for bit 5 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. |
| L15 | DD11+ | O | LVDS output for bit 11 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. |
| L16 | DD11– | O | LVDS output for bit 11 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. |
| M1 | SYSREF+ | I | SYSREF input positive connection. The SYSREF input is used to achieve synchronization between multiple ADC12DLx500 devices and deterministic latency across the LVDS data interface. This differential input (SYSREF+ to SYSREF–) has an internal untrimmed 100Ω differential termination and can be AC-coupled when SYSREF_LVPECL_EN is set to 0. This input is self-biased when SYSREF_LVPECL_EN is set to 0. The termination changes to 50Ω to ground on each input pin (SYSREF+ and SYSREF–) and can be DC-coupled when SYSERF_LVPECL_EN is set to 1. This input is not self-biased when SYSERF_LVPECL is set to 1 and must be biased externally to the input common-mode voltage range provided in the Recommended Operating Conditions table. |
| M2 | TDIODE+ | I | Temperature diode positive (anode) connection. An external temperature sensor can be connected to TDIODE+ and TDIODE– to monitor the junction temperature of the device. This pin can be left disconnected if not used. |
| M3 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| M4 | VA11 | I | 1.1V analog supply |
| M5 | VA11 | I | 1.1V analog supply |
| M6 | VA11 | I | 1.1V analog supply |
| M7 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| M8 | VD11 | I | 1.1V digital supply |
| M9 | DB4+ | O | LVDS output for bit 4 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. |
| M10 | DB4– | O | LVDS output for bit 4 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. |
| M11 | DB10+ | O | LVDS output for bit 10 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. |
| M12 | DB10– | O | LVDS output for bit 10 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. |
| M13 | DD4+ | O | LVDS output for bit 4 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. |
| M14 | DD4– | O | LVDS output for bit 4 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. |
| M15 | DD10+ | O | LVDS output for bit 10 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. |
| M16 | DD10– | O | LVDS output for bit 10 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. |
| N1 | SYSREF– | I | SYSREF input negative connection. See SYSREF+ (pin M1) for detailed description. |
| N2 | TDIODE– | I | Temperature diode negative (cathode) connection. This pin can be left disconnected if not used. |
| N3 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| N4 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| N5 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| N6 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| N7 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| N8 | SDO | O | Serial programming interface (SPI) data output. The Using the Serial Interface section describes the serial interface in more detail. This pin is high impedance during normal device operation. This pin outputs 1.9V CMOS levels during serial interface read operations. This pin can be left disconnected if not used. |
| N9 | DB3+ | O | LVDS output for bit 3 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. |
| N10 | DB3– | O | LVDS output for bit 3 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. |
| N11 | DB9+ | O | LVDS output for bit 9 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. |
| N12 | DB9– | O | LVDS output for bit 9 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. |
| N13 | DD3+ | O | LVDS output for bit 3 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. |
| N14 | DD3– | O | LVDS output for bit 3 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. |
| N15 | DD9+ | O | LVDS output for bit 9 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. |
| N16 | DD9– | O | LVDS output for bit 9 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. |
| P1 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| P2 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| P3 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| P4 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| P5 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| P6 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| P7 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| P8 | SDI | I | Serial programming interface (SPI) data input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1V and 1.8V CMOS levels. |
| P9 | DB2+ | O | LVDS output for bit 2 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. |
| P10 | DB2– | O | LVDS output for bit 2 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. |
| P11 | DB8+ | O | LVDS output for bit 8 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. |
| P12 | DB8– | O | LVDS output for bit 8 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. |
| P13 | DD2+ | O | LVDS output for bit 2 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. |
| P14 | DD2– | O | LVDS output for bit 2 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. |
| P15 | DD8+ | O | LVDS output for bit 8 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. |
| P16 | DD8– | O | LVDS output for bit 8 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. |
| R1 | PD | I | This pin disables all analog circuits and LVDS outputs when set high to save power or for temperature diode calibration. Tie this pin to ground during normal operation. |
| R2 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| R3 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| R4 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| R5 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| R6 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| R7 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| R8 | SCS | I | Serial programming interface (SPI) chip-select active low input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. This pin has an 82-kΩ pullup resistor to VD11. |
| R9 | DB1+ | O | LVDS output for bit 1 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. |
| R10 | DB1– | O | LVDS output for bit 1 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. |
| R11 | DB7+ | O | LVDS output for bit 7 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. |
| R12 | DB7– | O | LVDS output for bit 7 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. |
| R13 | DD1+ | O | LVDS output for bit 1 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. |
| R14 | DD1– | O | LVDS output for bit 1 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. |
| R15 | DD7+ | O | LVDS output for bit 7 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. |
| R16 | DD7– | O | LVDS output for bit 7 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. |
| T1 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| T2 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| T3 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| T4 | INB+ | I | Channel B analog input positive connection. The differential full-scale input range is determined by the FS_RANGE_B register; see the Full-Scale Voltage (VFS) Adjustment section. This input is terminated to AGND through a 50-Ω termination resistor. The input common-mode voltage must typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used. |
| T5 | INB– | I | Channel B analog input negative connection. See INB+ (pin T4) for detailed description. This input is terminated to ground through a 50Ω termination resistor. This pin can be left disconnected if not used. |
| T6 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| T7 | AGND | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| T8 | SCLK | I | Serial programming interface (SPI) clock. This pin functions as the serial-interface clock input that clocks the serial programming data in and out. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1V and 1.8V CMOS levels. |
| T9 | DB0+ | O | LVDS output for bit 0 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. |
| T10 | DB0– | O | LVDS output for bit 0 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. |
| T11 | DB6+ | O | LVDS output for bit 6 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. |
| T12 | DB6– | O | LVDS output for bit 6 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. |
| T13 | DD0+ | O | LVDS output for bit 0 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. |
| T14 | DD0– | O | LVDS output for bit 0 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. |
| T15 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
| T16 | DGND | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply voltage range | VA19(2) | –0.3 | 2.35 | V |
| VA11(2) | –0.3 | 1.32 | ||
| VD11(3) | –0.3 | 1.32 | ||
| VLVDS(3) | –0.3 | 2.35 | ||
| Voltage between VD11 and VA11 | –1.32 | 1.32 | ||
| Voltage between AGND and DGND | –0.1 | 0.1 | V | |
| Pin voltage range | DACLK+, DACLK–, DASTR+, DASTR–, DA[11:0]+, DA[11:0]–, DBCLK+, DBCLK–, DBSTR+, DBSTR–, DB[11:0]+, DB[11:0]–, DCCLK+, DCCLK–, DCSTR+, DCSTR–, DC[11:0]+, DC[11:0]–, DDCLK+, DDCLK–, DDSTR+, DDSTR–, DD[11:0]+, DD[11:0]–(3) | –0.5 | VLVDS + 0.5(7) | V |
| CLK+, CLK–, SYSREF+, SYSREF–(2) | –0.5 | VA11 + 0.5(5) | ||
| TMSTP+, TMSTP–(3) | –0.5 | VD11 + 0.5(6) | ||
| BG, TDIODE+, TDIODE–(2) | –0.5 | VA19 + 0.5(4) | ||
| INA+, INA–, INB+, INB–(2) | –1 | 1 | ||
| CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, PD, SCLK, SCS, SDI, SDO, SYNCSE(2) | –0.5 | VA19 + 0.5(4) | ||
| Peak input current (any input except INA+, INA–, INB+, INB–) | –25 | 25 | mA | |
| Peak input current (INA+, INA–, INB+, INB–) | –50 | 50 | mA | |
| Peak RF input power (INA+, INA–, INB+, INB–) | Single-ended with ZS-SE = 50 Ω or differential with ZS-DIFF = 100 Ω | 16.4 | dBm | |
| Peak total input current (sum of absolute value of all currents forced in or out, not including power supply current) | 100 | mA | ||
| Operating junction temperature, Tj | 150 | °C | ||
| Storage temperature, Tstg | –65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured to AGND.
(3) Measured to DGND.
(4) Maximum voltage not to exceed VA19 absolute maximum rating.
(5) Maximum voltage not to exceed VA11 absolute maximum rating.
(6) Maximum voltage not to exceed VD11 absolute maximum rating.
(7) Maximum voltage not to exceed VLVDS absolute maximum rating.
5.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2500 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| VDD | Supply voltage range | VA19, analog 1.9-V supply(2) | 1.8 | 1.9 | 2.0 | V |
| VA11, analog 1.1-V supply(2) | 1.05 | 1.1 | 1.15 | |||
| VD11, digital 1.1-V supply(3) | 1.05 | 1.1 | 1.15 | |||
| VLVDS, LVDS interface supply(3) | 1.05 | 1.9 | 2.0 | |||
| VCMI | Input common-mode voltage | INA+, INA–, INB+, INB–(2) | -50 | 0 | 110 | mV |
| CLK+, CLK–, SYSREF+, SYSREF–(2)(4) | 0 | 0.3 | 0.55 | V | ||
| TMSTP+, TMSTP–(3)(5) | 0 | 0.3 | 0.55 | |||
| VID | Input voltage, peak-to-peak differential | CLK+ to CLK–, SYSREF+ to SYSREF–, TMSTP+ to TMSTP– | 0.4 | 1.0 | 2.0 | VPP-DIFF |
| INA+ to INA–, INB+ to INB– | 1.0(6) | |||||
| VIH | High-level input voltage | CALTRIG, PD, SCLK, SCS, SDI, SYNCSE(2) | 0.7 | V | ||
| VIL | Low-level input voltage | CALTRIG, PD, SCLK, SCS, SDI, SYNCSE(2) | 0.45 | V | ||
| IC_TD | Temperature diode input current | TDIODE+ to TDIODE– | 100 | µA | ||
| CL | BG maximum load capacitance | 100 | pF | |||
| IO | BG maximum output current | 100 | µA | |||
| DC | Input clock duty cycle | 30% | 50% | 70% | ||
| TA | Operating free-air temperature | ADC12DL500 ADC12DL1500, ADC12DL2500 |
0(7) -40(8) |
85 | ºC | |
| Tj | Operating junction temperature | 105(1) | ºC | |||
(1) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.
(2) Measured to AGND.
(3) Measured to DGND.
(4) It is strongly recommended that CLK± be AC coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK± to self bias to the optimal input common mode voltage for best performance. TI recommends AC coupling for SYSREF± unless DC coupling is required, in which case LVPECL input mode must be used (SYSREF_LVPECL_EN = 1).
(5) TMSTP± does not have internal biasing which requires TMSTP± to be biased externally whether AC coupled with TMSTP_LVPECL_EN = 0 or DC coupled with TMSTP_LVPECL_EN = 1.
(6) ADC output code will saturate when VID for INA+/– or INB+/– exceeds the programmed full-scale voltage (VFS) set by FS_RANGE_A for INA± or FS_RANGE_B for INB±.
(7) ADC12DL500 min. operating free-air temperature
(8) ADC12DL1500/2500 min. operating free-air temperature
5.4 Thermal Information
| THERMAL METRIC(1) | ACF (FCBGA) | UNIT | |
|---|---|---|---|
| 256 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 16.5 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 0.94 | °C/W |
| RθJB | Junction-to-board thermal resistance | 5.4 | °C/W |
| ψJT | Junction-to-top characterization parameter | 0.5 | °C/W |
| ψJB | Junction-to-board characterization parameter | 5.1 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | °C/W |
(1) For more information about traditional and new thermal metrics, see the spra953 application report.
5.5 Electrical Characteristics: DC Specifications
Typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), foreground calibration; minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| DC ACCURACY | |||||||
| Resolution | Resolution with no missing codes | 12 | Bits | ||||
| ADC12DL500 | |||||||
| DNL | Differential nonlinearity | Maximum positive excursion from ideal step size | 0.17 | LSB | |||
| Maximum negative excursion from ideal step size | -0.14 | ||||||
| INL | Integral nonlinearity | Maximum positive excursion from ideal transfer function | 1 | LSB | |||
| Maximum negative excursion from ideal transfer function | -1.5 | ||||||
| ADC12DL1500 | |||||||
| DNL | Differential nonlinearity | Maximum positive excursion from ideal step size | 0.14 | LSB | |||
| Maximum negative excursion from ideal step size | -0.14 | ||||||
| INL | Integral nonlinearity | Maximum positive excursion from ideal transfer function | 1 | LSB | |||
| Maximum negative excursion from ideal transfer function | -1 | ||||||
| ADC12DL2500 | |||||||
| DNL | Differential nonlinearity | Maximum positive excursion from ideal step size | 0.17 | LSB | |||
| Maximum negative excursion from ideal step size | -0.19 | ||||||
| INL | Integral nonlinearity | Maximum positive excursion from ideal transfer function | 2.3 | LSB | |||
| Maximum negative excursion from ideal transfer function | -1 | ||||||
| ANALOG INPUTS (INA±, INB±) | |||||||
| VOFF | Offset Error | CAL_OS = 0 | ±2.0 | mV | |||
| CAL_OS = 1 | ±0.3 | mV | |||||
| VOFF_ADJ | Input offset voltage adjustment range | Available offset correction range (see CAL_OS bit in the CAL_CFGO register or the OADJ_A_FG0_VINA register) | ±55 | mV | |||
| VOFF_ DRIFT | Offset drift | Foreground calibration at nominal temperature only | 14 | µV/°C | |||
| Foreground calibration at each temperature | 4 | ||||||
| VIN_FSR | Analog differential input full-scale range | Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) | 800 | mVPP | |||
| Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) | 1040 | ||||||
| Minimum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0x2000) | 480 | ||||||
| VIN_FSR_DRIFT | Analog differential input full-scale range drift | Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at nominal temperature only, inputs driven by 50-Ω source, includes effect of RIN drift | 0.037 | %/°C | |||
| Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at each temperature, inputs driven by 50-Ω source, includes effect of RIN drift | 0.006 | ||||||
| VIN_FSR_MATCH | Analog differential input full-scale range matching | Matching between INA± and INB±, default setting, dual channel mode | 0.53 | % | |||
| RIN | Single-ended input resistance to AGND | Each input terminal is terminated to AGND, measured at TA = 25°C | 50 | Ω | |||
| RIN_ TEMPCO | Input termination linear temperature coefficient | 11.6 | mΩ/°C | ||||
| CIN | Single-ended input capacitance | Single-channel mode measured at DC | 0.45 | pF | |||
| Dual-channel mode measured at DC | 0.45 | ||||||
| TEMPERATURE DIODE CHARACTERISTICS (TDIODE±) | |||||||
| ΔVBE | Temperature diode voltage slope | Forced forward current of 100 µA. Offset voltage (approximately 0.792 V at 0°C) varies with process and must be measured for each part. Perform offset measurements with the device unpowered or with the PD pin asserted to minimize device self-heating. | -1.5 | mV/°C | |||
| BANDGAP VOLTAGE OUTPUT (BG) | |||||||
| VBG | Reference output voltage | IL ≤ 100 µA | 1.1 | V | |||
| VBG_ DRIFT | Reference output temperature drift | IL ≤ 100 µA | -125 | µV/°C | |||
| CLOCK INPUTS (CLK±, SYSREF±, TMSTP±) | |||||||
| ZT | Internal termination | Differential termination with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0 | 100 | Ω | |||
| Single ended termination to GND (per pin) with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0 | 50 | ||||||
| VCM | Input common-mode voltage, self-biased | Self-biasing common-mode voltage for CLK± when AC coupled (DEVCLK_LVPECL_EN must be set to 0) | 0.3 | V | |||
| Self-biasing common-mode voltage for SYSREF± when AC coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver enabled (SYSREF_RECV_EN = 1). | 0.3 | ||||||
| Self-biasing common-mode voltage for SYSREF± when AC coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver disabled (SYSREF_RECV_EN = 0). | VA11 | ||||||
| CL_DIFF | Differential input capacitance | Between positive and negative differential input pins | 0.1 | pF | |||
| CL_SE | Single-ended input capacitance | Each input to ground | 0.5 | pF | |||
| LVDS OUTPUTS (DACLK±, DASTR±, DA[11:0]±, DBCLK±, DBSTR±, DB[11:0]±, DCCLK±, DCSTR±, DC[11:0]±, DDCLK±, DDSTR±, DD[11:0]±) | |||||||
| VDIFF | Differential output peak-to-peak voltage, DC measurement | Default swing (HSM), 100-Ω load | 720 | mVPP-DIFF | |||
| Low swing (LSM), 100-Ω load | 350 | ||||||
| Low swing high-Z mode (HZM), high-impedance load | 380 | ||||||
| VCM | Output common-mode voltage, tracks with VLVDS | VLVDS = 1.9 V | 1.3 | V | |||
| VLVDS = 1.1 V | 0.5 | ||||||
| IOS_DIFF | Differential short-circuit current | Positive and negative outputs shorted together | 5 | mA | |||
| IOS_GND | Short-circuit current to ground | Either positive or negative output tied to ground | 20 | mA | |||
| ZDIFF | Differential output impedance | Measured at DC | 300 | Ω | |||
| CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE | |||||||
| IIH | High-level input current | 40 | µA | ||||
| IIL | Low-level input current | –40 | µA | ||||
| CI | Input capacitance | 2 | pF | ||||
| VOH | High-level output voltage | ILOAD = –400 µA | 1.65 | V | |||
| VOL | Low-level output voltage | ILOAD = 400 µA | 150 | mV | |||
5.6 Electrical Characteristics: Power Consumption
Typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), foreground calibration.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| ADC12DL500 | ||||||
| IVA19 | 1.9-V analog supply current | Power mode 1: single-channel mode, demux-by-2, foreground calibration, VLVDS = 1.9 V | 835 | mA | ||
| IVA11 | 1.1-V analog supply current | 185 | mA | |||
| IVD11 | 1.1-V digital supply current | 40 | mA | |||
| IVLVDS | LVDS interface supply current | 389 | mA | |||
| PDIS | Power dissipation | 2.58 | W | |||
| IVA19 | 1.9-V analog supply current | Power mode 2: dual-channel mode, demux-by-2, foreground calibration, VLVDS = 1.9 V | 913 | mA | ||
| IVA11 | 1.1-V analog supply current | 185 | mA | |||
| IVD11 | 1.1-V digital supply current | 35 | mA | |||
| IVLVDS | LVDS interface supply current | 389 | mA | |||
| PDIS | Power dissipation | 2.72 | W | |||
| IVA19 | 1.9-V analog supply current | Power mode 3: PD pin held high, no clock, VLVDS = 1.9 V | 33 | mA | ||
| IVA11 | 1.1-V analog supply current | 23 | mA | |||
| IVD11 | 1.1-V digital supply current | 3 | mA | |||
| IVLVDS | LVDS interface supply current | 0 | mA | |||
| PDIS | Power dissipation | 0.1 | W | |||
| ADC12DL1500 | ||||||
| IVA19 | 1.9-V analog supply current | Power mode 1: single-channel mode, demux-by-2, foreground calibration, VLVDS = 1.9 V | 834 | mA | ||
| IVA11 | 1.1-V analog supply current | 300 | mA | |||
| IVD11 | 1.1-V digital supply current | 113 | mA | |||
| IVLVDS | LVDS interface supply current | 389 | mA | |||
| PDIS | Power dissipation | 2.78 | W | |||
| IVA19 | 1.9-V analog supply current | Power mode 2: dual-channel mode, demux-by-2, foreground calibration, VLVDS = 1.9 V | 912 | mA | ||
| IVA11 | 1.1-V analog supply current | 299 | mA | |||
| IVD11 | 1.1-V digital supply current | 98 | mA | |||
| IVLVDS | LVDS interface supply current | 389 | mA | |||
| PDIS | Power dissipation | 2.91 | W | |||
| IVA19 | 1.9-V analog supply current | Power mode 3: PD pin held high, no clock, VLVDS = 1.9 V | 33 | mA | ||
| IVA11 | 1.1-V analog supply current | 23 | mA | |||
| IVD11 | 1.1-V digital supply current | 3 | mA | |||
| IVLVDS | LVDS interface supply current | 0 | mA | |||
| PDIS | Power dissipation | 0.1 | W | |||
| ADC12DL2500 | ||||||
| IVA19 | 1.9-V analog supply current | Power mode 1: single-channel mode, demux-by-2, foreground calibration, VLVDS = 1.9 V | 833 | mA | ||
| IVA11 | 1.1-V analog supply current | 419 | mA | |||
| IVD11 | 1.1-V digital supply current | 188 | mA | |||
| IVLVDS | LVDS interface supply current | 388 | mA | |||
| PDIS | Power dissipation | 2.99 | W | |||
| IVA19 | 1.9-V analog supply current | Power mode 2: dual-channel mode, demux-by-2, foreground calibration, VLVDS = 1.9 V | 911 | mA | ||
| IVA11 | 1.1-V analog supply current | 419 | mA | |||
| IVD11 | 1.1-V digital supply current | 169 | mA | |||
| IVLVDS | LVDS interface supply current | 389 | mA | |||
| PDIS | Power dissipation | 3.12 | W | |||
| IVA19 | 1.9-V analog supply current | Power mode 3: PD pin held high, no clock, VLVDS = 1.9 V | 33 | mA | ||
| IVA11 | 1.1-V analog supply current | 23 | mA | |||
| IVD11 | 1.1-V digital supply current | 3 | mA | |||
| IVLVDS | LVDS interface supply current | 0 | mA | |||
| PDIS | Power dissipation | 0.1 | W | |||
5.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode)
Typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 0, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), foreground calibration; minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommending Operating Conditions table.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| ADC12DL500 | ||||||
| FPBW | Full-power input bandwidth (–3 dB)(1) | Foreground calibration | 8.0 | GHz | ||
| XTALK | Channel-to-channel crosstalk | Aggressor = 400 MHz, –1 dBFS | -94 | dB | ||
| CER | Code error rate | Maximum CER | 10-18 | errors/ sample | ||
| NSD | Noise spectral density, no input signal | Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting | -143.5 | dBFS/Hz | ||
| Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting | -142.3 | |||||
| NF | Noise figure | Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting, no input, ZS = 100 Ω | 31.5 | dB | ||
| Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting, no input, ZS = 100 Ω | 30.7 | |||||
| NOISEDC | DC input noise standard deviation | No input, excludes DC offset, includes fixed interleaving spur (FS/2 spur) | 1.8 | LSB | ||
| SNR | Signal-to-noise ratio, large signal, excluding DC, HD2 to HD9 and interleaving spurs | fIN = 97 MHz, AIN = –1 dBFS | 56.8 | dBFS | ||
| fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | 57.6 | |||||
| fIN = 347 MHz, AIN = –1 dBFS | 56.7 | |||||
| SNR | Signal-to-noise ratio, small signal, excluding DC, HD2 to HD9 and interleaving spurs | fIN = 97 MHz, AIN = –16 dBFS | 57.3 | dBFS | ||
| fIN = 347 MHz, AIN = –16 dBFS | 57.4 | |||||
| SINAD | Signal-to-noise and distortion ratio, large signal, excluding DC and FS/2 fixed spurs | fIN = 97 MHz, AIN = –1 dBFS | 56 | dBFS | ||
| fIN = 347 MHz, AIN = –1 dBFS | 55.9 | |||||
| ENOB | Effective number of bits, large signal, excluding DC and FS/2 fixed spurs | fIN = 97 MHz, AIN = –1 dBFS | 9.0 | bits | ||
| fIN = 347 MHz, AIN = –1 dBFS | 9.0 | |||||
| SFDR | Spurious-free dynamic range, large signal, excluding DC and FS/2 fixed spurs | fIN = 97 MHz, AIN = –1 dBFS | 69 | dBFS | ||
| fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | 65 | |||||
| fIN = 347 MHz, AIN = –1 dBFS | 67 | |||||
| SFDR | Spurious-free dynamic range, small signal, excluding DC and FS/2 fixed spurs | fIN = 97 MHz, AIN = –16 dBFS | 75 | dBFS | ||
| fIN = 347 MHz, AIN = –16 dBFS | 72 | |||||
| FS/2 | FS/2 fixed interleaving spur, independent of input signal | No input | -71 | dBFS | ||
| HD2 | 2nd-order harmonic | fIN = 97 MHz, AIN = –1 dBFS | -75 | dBFS | ||
| fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | -72 | |||||
| fIN = 347 MHz, AIN = –1 dBFS | -67 | |||||
| HD3 | 3rd-order harmonic | fIN = 97 MHz, AIN = –1 dBFS | -71 | dBFS | ||
| fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | -67 | |||||
| fIN = 347 MHz, AIN = –1 dBFS | -69 | |||||
| FS/2-FIN | FS/2-FIN interleaving spur, signal dependent | fIN = 97 MHz, AIN = –1 dBFS | -77 | dBFS | ||
| fIN = 347 MHz, AIN = –1 dBFS | -71 | |||||
| SPUR | Worst harmonic 4th-order or higher | fIN = 97 MHz, AIN = –1 dBFS | -72 | dBFS | ||
| fIN = 347 MHz, AIN = –1 dBFS | -71 | |||||
| IMD3 | 3rd-order intermodulation | fIN = 97 MHz ± 5 MHz, AIN = –7 dBFS per tone |
-82 | dBFS | ||
| fIN = 347 MHz ± 5 MHz, AIN = –7 dBFS per tone |
-80 | |||||
| ADC12DL1500 | ||||||
| FPBW | Full-power input bandwidth (–3 dB)(1) | Foreground calibration | 8.0 | GHz | ||
| XTALK | Channel-to-channel crosstalk | Aggressor = 400 MHz, –1 dBFS | -93 | dB | ||
| Aggressor = 1000 MHz, –1 dBFS | -80 | |||||
| CER | Code error rate | Maximum CER | 10-18 | errors/ sample | ||
| NSD | Noise spectral density, no input signal | Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting | -148.0 | dBFS/Hz | ||
| Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting | -146.7 | |||||
| NF | Noise figure | Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting, no input, ZS = 100 Ω | 27.0 | dB | ||
| Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting, no input, ZS = 100 Ω | 26.3 | |||||
| NOISEDC | DC input noise standard deviation | No input, excludes DC offset, includes fixed interleaving spur (FS/2 spur) | 1.9 | LSB | ||
| SNR | Signal-to-noise ratio, large signal, excluding DC, HD2 to HD9 and interleaving spurs | fIN = 97 MHz, AIN = –1 dBFS | 56.6 | dBFS | ||
| fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | 57.3 | |||||
| fIN = 347 MHz, AIN = –1 dBFS | 56.7 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | 56.5 | |||||
| SNR | Signal-to-noise ratio, small signal, excluding DC, HD2 to HD9 and interleaving spurs | fIN = 97 MHz, AIN = –16 dBFS | 57 | dBFS | ||
| fIN = 347 MHz, AIN = –16 dBFS | 56.9 | |||||
| fIN = 797 MHz, AIN = –16 dBFS | 57.1 | |||||
| SINAD | Signal-to-noise and distortion ratio, large signal, excluding DC and FS/2 fixed spurs | fIN = 97 MHz, AIN = –1 dBFS | 55.7 | dBFS | ||
| fIN = 347 MHz, AIN = –1 dBFS | 56.3 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | 55.8 | |||||
| ENOB | Effective number of bits, large signal, excluding DC and FS/2 fixed spurs | fIN = 97 MHz, AIN = –1 dBFS | 9.0 | bits | ||
| fIN = 347 MHz, AIN = –1 dBFS | 9.1 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | 9.0 | |||||
| SFDR | Spurious-free dynamic range, large signal, excluding DC and FS/2 fixed spurs | fIN = 97 MHz, AIN = –1 dBFS | 67 | dBFS | ||
| fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | 65 | |||||
| fIN = 347 MHz, AIN = –1 dBFS | 65 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | 62 | |||||
| SFDR | Spurious-free dynamic range, small signal, excluding DC and FS/2 fixed spurs | fIN = 97 MHz, AIN = –16 dBFS | 72 | dBFS | ||
| fIN = 347 MHz, AIN = –16 dBFS | 72 | |||||
| fIN = 797 MHz, AIN = –16 dBFS | 73 | |||||
| FS/2 | FS/2 fixed interleaving spur, independent of input signal | No input | -74 | dBFS | ||
| HD2 | 2nd-order harmonic | fIN = 97 MHz, AIN = –1 dBFS | -71 | dBFS | ||
| fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | -71 | |||||
| fIN = 347 MHz, AIN = –1 dBFS | -71 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | -65 | |||||
| HD3 | 3rd-order harmonic | fIN = 97 MHz, AIN = –1 dBFS | -68 | dBFS | ||
| fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | -66 | |||||
| fIN = 347 MHz, AIN = –1 dBFS | -69 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | -69 | |||||
| FS/2-FIN | FS/2-FIN interleaving spur, signal dependent | fIN = 97 MHz, AIN = –1 dBFS | -74 | dBFS | ||
| fIN = 347 MHz, AIN = –1 dBFS | -73 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | -73 | |||||
| SPUR | Worst harmonic 4th-order or higher | fIN = 97 MHz, AIN = –1 dBFS | -72 | dBFS | ||
| fIN = 347 MHz, AIN = –1 dBFS | -70 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | -70 | |||||
| IMD3 | 3rd-order intermodulation | fIN = 97 MHz ± 5 MHz, AIN = –7 dBFS per tone |
-87 | dBFS | ||
| fIN = 347 MHz ± 5 MHz, AIN = –7 dBFS per tone |
-85 | |||||
| fIN = 797 MHz ± 5 MHz, AIN = –7 dBFS per tone |
-83 | |||||
| ADC12DL2500 | ||||||
| FPBW | Full-power input bandwidth (–3 dB)(1) | Foreground calibration | 8.0 | GHz | ||
| XTALK | Channel-to-channel crosstalk | Aggressor = 400 MHz, –1 dBFS | -83 | dB | ||
| Aggressor = 1000 MHz, –1 dBFS | -76 | |||||
| Aggressor = 3000 MHz, –1 dBFS | -59 | |||||
| CER | Code error rate | Maximum CER | 10-18 | errors/ sample | ||
| NSD | Noise spectral density, no input signal | Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting | -149.8 | dBFS/Hz | ||
| Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting | -148.3 | |||||
| NF | Noise figure | Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting, no input, ZS = 100 Ω | 25.2 | dB | ||
| Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting, no input, ZS = 100 Ω | 24.7 | |||||
| NOISEDC | DC input noise standard deviation | No input, excludes DC offset, includes fixed interleaving spur (FS/2 spur) | 2.0 | LSB | ||
| SNR | Signal-to-noise ratio, large signal, excluding DC, HD2 to HD9 and interleaving spurs | fIN = 97 MHz, AIN = –1 dBFS | 56.3 | dBFS | ||
| fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | 57 | |||||
| fIN = 347 MHz, AIN = –1 dBFS | 56.1 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | 56 | |||||
| fIN = 2397 MHz, AIN = –1 dBFS | 54.6 | |||||
| fIN = 2397 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | 55.1 | |||||
| SNR | Signal-to-noise ratio, small signal, excluding DC, HD2 to HD9 and interleaving spurs | fIN = 97 MHz, AIN = –16 dBFS | 56.8 | dBFS | ||
| fIN = 347 MHz, AIN = –16 dBFS | 56.5 | |||||
| fIN = 797 MHz, AIN = –16 dBFS | 56.7 | |||||
| fIN = 2397 MHz, AIN = –16 dBFS | 56.7 | |||||
| SINAD | Signal-to-noise and distortion ratio, large signal, excluding DC and FS/2 fixed spurs | fIN = 97 MHz, AIN = –1 dBFS | 55.9 | dBFS | ||
| fIN = 347 MHz, AIN = –1 dBFS | 55.7 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | 54.6 | |||||
| fIN = 2397 MHz, AIN = –1 dBFS | 53.2 | |||||
| ENOB | Effective number of bits, large signal, excluding DC and FS/2 fixed spurs | fIN = 97 MHz, AIN = –1 dBFS | 9.0 | bits | ||
| fIN = 347 MHz, AIN = –1 dBFS | 9.0 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | 8.8 | |||||
| fIN = 2397 MHz, AIN = –1 dBFS | 8.5 | |||||
| SFDR | Spurious-free dynamic range, large signal, excluding DC and FS/2 fixed spurs | fIN = 97 MHz, AIN = –1 dBFS | 65 | dBFS | ||
| fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | 65 | |||||
| fIN = 347 MHz, AIN = –1 dBFS | 66 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | 64 | |||||
| fIN = 2397 MHz, AIN = –1 dBFS | 60 | |||||
| fIN = 2397 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | 56 | |||||
| SFDR | Spurious-free dynamic range, small signal, excluding DC and FS/2 fixed spurs | fIN = 97 MHz, AIN = –16 dBFS | 74 | dBFS | ||
| fIN = 347 MHz, AIN = –16 dBFS | 72 | |||||
| fIN = 797 MHz, AIN = –16 dBFS | 72 | |||||
| fIN = 2397 MHz, AIN = –16 dBFS | 73 | |||||
| FS/2 | FS/2 fixed interleaving spur, independent of input signal | No input | -75 | dBFS | ||
| HD2 | 2nd-order harmonic | fIN = 97 MHz, AIN = –1 dBFS | -76 | dBFS | ||
| fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | -71 | |||||
| fIN = 347 MHz, AIN = –1 dBFS | -73 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | -68 | |||||
| fIN = 2397 MHz, AIN = –1 dBFS | -62 | |||||
| fIN = 2397 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | -59 | |||||
| HD3 | 3rd-order harmonic | fIN = 97 MHz, AIN = –1 dBFS | -68 | dBFS | ||
| fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | -66 | |||||
| fIN = 347 MHz, AIN = –1 dBFS | -68 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | -65 | |||||
| fIN = 2397 MHz, AIN = –1 dBFS | -63 | |||||
| fIN = 2397 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting | -58 | |||||
| FS/2-FIN | FS/2-FIN interleaving spur, signal dependent | fIN = 97 MHz, AIN = –1 dBFS | -72 | dBFS | ||
| fIN = 347 MHz, AIN = –1 dBFS | -72 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | -74 | |||||
| fIN = 2397 MHz, AIN = –1 dBFS | -68 | |||||
| SPUR | Worst harmonic 4th-order or higher | fIN = 97 MHz, AIN = –1 dBFS | -71 | dBFS | ||
| fIN = 347 MHz, AIN = –1 dBFS | -70 | |||||
| fIN = 797 MHz, AIN = –1 dBFS | -69 | |||||
| fIN = 2397 MHz, AIN = –1 dBFS | -69 | |||||
| IMD3 | 3rd-order intermodulation | fIN = 97 MHz ± 5 MHz, AIN = –7 dBFS per tone |
-80 | dBFS | ||
| fIN = 347 MHz ± 5 MHz, AIN = –7 dBFS per tone |
-79 | |||||
| fIN = 797 MHz ± 5 MHz, AIN = –7 dBFS per tone |
-83 | |||||
| fIN = 2397 MHz ± 5 MHz, AIN = –7 dBFS per tone |
-69 | |||||
(1) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB full-power input bandwidth.