ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

1 Features

Dual channel ADC
18-bit 10, 25, 65 MSPS ADC
Noise floor: -160 dBFS/Hz
Low power and optimized power scaling:
53 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS)
Latency: 1-2 clock cycles
18-bit, no missing codes
INL/DNL: ±7/ ±0.7 LSB (typical)
Reference: external or internal
Input bandwidth: 900 MHz (3-dB)
Industrial temperature range: -40 to +105°C
On-chip digital filter (optional)
- Decimation by 2, 4, 8, 16, 32
- 32-bit NCO
Serial LVDS digital interface (2-, 1- and 1/2-wire)
Small footprint: 40-QFN (5x5 mm) package
Spectral performance (f_IN = 5 MHz):
- SNR: 83.8 dBFS
- SFDR: 89 dBc HD2, HD3
- SFDR: 101 dBFS Worst spur
Spectral performance (f_IN = 20 MHz):
- SNR: 82.6 dBFS
- SFDR: 85 dBc HD2, HD3
- SFDR: 97 dBFS Worst spur