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ADS1293 Low-Power, 3-Channel, 24-Bit Analog Front-End for Biopotential Measurements
SNAS602C
FEBRUARY 2013 – December 2014
ADS1293
PRODUCTION DATA.
CONTENTS
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ADS1293 Low-Power, 3-Channel, 24-Bit Analog Front-End for Biopotential Measurements
1
Features
2
Applications
3
Description
4
Application Diagram
5
Revision History
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Write Timing Requirements
7.7
Read Timing Requirements
7.8
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Flexible Routing Switch
8.3.2
Battery Monitoring
8.3.3
Test Mode
8.3.4
Analog Front-End
8.3.5
Instrumentation Amplifier (INA)
8.3.5.1
Instrumentation Amplifier Fault Detection
8.3.6
Sigma-Delta Modulator (SDM)
8.3.6.1
Sigma-Delta Modulator Fault Detection
8.3.7
Programmable Digital Filters
8.3.8
Filter Settling Time
8.3.9
Analog Pace Channel
8.3.10
Wilson Reference
8.3.10.1
Wilson Central Terminal
8.3.10.2
Goldberger Terminals
8.3.11
Common-Mode (CM) Detector
8.3.11.1
Cable Shield Driving
8.3.11.2
Common-Mode Output Range (CMOR)
8.3.12
Right-Leg Drive (RLD)
8.3.13
Capacitive Load Driving
8.3.14
Error Status: RLD Rail
8.3.15
Lead-Off Detection (LOD)
8.3.16
DC Lead-Off Detect
8.3.17
Analog AC Lead-Off Detect
8.3.18
Digital AC Lead-Off Detect
8.3.19
Clock Oscillator
8.3.20
Synchronization
8.3.21
Single-Chip Multi-Channel Synchronization
8.3.22
Multichip Synchronization
8.3.23
Synchronization Errors
8.3.24
Alarm Functions
8.3.25
Error Filtering
8.3.26
ALARMB Pin and Error Masking
8.3.27
Error Register Automatic Clearing Description
8.3.28
Alarm Propagation
8.3.29
Reference Voltage Generators
8.3.30
Power Management
8.4
Device Functional Modes
8.4.1
Low Sampling Rate
8.4.2
High Sampling Rate
8.4.3
Ouput Code (ADCOUT)
8.5
Programming
8.5.1
Serial Digital Interface
8.5.2
Digital Output Drive Strength
8.5.3
SPI Protocol
8.5.4
Random Register Access Protocol
8.5.5
Auto-Incrementing Address
8.5.6
Streaming
8.5.7
Data Ready Bar
8.5.8
Simultaneous ECG and Pace Data Read
8.6
Register Maps
8.6.1
Operation Mode Registers
8.6.2
Input Channel Selection Registers
8.6.3
Lead-Off Detect Control Registers
8.6.4
Common-Mode Detection and Right-Leg Drive Common-Mode Feedback Control Registers
8.6.5
Wilson Control Registers
8.6.6
Reference Registers
8.6.7
OSC Control Registers
8.6.8
AFE Control Registers
8.6.9
Error Status Registers
8.6.10
Digital Registers
8.6.11
Pace and ECG Data Read Back Registers
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
3-Lead ECG Application
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
5-Lead ECG Application
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.3
Application Curves
9.2.3
8- or 12-Lead ECG Application
9.2.3.1
Design Requirements
9.2.3.2
Detailed Design Procedure
9.2.3.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Trademarks
12.2
Electrostatic Discharge Caution
12.3
Glossary
13
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
RSG|28
MPQF190A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snas602c_oa
snas602c_pm
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