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ADSxx54 Dual, High-Speed, 16-, 14-, and 12-Bit, Simultaneous-Sampling, Analog-to-Digital Converters
SBAS556B
October 2013 – August 2014
ADS7254
,
ADS7854
,
ADS8354
PRODUCTION DATA.
CONTENTS
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ADSxx54 Dual, High-Speed, 16-, 14-, and 12-Bit, Simultaneous-Sampling, Analog-to-Digital Converters
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison Table
6
Pin Configurations and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
Handling Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics: ADS8354
7.6
Electrical Characteristics: ADS7854
7.7
Electrical Characteristics: ADS7254
7.8
Electrical Characteristics: All Devices
7.9
Timing Requirements: Interface Mode
7.10
Timing Characteristics: Serial Interface
7.11
Typical Characteristics: ADS8354
7.12
Typical Characteristics: ADS7854
7.13
Typical Characteristics: ADS7254
7.14
Typical Characteristics: Common to ADS8354, ADS7854, and ADS7254
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Reference
8.3.2
Analog Inputs
8.3.2.1
Analog Input: Full-Scale Range Selection
8.3.2.2
Analog Input: Common-Mode Voltage Range
8.3.3
Transfer Function
8.4
Device Functional Modes
8.5
Register Maps and Serial Interface
8.5.1
Serial Interface
8.5.2
Write to User Programmable Registers
8.5.2.1
Configuration Register (CFR)
8.5.2.2
REFDAC Registers (REFDAC_A and REFDAC_B)
8.5.3
Data Read Operation
8.5.3.1
Reading User-Programmable Registers
8.5.3.2
Conversion Data Read
8.5.3.2.1
32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)
8.5.3.2.2
32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)
8.5.3.2.3
16-CLK, Dual-SDO Mode (CFR.B11 = 1, CFR.B10 = 0)
8.5.3.2.4
16-CLK, Single-SDO Mode (CFR.B11 = 1, CFR.B10 = 1)
8.5.4
Low-Power Modes
8.5.4.1
STANDBY Mode
8.5.4.2
Software Power-Down (SPD) Mode
8.5.5
Frame Abort, Reconversion, or Short-Cycling
9
Application and Implementation
9.1
Application Information
9.1.1
Input Amplifier Selection
9.1.2
Antialiasing Filter
9.2
Typical Applications
9.2.1
DAQ Circuit to Achieve Maximum SINAD for a 10-kHz Input Signal at Full Throughput
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
DAQ Circuit to Achieve Maximum SINAD for a 100-kHz Input Signal at Full Throughput
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.3
Application Curves
10
Power-Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Related Links
12.2
Related Documentation
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
RTE|16
MPQF149D
PW|16
MPDS361A
Thermal pad, mechanical data (Package|Pins)
RTE|16
QFND298F
Orderable Information
sbas556b_oa
sbas556b_pm
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