AM62Dx Sitara™ Processors

1 Features

Processor Cores:

Up to Quad Arm®Cortex®-A53 microprocessor subsystem at up to 1.4GHz
- Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
- Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
Single-core Arm®Cortex®-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
- 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
- 512KB SRAM with SECDED ECC
Single-core Arm®Cortex®-R5F at up to 800MHz, integrated to support Device Management
- 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
DSP with Matrix Multiplication Accelerator based on single-core C7x
- C7x floating point, up to 40GFLOPS, 256-bit Vector DSP at 1.0GHz
- Matrix Multiply Accelerator (MMA), up to 2TOPS (8b) at 1.0GHz
- 32KB L1 DCache with SECDED ECC and 64KB L1 ICache with Parity protection
- 1.25MB of L2 SRAM with SECDED ECC

Memory Subsystem:

Up to 2.29MB of On-chip RAM
- 64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
- 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
- 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
- 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
- 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
- 1.25MB of L2 SRAM with SECDED ECC in C7x
  DSP with Matrix Multiplication Accelerator
DDR Subsystem (DDRSS)
- Supports LPDDR4
- 32-bit data bus with inline ECC
- Supports speeds up to 3733MT/s
- Max addressable range of 8GBytes

Functional Safety:

Functional Safety-Compliant targeted [Automotive]
- Developed for functional safety applications
- Documentation will be available to aid functional safety system design
- Systematic capability up to ASIL D targeted
- Hardware integrity up to ASIL B targeted
AEC - Q100 qualified [Automotive]

Security:

Secure boot supported
- Hardware-enforced Root-of-Trust (RoT)
- Support to switch RoT via backup key
- Support for takeover protection, IP protection, and anti-roll back protection
Trusted Execution Environment (TEE) supported
- Arm TrustZone® based TEE
- Extensive firewall support for isolation
- Secure watchdog/timer/IPC
- Secure storage support
- Replay Protected Memory Block (RPMB) support
Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
Cryptographic acceleration supported
- Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
  - Supports cryptographic cores
- AES – 128-/192-/256-Bit key sizes
- SHA2 – 224-/256-/384-/512-Bit key sizes
- DRBG with true random number generator
- PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
Debugging security
- Secure software controlled debug access
- Security aware debugging

High-Speed Interfaces:

Integrated Ethernet switch supporting (total 2 external ports)
- RMII(10/100) or RGMII (10/100/1000)
- IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
- Clause 45 MDIO PHY management
- Packet Classifier based on ALE engine with 512 classifiers
- Priority based flow control
- Time Sensitive Networking (TSN) support
- Four CPU H/W interrupt Pacing
- IP/UDP/TCP checksum offload in hardware
Two USB2.0 Ports
- Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
- Integrated USB VBUS detection
One Camera Serial interface (CSI-2) Receiver with 4-Lane D-PHY
- High Speed External Processor Data Receive Interface over CSI-2 and MIPI D-PHY

General Connectivity:

Media and Data Storage:

3x Multi-Media Card/Secure Digital® (MMC/SD®/SDIO) interface
- 1x 8-bit eMMC interface up to HS200 speed
- 2x 4-bit SD/SDIO interface up to UHS-I
- Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
1× General-Purpose Memory Controller (GPMC) up to 133MHz
- Flexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
- Uses BCH code to support 4-, 8-, or 16-bit ECC
- Uses Hamming code to support 1-bit ECC
- Error Locator Module (ELM)
  - Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
  - Supports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithms
OSPI/QSPI with DDR / SDR support
- Support for Serial NAND and Serial NOR Flash devices
- 4GBytes memory address support
- XIP mode with optional on-the-fly encryption

Power Management:

Low-power modes supported by Device/Power Manager
- Partial IO support for CAN/GPIO/UART wakeup

Boot Options:

Technology / Package: