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  • AMC1106x Small, High-Precision, Basic Isolated Delta-Sigma Modulators

    • SBAS789B October   2017  – April 2020 AMC1106E05 , AMC1106M05

      PRODUCTION DATA.  

  • CONTENTS
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  • AMC1106x Small, High-Precision, Basic Isolated Delta-Sigma Modulators
  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics: AMC1106x
    10. 7.10 Timing Requirements
    11. 7.11 Switching Characteristics
    12. 7.12 Insulation Characteristics Curves
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 Modulator
      3. 8.3.3 Isolation Channel Signal Transmission
      4. 8.3.4 Digital Output
      5. 8.3.5 Manchester Coding Feature
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fail-Safe Output
      2. 8.4.2 Output Behavior in Case of a Full-Scale Input
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Digital Filter Usage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
      4. 9.2.4 What To Do and What Not To Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
        1. 12.1.1.1 Isolation Glossary
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

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DATA SHEET

AMC1106x Small, High-Precision, Basic Isolated Delta-Sigma Modulators

1 Features

  • ±50-mV input voltage range optimized for current measurement with shunt resistors
  • Manchester coded or uncoded bitstream options
  • Excellent DC performance for high-precision sensing on system level:
    • Offset error and drift: ±50 µV, ±1 µV/°C (max)
    • Gain error and drift: ±0.2%, ±40 ppm/°C (max)
  • 3.3-V operation for reduced power dissipation on both sides of the isolation barrier
  • System-level diagnostic features
  • High electromagnetic field immunity
    (see the ISO72x Digital Isolator Magnetic-Field Immunity application report)
  • Safety-related certifications:
    • 5657-VPK basic isolation per DIN VDE V 0884-11: 2017-01
    • 4000-VRMS isolation for 1 minute per UL1577
    • CAN/CSA No. 5A-component acceptance service notice
      and DIN EN 61010-1 end equipment standard

2 Applications

    Shunt-resistor-based current sensing in 3-phase electricity meters

3 Description

The AMC1106 is a precision, delta-sigma (ΔΣ) modulator with the output separated from the input circuitry by a capacitive isolation barrier that is highly resistant to magnetic interference.

The input stage of the AMC1106 is optimized for direct connection to shunt resistors or other low voltage-level signal sources commonly used in multi-phase electricity meters to achieve excellent ac and dc performance. The device low input voltage range of ±50-mV allows use of small shunt resistor values to minimize power dissipation. Decimate the output bitstream of the AMC1106 with an appropriate digital filter. The MSP430F67x, TMS320F2807x, and TMS320F2837x microcontrollers, and the AMC1210 integrate these digital filters for seamless operation with the AMC1106.

On the high-side, the modulator is supplied by a
3.3-V or 5-V power supply (AVDD). The isolated digital interface operates from a 3.0-V, 3.3-V, or 5-V power supply (DVDD).

The AMC1106 is specified over the extended industrial temperature range of –40°C to +125°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
AMC1106x SOIC (8) 5.85 mm × 7.50 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Device Images

Simplified Schematic

AMC1106E05 AMC1106M05 fbd_bas789.gif

4 Revision History

Changes from A Revision (June 2018) to B Revision

  • Changed safety-related certifications details as per ISO standardGo
  • Changed CLR and CPG values from 9 mm to 8.5 mm in Insulation Specifications tableGo
  • Changed Insulation Specifications table per ISO standard Go
  • Changed Safety-Related Certification table per ISO standardGo
  • Changed Safety Limiting Values table format per latest standardGo

Changes from * Revision (October 2017) to A Revision

  • Changed test conditions of DTI parameterGo
  • Changed test conditions of VIOSM parameterGo
  • Changed test conditions of second qpd parameter row Go
  • Changed test conditions of third qpd parameter row Go
  • Changed VDE certification details in Safety Related Certifications tableGo
  • Changed Block Diagram of an Isolation Channel figureGo

5 Device Comparison Table

PART NUMBER DIGITAL OUTPUT INTERFACE
AMC1106E05 Manchester coded CMOS
AMC1106M05 Uncoded CMOS

6 Pin Configuration and Functions

DWV Package
8-Pin SOIC
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 AVDD — Analog (high-side) power supply, 3.0 V to 5.5 V.
See the Power Supply Recommendations section for decoupling recommendations.
2 AINP I Noninverting analog input
3 AINN I Inverting analog input
4 AGND — Analog (high-side) ground reference
5 DGND — Digital (controller-side) ground reference
6 DOUT O Modulator data output. This pin is a Manchester coded output for the AMC1106E05.
7 CLKIN I Modulator clock input
8 DVDD — Digital (controller-side) power supply, 2.7 V to 5.5 V.
See the Power Supply Recommendations section for decoupling recommendations.

7 Specifications

7.1 Absolute Maximum Ratings

see (1)
MIN MAX UNIT
Supply voltage, AVDD to AGND or DVDD to DGND –0.3 6.5 V
Analog input voltage at AINP, AINN AGND – 6 AVDD + 0.5 V
Digital output voltage at DOUT, or digital input voltage on CLKIN DGND – 0.5 DVDD + 0.5 V
Input current to any pin except supply pins –10 10 mA
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Analog (high-side) supply voltage (AVDD to AGND) 3.0 5.0 5.5 V
DVDD Digital (controller-side) supply voltage (DVDD to DGND) 2.7 3.3 5.5 V
TA Operating ambient temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) AMC1106x UNIT
DWV (SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance 112.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 47.6 °C/W
RθJB Junction-to-board thermal resistance 60.0 °C/W
ψJT Junction-to-top characterization parameter 23.1 °C/W
ψJB Junction-to-board characterization parameter 60.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD Maximum power dissipation
(both sides)		 AMC1106E05, AVDD = DVDD = 5.5 V 91.85 mW
AMC1106M05, AVDD = DVDD = 5.5 V 86.90
PD1 Maximum power dissipation
(high-side supply)		 AVDD = 5.5 V 53.90 mW
PD2 Maximum power dissipation
(low-side supply)		 AMC1106E05, AVDD = DVDD = 5.5 V 37.95 mW
AMC1106M05, AVDD = DVDD = 5.5 V 33.00

7.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air ≥ 8.5 mm
CPG External creepage(1) Shortest pin-to-pin distance across the package surface ≥ 8.5 mm
DTI Distance through insulation Minimum internal gap (internal clearance) of the insulation ≥ 0.021 mm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material group According to IEC 60664-1 I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 300 VRMS I-IV
Rated mains voltage ≤ 600 VRMS I-IV
DIN VDE V 0884-11: 2017-01(2)
VIORM Maximum repetitive peak isolation voltage At ac voltage (bipolar) 849 VPK
VIOWM Maximum-rated isolation working voltage At ac voltage (sine wave) 600 VRMS
At dc voltage 849 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification test) 5657 VPK
VTEST = 1.2 × VIOTM, t = 1 s (100% production test) 6789
VIOSM Maximum surge isolation voltage(3) Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.3 × VIOSM = 7800 VPK (qualification) 		6000 VPK
qpd Apparent charge(4) Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.2 × VIORM = 1019 VPK, tm = 10 s		 ≤ 5 pC
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.3 × VIORM = 1104 VPK, tm = 10 s 		≤ 5
Method b1, at routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s,
Vpd(m) = 1.5 × VIORM = 1274 VPK, tm = 1 s 		≤ 5
CIO Barrier capacitance, input to output(5) VIO = 0.5 VPP at 1 MHz 1.2 pF
RIO Insulation resistance, input to output(5) VIO = 500 V at TS = 150°C > 109 Ω
Pollution degree 2
Climatic category 40/125/21
UL1577
VISO Withstand isolation voltage VTEST = VISO = 4000 VRMS or 5657 VDC, t = 60 s (qualification), VTEST = 1.2 × VISO = 4800 VRMS, t = 1 s (100% production test) 4000 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves and ribs on the PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.

7.7 Safety-Related Certifications

VDE UL
Certified according to DIN VDE V 0884-11: 2017-01 and DIN EN 61010-1 (VDE 0411-1): 2011-07 Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
Basic insulation Single protection
Certificate number: 40047657 File number: E181974

7.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IS Safety input, output, or supply current,
see Figure 3 		RθJA = 112.2°C/W, VDD1 = VDD2 = 5.5 V,
TJ = 150°C, TA = 25°C		 202.5 mA
RθJA = 112.2°C/W, VDD1 = VDD2 = 3.6 V,
TJ = 150°C, TA = 25°C		 309.4
PS Safety input, output, or total power,
see Figure 4 		RθJA = 112.2°C/W, TJ = 150°C, TA = 25°C 1114(1) mW
TS Maximum safety temperature 150 °C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × AVDDmax + IS × AVDDmax, where AVDDmax is the maximum high-side supply voltage and DVDDmax is the maximum controller-side supply voltage.

7.9 Electrical Characteristics: AMC1106x

minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, AINP = –50 mV to 50 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
VClipping Differential input voltage before clipping output VIN = AINP – AINN ±64 mV
FSR Specified linear differential full-scale VIN = AINP – AINN –50 50 mV
Absolute common-mode input voltage(1) (AINP + AINN) / 2 to AGND –2 AVDD V
VCM Operating common-mode input voltage (AINP + AINN) / 2 to AGND –0.032 AVDD – 2.1 V
VCMov Common-mode overvoltage detection level(2) (AINP + AINN) / 2 to AGND AVDD – 2 V
CIN Single-ended input capacitance AINN = AGND 4 pF
CIND Differential input capacitance 2 pF
IIB Input bias current AINP = AINN = AGND, IIB = IIBP + IIBN –97 –72 –57 µA
RIN Single-ended input resistance AINN = AGND 4.75 kΩ
RIND Differential input resistance 4.9 kΩ
IIO Input offset current ±10 nA
CMTI Common-mode transient immunity 15 kV/µs
CMRR Common-mode rejection ratio AINP = AINN, fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max 		–99 dB
AINP = AINN, fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max 		–98
BW Input bandwidth(3) 800 kHz
DC ACCURACY
DNL Differential nonlinearity Resolution: 16 bits –0.99 0.99 LSB
INL Integral nonlinearity(4) Resolution: 16 bits, 4.5 V ≤ AVDD ≤ 5.5 V –4 ±1 4 LSB
Resolution: 16 bits, 3.0 V ≤ AVDD ≤ 3.6 V –5 ±1.5 5
EO Offset error Initial, at 25°C, AINP = AINN = AGND –50 ±2.5 50 µV
TCEO Offset error thermal drift(5) –1 ±0.25 1 μV/°C
EG Gain error Initial, at 25°C –0.2% ±0.005% 0.2%
TCEG Gain error thermal drift(6) –40 ±20 40 ppm/°C
PSRR Power-supply rejection ratio AINP = AINN = AGND,
3.0 V ≤ AVDD ≤ 5.5 V, at dc		 –108 dB
AINP = AINN = AGND,
3.0 V ≤ AVDD ≤ 5.5 V,
10 kHz, 100-mV ripple		 –107
AC ACCURACY
SNR Signal-to-noise ratio fIN = 1 kHz 78 82.5 dB
SINAD Signal-to-noise + distortion fIN = 1 kHz 77.5 82.3 dB
THD Total harmonic distortion 4.5 V ≤ AVDD ≤ 5.5 V,
5 MHz ≤ fCLKIN ≤ 21 MHz, fIN = 1 kHz		 –98 –84 dB
3.0 V ≤ AVDD ≤ 3.6 V,
5 MHz ≤ fCLKIN ≤ 20 MHz, fIN = 1 kHz		 –93 –83
SFDR Spurious-free dynamic range fIN = 1 kHz 83 100 dB
DIGITAL INPUTS/OUTPUTS (CMOS Logic With Schmitt-Trigger)
IIN Input current DGND ≤ VCLKIN ≤ DVDD 0 7 µA
CIN Input capacitance 4 pF
VIH High-level input voltage 0.7 × DVDD DVDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 × DVDD V
VOH High-level output voltage IOH = –20 µA DVDD – 0.1 V
IOH = –4 mA DVDD – 0.4
VOL Low-level output voltage IOL = 20 µA 0.1 V
IOL = 4 mA 0.4
CLOAD Output load capacitance 30 pF
POWER SUPPLY
IAVDD High-side supply current 3.0 V ≤ AVDD ≤ 3.6 V 6.3 8.5 mA
4.5 V ≤ AVDD ≤ 5.5 V 7.2 9.8
IDVDD Controller-side supply current AMC1106E05, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF		 4.1 5.5 mA
AMC1106M05, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF		 3.3 4.8
AMC1106E05, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF		 5.0 6.9
AMC1106M05, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF		 3.9 6.0
(1) Steady-state voltage supported by the device in case of a system failure. See the specified common-mode input voltage VCM for normal operation. Observe the analog input voltage range as specified in the Absolute Maximum Ratings table.
(2) The common-mode overvoltage detection level has a typical hysteresis of 90 mV.
(3) This parameter is the –3-dB, second-order, roll-off frequency of the integrated differential input amplifier to consider for antialiasing filter designs.
(4) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as a number of LSBs or as a percent of the specified linear full-scale range (FSR).
(5) Offset error drift is calculated using the box method, as described by the following equation:
AMC1106E05 AMC1106M05 ec_eodrift_bas654.gif
(6) Gain error drift is calculated using the box method, as described by the following equation:
AMC1106E05 AMC1106M05 ec_egdrift_bas654.gif

7.10 Timing Requirements

over operating ambient temperature range (unless otherwise noted)
MIN NOM MAX UNIT
fCLKIN CLKIN clock frequency 4.5 V ≤ AVDD ≤ 5.5 V 5 21 MHz
3.0 V ≤ AVDD ≤ 5.5 V 5 20
tCLKIN CLKIN clock period,
see Figure 1 		4.5 V ≤ AVDD ≤ 5.5 V 47.6 200 ns
3.0 V ≤ AVDD ≤ 5.5 V 50 200
tHIGH CLKIN clock high time, see Figure 1 20 25 120 ns
tLOW CLKIN clock low time, see Figure 1 20 25 120 ns

7.11 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tH DOUT hold time after rising edge
of CLKIN, see Figure 1 		AMC1106M05(1), CLOAD = 15 pF 3.5 ns
tD Rising edge of CLKIN to DOUT valid delay, see Figure 1 AMC1106M05(1), CLOAD = 15 pF 15 ns
tr DOUT rise time, see Figure 1 10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF		 0.8 3.5 ns
10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF		 1.8 3.9
tf DOUT fall time, see Figure 1 90% to 10%, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF		 0.8 3.5 ns
90% to 10%, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF		 1.8 3.9
tISTART Interface startup time,
see Figure 2 		DVDD at 2.7 V (min) to DOUT valid with AVDD ≥ 3.0 V 32 32 tCLKIN
tASTART Analog startup time,
see Figure 2 		AVDD step to 3.0 V with DVDD ≥ 2.7 V, 0.1% settling 0.5 ms
(1) The output of the Manchester encoded versions of the AMC1106E05 can change with every edge of CLKIN with a typical delay of 6 ns; see the Manchester Coding Feature section for additional details.
AMC1106E05 AMC1106M05 tim_int_bas734.gifFigure 1. Digital Interface Timing
AMC1106E05 AMC1106M05 tim_start_bas734.gifFigure 2. Device Startup Timing

 
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