The bq78z100 device provides a fully integrated pack-based solution with a flash programmable custom reduced instruction-set CPU (RISC), safety protection, and authentication for 1-series to 2-series cell Li-Ion and Li-Polymer battery packs.
The bq78z100 gas gauge communicates via an I2C-compatible interface or single-wire HDQ interface and combines an ultra-low-power, high-speed TI bqBMP processor, high-accuracy analog measurement capabilities, integrated flash memory, an array of peripheral and communication ports, an N-channel FET drive, and a SHA-1 Authentication transform responder into a complete, high-performance battery management solution.
The bq78z100 device provides an array of battery and system safety functions, including overcurrent in discharge, short circuit in charge, and short circuit in discharge protection for the battery, as well as FET protection for the N-channel FETs, internal AFE watchdog, and cell balancing. Through firmware, the devices can provide a larger array of features including protection against overvoltage, undervoltage, overtemperature, and more.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
bq78z100 | VSON (12) | 4.00 mm × 2.50 mm |
DATE | REVISION | NOTES |
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September 2015 | * | Initial Release |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | DRZ | ||
VSS | 1 | P | Device ground |
SRN | 2 | IA | Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN where SRP is the top of the sense resistor. |
SRP | 3 | IA | Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN where SRP is the top of the sense resistor. |
TS1 | 4 | IA | Input for ADC to the oversampled ADC channel |
SCL | 5 | I/O | Serial Clock for the I2C interface; requires an external pullup when used |
SDA/HDQ | 6 | I/O | Serial Data for the I2C and HDQ interfaces; requires an external pullup |
DSG | 7 | O | N-Channel FET drive output pin |
PACK | 8 | IA, P | Pack sense input pin |
CHG | 9 | O | N-Channel FET drive output pin |
PBI | 10 | P | Power supply backup input pin |
VC2 | 11 | IA, P | Sense voltage input pin for most positive cell, balance current input for most positive cell. Primary power supply input and battery stack measurement input (BAT) |
VC1 | 12 | IA | Sense voltage input pin for least positive cell, balance current input for least positive cell |
PWPD | — | Exposed Pad, electrically connected to VSS (external trace) |