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CC113L Value Line Receiver
SWRS108B
May 2011 – June 2014
CC113L
PRODUCTION DATA.
CONTENTS
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CC113L Value Line Receiver
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Terminal Configuration and Functions
3.1
Pin Diagram
3.2
Signal Descriptions
4
Specifications
4.1
Absolute Maximum Ratings
4.2
Handling Ratings
4.3
Recommended Operating Conditions
4.4
General Characteristics
4.5
Current Consumption
4.5.1
Typical RX Current Consumption over Temperature and Input Power Level, 868/915 MHz
4.6
RF Receive Section
4.6.1
Typical Sensitivity over Temperature and Supply Voltage, 868 MHz, Sensitivity Optimized Setting
4.6.2
Typical Sensitivity over Temperature and Supply Voltage, 915 MHz, Sensitivity Optimized Setting
4.6.3
Blocking and Selectivity
4.7
Crystal Oscillator
4.8
Frequency Synthesizer Characteristics
4.9
DC Characteristics
4.10
Power-On Reset
4.11
Thermal Characteristics
4.12
Typical Characteristics
4.12.1
Typical Characteristics, RX Current Consumption
4.12.2
Typical Characteristics, Blocking and Selectivity
5
Detailed Description
5.1
Overview
5.2
Functional Block Diagram
5.3
Configuration Overview
5.4
Configuration Software
5.5
4-wire Serial Configuration and Data Interface
5.5.1
Chip Status Byte
5.5.2
Register Access
5.5.3
SPI Read
5.5.4
Command Strobes
5.5.5
RX FIFO Access
5.6
Microcontroller Interface and Pin Configuration
5.6.1
Configuration Interface
5.6.2
General Control and Status Pins
5.7
Data Rate Programming
5.8
Receiver Channel Filter Bandwidth
5.9
Demodulator, Symbol Synchronizer, and Data Decision
5.9.1
Frequency Offset Compensation
5.9.2
Bit Synchronization
5.9.3
Byte Synchronization
5.10
Packet Handling Hardware Support
5.10.1
Packet Format
5.10.1.1
Arbitrary Length Field Configuration
5.10.1.2
Packet Length > 255
5.10.2
Packet Filtering
5.10.2.1
Address Filtering
5.10.2.2
Maximum Length Filtering
5.10.2.3
CRC Filtering
5.10.3
Packet Handling in Receive Mode
5.10.4
Packet Handling in Firmware
5.11
Modulation Formats
5.11.1
Frequency Shift Keying
5.11.2
Amplitude Modulation
5.12
Received Signal Qualifiers and RSSI
5.12.1
Sync Word Qualifier
5.12.2
RSSI
5.12.3
Carrier Sense (CS)
5.12.3.1
CS Absolute Threshold
5.12.3.2
CS Relative Threshold
5.13
Radio Control
5.13.1
Power-On Start-Up Sequence
5.13.1.1
Automatic POR
5.13.1.2
Manual Reset
5.13.2
Crystal Control
5.13.3
Voltage Regulator Control
5.13.4
Receive Mode (RX)
5.13.5
RX Termination
5.13.6
Timing
5.13.6.1
Overall State Transition Times
5.13.6.2
Frequency Synthesizer Calibration Time
5.14
RX FIFO
5.15
Frequency Programming
5.16
VCO
5.16.1
VCO and PLL Self-Calibration
5.17
Voltage Regulators
5.18
General Purpose and Test Output Control Pins
5.19
Asynchronous and Synchronous Serial Operation
5.19.1
Asynchronous Serial Operation
5.19.2
Synchronous Serial Operation
5.20
System Consideration and Guidelines
5.20.1
SRD Regulations
5.20.2
Calibration in Multi-Channel Systems
5.21
Configuration Registers
5.21.1
Configuration Register Details - Registers with preserved values in SLEEP state
5.21.2
Configuration Register Details - Registers that Loose Programming in SLEEP State
5.21.3
Status Register Details
5.22
Development Kit Ordering Information
6
Applications, Implementation, and Layout
6.1
Bias Resistor
6.2
Balun and RF Matching
6.2.1
Balun and RF Matching (Low-Cost Application Circuit)
6.2.2
Balun and RF Matching (Characterization Circuit)
6.3
Crystal
6.4
Reference Signal
6.5
Power Supply Decoupling
6.6
PCB Layout Recommendations
7
Device and Documentation Support
7.1
Device Support
7.1.1
Device Nomenclature
7.2
Documentation Support
7.2.1
Related Documentation from Texas Instruments
7.2.2
Community Resources
7.3
Trademarks
7.4
Electrostatic Discharge Caution
7.5
Export Control Notice
7.6
Glossary
7.7
Additional Acronyms
8
Mechanical Packaging and Orderable Information
8.1
Packaging Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
RGP|20
MPQF126G
Thermal pad, mechanical data (Package|Pins)
RGP|20
QFND856
Orderable Information
swrs108b_oa
swrs108b_pm
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