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CSD97396Q4M Synchronous Buck NexFET™ Power Stage
SLPS572
December 2015
CSD97396Q4M
PRODUCTION DATA.
CONTENTS
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CSD97396Q4M Synchronous Buck NexFET™ Power Stage
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Powering CSD97396Q4M and Gate Drivers
7.3.2
Undervoltage Lockout (UVLO) Protection
7.3.3
PWM Pin
7.3.4
SKIP# Pin
7.3.4.1
Zero Crossing (ZX) Operation
7.3.5
Integrated Boost-Switch
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Application Curves
8.3
System Example
8.3.1
Power Loss Curves
8.3.2
SOA Curves
8.3.3
Normalized Curves
8.3.4
Calculating Power Loss and SOA
8.3.4.1
Design Example
8.3.4.2
Calculating Power Loss
8.3.4.3
Calculating SOA Adjustments
9
Layout
9.1
Layout Guidelines
9.1.1
Recommended PCB Design Overview
9.1.2
Electrical Performance
9.2
Layout Example
9.3
Thermal Considerations
10
Device and Documentation Support
10.1
Community Resources
10.2
Trademarks
10.3
Electrostatic Discharge Caution
10.4
Glossary
11
Mechanical, Packaging, and Orderable Information
11.1
Mechanical Drawing
11.2
Recommended PCB Land Pattern
11.3
Recommended Stencil Opening
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
DPC|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slps572_oa
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