EMB1412 MOSFET Gate Driver

1 Features

Compound CMOS and Bipolar Outputs Reduce Output Current Variation
7 A Sink/3 A Source Current
Fast Propagation Times (25 ns Typical)
Fast Rise and Fall Times (14 ns/12 ns Rise/Fall with 2 nF Load)
Inverting and Non-Inverting Inputs Provide Either Configuration with a Single Device
Supply Rail Under-Voltage Lockout Protection
Dedicated Input Ground (IN_REF) for Split Supply or Single Supply Operation
Thermally Enhanced 8-Pin VSSOP Package
Output Swings from V_CC to V_EE Which can be Negative Relative to Input Ground

2 Applications

Li-Ion Battery Management Systems
Hybrid and Electric Vehicles
Grid Storage
48 V Systems Supply
UPS

3 Description

The EMB1412 MOSFET gate driver provides high peak gate drive current in 8-lead exposed-pad VSSOP package, with improved power dissipation required for high frequency operation. The compound output driver stage includes MOS and bipolar transistors operating in parallel that together sink more than 7-A peak from capacitive loads. Combining the unique characteristics of MOS and bipolar devices reduces drive current variation with voltage and temperature. Under-voltage lockout protection is provided to prevent damage to the MOSFET due to insufficient gate turn-on voltage. The EMB1412 provides both inverting and non-inverting inputs to satisfy requirements for inverting and non-inverting gate drive with a single device type.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
EMB1412	HVSSOP (8)	3.00 mm x 3.00 mm

For all available packages, see the orderable addendum at the end of the datasheet.

4 Revision History

Changes from A Revision (May 2013) to B Revision

Added Handling Ratings Table Go
Changed layout of National Data Sheet to TI format.Go

5 Pin Configuration and Functions

VSSOP (DGN)

8 Pins

Top View

Pin Functions

PIN	NAME	DESCRIPTION	APPLICATION INFORMATION
1	IN_REF	Ground reference for control inputs	Connect to power ground (VEE) for standard positive only output voltage swing. Connect to system logic ground when VEE is connected to a negative gate drive supply.
2	INB	Inverting input pin	TTL compatible thresholds. Connect to IN_REF when not used.
3	VEE	Power ground for driver outputs	Connect to either power ground or a negative gate drive supply for positive or negative voltage swing.
4	IN	Non-inverting input pin	TTL compatible thresholds. Pull up to VCC when not used.
5, 8	N/C	Not internally connected
6	VCC	Positive Supply voltage input	Locally decouple to VEE. The decoupling capacitor should be located close to the chip.
7	OUT	Gate drive output	Capable of sourcing 3 A and sinking 7 A. Voltage swing of this output is from VEE to VCC.
- - -	Exposed Pad	Exposed Pad, underside of package	Internally bonded to the die substrate. Connect to VEE ground pin for low thermal impedance.

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

	MIN	MAX	UNIT
V_CC to V_EE	−0.3	15	V
V_CC to IN_REF	−0.3	15	V
IN/INB to IN_REF	−0.3	15	V
IN_REF to V_EE	−0.3	5	V
Maximum junction temperature		150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–55	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾		2	kV

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
Operating Junction Temperature		−40		125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		EMB1412	UNIT
		VSSOP (DGN)
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	60⁽²⁾	°C/W
R_θJCbot	Junction-to-case (bottom) thermal resistance	4.7	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The primary goal of the thermal management is to maintain the integrated circuit (IC) junction temperature (T_J) below a specified limit to ensure reliable long term operation. The maximum T_J of IC components should be estimated in worst case operating conditions. The junction temperature can be calculated based on the power dissipated on the IC and the junction to ambient thermal resistance R_θJA for the IC package in the application board and environment. The R_θJA is not a given constant for the package and depends on the PCB design and the operating environment.

6.5 Electrical Characteristics

T_J = −40°C to 125°C, V_CC = 12 V, INB = IN_REF = V_EE = 0 V, No Load on output, unless otherwise specified.

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY
V_CC	V_CC Operating Range	V_CC – IN_REF and V_CC - V_EE	3.5		14	V
UVLO	V_CC Under-voltage Lockout (rising)	V_CC – IN_REF	2.4	3.0	3.5	V
V_CCH	V_CC Under-voltage Hysteresis			230		mV
I_CC	V_CC Supply Current			1.0	2.0	mA
CONTROL INPUTS
V_IH	Logic High		2.3			V
V_IL	Logic Low				0.8	V
V_thH	High Threshold		1.3	1.75	2.3	V
V_thL	Low Threshold		0.8	1.35	2.0	V
HYS	Input Hysteresis			400		mV
I_IL	Input Current Low	IN = INB = 0 V	-1	0.1	1	µA
I_IH	Input Current High	IN = INB = V_CC	-1	0.1	1	µA
OUTPUT DRIVER
R_OH	Output Resistance High	I_OUT = -10 mA⁽¹⁾		30	50	Ω
R_OL	Output Resistance Low	I_OUT = 10 mA⁽¹⁾		1.4	2.5	Ω
I_SOURCE	Peak Source Current	OUT = V_CC/2, 200 ns pulsed current		3		A
I_SINK	Peak Sink Current	OUT = V_CC/2, 200 ns pulsed current		7		A
SWITCHING CHARACTERISTICS
td1	Propagation Delay Time Low to High, IN/ INB rising ( IN to OUT)	C_LOAD = 2 nF		25	40	ns
td2	Propagation Delay Time High to Low, IN / INB falling (IN to OUT)	C_LOAD = 2 nF		25	40	ns
tr	Rise time	C_LOAD = 2 nF		14		ns
tf	Fall time	C_LOAD = 2 nF		12		ns
LATCHUP PROTECTION
	AEC –Q100, METHOD 004	T_J = 150°C		500		mA
THERMAL RESISTANCE
R_θJA	Junction to Ambient, 0 LFPM Air Flow	VSSOP Package		60		°C/W
R_θJC	Junction to Case	VSSOP Package		4.7		°C/W

(1) The output resistance specification applies to the MOS device only. The total output current capability is the sum of the MOS and Bipolar devices.

Figure 1. (A) Inverting

Figure 2. (B) Non-Inverting