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  • ISO1228 Eight-Channel Isolated Digital Input with Current Limit and Diagnostics

    • SLLSFN5A June   2023  – February 2024 ISO1228

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  • ISO1228 Eight-Channel Isolated Digital Input with Current Limit and Diagnostics
  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics—DC Specification
    10. 5.10 Switching Characteristics—AC Specification
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Test Circuits
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Surge Protection
      2. 7.3.2  Field Side LED Indication
      3. 7.3.3  Serial and Parallel Output option
      4. 7.3.4  Cyclic Redundancy Check (CRC)
      5. 7.3.5  FAULT Indication
      6. 7.3.6  Digital Low Pass Filter
      7. 7.3.7  SPI Register Map
      8. 7.3.8  SPI Interface Timing - Non-Daisy Chain
      9. 7.3.9  SPI Interface Timing - Daisy Chain
      10. 7.3.10 SPI Interface Timing - Burst Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Sinking Type Digital Inputs
      2. 8.2.2 Sourcing Type Digital Inputs
      3. 8.2.3 Design Requirements
        1. 8.2.3.1 Detailed Design Procedure
          1. 8.2.3.1.1 Current Limit
          2. 8.2.3.1.2 Voltage Thresholds
          3. 8.2.3.1.3 Wire-Break Detection
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information
  15. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DFB|38
    • MPSS151A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
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  • sllsfn5a_pm
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Data Sheet

ISO1228 Eight-Channel Isolated Digital Input with Current Limit and Diagnostics

1 Features

  • Configurable IEC 61131-2 eight Type 1/3 or four Type 2 Isolated Digital Inputs
  • Low Power and Heat Dissipation
    • Selectable input current limit
    • Fieldside LED drivers using input current
  • Configurable sinking or sourcing type inputs
  • Wire-break detection in sink mode
  • Integrated field-side power loss detection
  • Programmable Glitch Filters
  • Built in CRC check across barrier
  • Serial SPI and Parallel output options
    • Supports SPI daisy chaining
    • Supports SPI burst mode
  • Integrated IEC ESD and Surge Protection
  • High CMTI(Typ): 75kV/µs
  • VCC1 Logic supply voltage range: 1.71V to 5.5V
  • AVCC field supply voltage range (sink mode): 8.5V to 36V
  • AVCC field supply voltage range (source mode): 13V to 36V
  • Ambient temperature range: –40°C to 125°C
  • Small Footprint 38-SSOP Package
  • Safety-related certifications:
    • 4242-VPK VIOTM and 637-VPK VIORM per DIN EN IEC 60747-17 (VDE 0884-17)
    • 3000-VRMS Isolation for 1 Minute per UL 1577
    • IEC 62368-1, IEC 61010-1 Certifications
    • All Certifications Planned

2 Applications

  • Programmable Logic Controllers (PLC)
    • Digital Input Modules
    • Mixed Input Modules
  • Motor Drive Digital Inputs
  • Binary Input Modules
  • CNC Control
  • Industrial Transport Digital Inputs

3 Description

The ISO1228 is an eight-channel isolated 24V digital input receiver, configurable to IEC 61131-2 Type 1, and 3 characteristics or four-channel Type 2 characteristics. The ISO1228 includes resistor-programmable accurate current limit and field side input-current-powered LED indication to reduce system power dissipation and reduce board temperatures. ISO1228 can be configured for either sourcing or sinking type digital inputs with minimal hardware change. Both serial SPI and parallel output modes are available. Wire-break detection, fieldside supply monitoring and built-in CRC across barriers help improve system reliability. In-built glitch filters and integrated IEC-ESD and surge protection help to achieve a robust design.

The ISO1228 operates over the logic supply range of 1.71V to 5.5V, supporting 1.8V, 2.5-V, 3.3V, and 5V controllers. Field side output voltage range supported is 8.5V to 36V in sink mode and 13V to 36V in source mode.ISO1228 supports up to 1.5Mbps data rates passing a minimum pulse width of 667ns for high-speed operation.

Device Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE (NOM)
ISO1228 SSOP (38) DFB 9.9mm × 6.0mm 9.9mm × 3.90mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value andincludes pins, where applicable.
GUID-20230303-SS0I-JBKZ-PW4J-SQ9FB1QFLL0Z-low.svgSink Type
GUID-20230303-SS0I-CXJ3-2J27-WS97BGNS1T2B-low.svgSource Type

4 Pin Configuration and Functions

GUID-20230303-SS0I-BDVZ-7L47-4DSF01DLSLBD-low.svg Figure 4-1 ISO1228
Table 4-1 Pin Functions—38 Pins
PIN I/O DESCRIPTION
NO. NAME
1 IN1 I/O Field Input, Channel 1
2 LED1 I/O LED Indication Pin, Channel 1
3 IN2 I/O Field Input, Channel 2
4 LED2 I/O LED Indication Pin, Channel 2
5 IN3 I/O Field Input, Channel 3
6 LED3 I/O LED Indication Pin, Channel 3
7 AVSS — Field Side Negative Supply
8 IN4 I/O Field Input, Channel 4
9 LED4 I/O LED Indication Pin, Channel 4
10 IN5 I/O Field Input, Channel 5
11 LED5 I/O LED Indication Pin, Channel 5
12 IN6 I/O Field Input, Channel 6
13 LED6 I/O LED Indication Pin, Channel 6
14 IN7 I/O Field Input, Channel 7
15 LED7 I/O LED Indication Pin, Channel 7
16 AVCC — Field Side Power Supply
17 AVSS — Field Side Negative Supply
18 IN8 I/O Field Input, Channel 8
19 LED8 I/O LED Indication Pin, Channel 8
20 NC — Leave unconnected
21 GND1 — Logic Ground
22 NC — Leave unconnected
23 F1 I Digital Filter Setting
24 F0 I Digital Filter Setting
25 GND1 — Logic Ground
26 nFAULT O Open Drain Ouput. Connect 4.7 kΩ pull-up to VCC1
27 OUT_EN I Ouput Enable. Output pins OUT1 through OUT8 are tri-stated if OUT_EN=0 or FLOAT
28 OUT8/SYNC O Synchronize data in Burst Mode(COMM_SEL=VCC1)

Data Output, Channel 8, in Parallel Interface Mode (COMM_SEL=0)
29 OUT7/BURST_EN I/O Burst Mode in Serial Interface Mode (COMM_SEL=VCC1)

Data Output, Channel 7, in Parallel Interface Mode (COMM_SEL=0)
30 OUT6/nRST I/O Active Low SPI Reset in Serial Interface Mode (COMM_SEL=VCC1)

Data Output, Channel 6, in Parallel Interface Mode (COMM_SEL=0)
31 OUT5/nINT O Active Low SPI Interrupt in Serial Interface Mode (COMM_SEL=VCC1)

Data Output, Channel 5, in Parallel Interface Mode (COMM_SEL=0)
32 OUT4/nCS I/O SPI Chip Seltect in Serial Interface Mode (COMM_SEL=VCC1)

Data Output, Channel 4, in Parallel Interface Mode (COMM_SEL=0)
33 OUT3/SCLK I/O SPI Clock in Serial Interface Mode (COMM_SEL=VCC1)

Data Output, Channel 3, in Parallel Interface Mode (COMM_SEL=0)
34 OUT2/SDI I/O SPI Input Data in Serial Interface Mode (COMM_SEL=VCC1)

Data Output, Channel 2, in Parallel Interface Mode (COMM_SEL=0)
35 OUT1/SDO O SPI Output Data in Serial Interface Mode (COMM_SEL=VCC1)

Data Output, Channel 1, in Parallel Interface Mode (COMM_SEL=0)
36 GND1 — Logic Ground
37 VCC1 — Logic Supply
38 COMM_SEL I Serial vs. Parallel Interface selection

Serial Interface Mode if COMM_SEL=VCC1

Parallel Interface Mode if COMM_SEL=0 or Floating
  • I = Input, O = Output, I/O = Input/Output
  • Connect all AVSS pins on Field side together
  • Connect all GND1 pins on backplane/MCU side together

5 Specifications

5.1 Absolute Maximum Ratings

See(1)
MIN MAX UNIT
AVCC(2) AVCC to AVSS supply voltage -0.5 38.5 V
VCC1(2) VCC1 supply voltage to GND1 -0.5 6 V
VINx Voltage from INx pins to AVSS -0.5 38.5 V
VLEDx Voltage from LEDx pins to AVSS -0.5 38.5 V
VIO I/O voltage range on SDx, nCS, nINT, OUTx, OUT_EN, F0, F1, nFAULT, and COMM_SEL pins  –0.3 VCC1+0.5(3) V
IO Output current on SDO, nINT, OUTx, and nFAULT pins   -15 15 mA
TJ Operating junction temperature 150 °C
TSTG Storage temperature -65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the local ground terminal (AVSS or GND1) and are peak voltage values
(3) Maximum voltage must not exceed 6 V.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,		 All pins(1) ±1000 V
All INx, LEDx and AVCC to AVSS(1) ±6000 V
V(ESD) Electrostatic discharge
Charged device model (CDM), per JEDEC specification JESD22-C101		 All pins(2) ±1500
V(ESD_IEC) IEC ESD System Level Test Contact discharge per IEC 61000-4-2; Isolation barrier withstand test ±6000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

 
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