SNOSD74B
May 2019 – January 2020
LMG1025-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Typical (Simplified) System Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Input Stage
7.3.2
Output Stage
7.3.3
Bias Supply and Under Voltage Lockout
7.3.4
Overtemperature Protection (OTP)
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Handling Ground Bounce
8.2.2.2
Creating Nanosecond Pulse
8.2.3
VDD and Overshoot
8.2.4
Operating at Higher Frequency
8.2.5
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.1.1
Gate Drive Loop Inductance and Ground Connection
10.1.2
Bypass Capacitor
10.2
Layout Example
11
Device and Documentation Support
11.1
Receiving Notification of Documentation Updates
11.2
Support Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DEE|6
MPSS117
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snosd74b_oa
snosd74b_pm
1
Features
AEC-Q100 grade 1 qualified
1.25-ns typical minimum input pulse width
2.6-ns typical rising propagation delay
2.9-ns typical falling propagation delay
300-ps typical pulse distortion
Independent 7-A pull-up and 5-A pull-down current
650-ps typical rise time (220-pF load)
850-ps typical fall time (220-pF load)
2-mm x 2-mm QFN package
Inverting and non-inverting inputs
UVLO and over-temperature protection
Single 5-V supply voltage