SNOSDE2A October   2022  – December 2022 LMG2610

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 GaN Power FET Switching Parameters
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  GaN Power FET Switching Capability
      2. 8.3.2  Turn-On Slew-Rate Control
      3. 8.3.3  Current-Sense Emulation
      4. 8.3.4  Bootstrap Diode Function
      5. 8.3.5  Input Control Pins (EN, INL, INH)
      6. 8.3.6  INL - INH Interlock
      7. 8.3.7  AUX Supply Pin
        1. 8.3.7.1 AUX Power-On Reset
        2. 8.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 8.3.8  BST Supply Pin
        1. 8.3.8.1 BST Power-On Reset
        2. 8.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 8.3.9  Over-Current Protection
      10. 8.3.10 Over-Temperature Protection
      11. 8.3.11 Fault Reporting
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Turn-On Slew-Rate Design
        2. 9.2.2.2 Current-Sense Design
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Solder-Joint Stress Relief
        2. 9.4.1.2 Signal-Ground Connection
        3. 9.4.1.3 CS Pin Signal
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • RRG|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 650-V GaN power-FET half bridge
  • 170-mΩ low-side and 248-mΩ high-side GaN FETs
  • Integrated gate drivers with low propagation delays and adjustable turn-on slew-rate control
  • Current-sense emulation with high-bandwidth and high accuracy
  • Low-side / high-side gate-drive interlock
  • High-side gate-drive signal level shifter
  • Smart-switched bootstrap diode function
  • High-side start up : < 8 us
  • Low-side / high-side cycle-by-cycle over-current protection
  • Over-temperature protection with FLT pin reporting
  • AUX idle quiescent current: 240 μA
  • AUX standby quiescent current: 50 μA
  • BST idle quiescent current: 60 μA
  • Maximum supply and input logic pin voltage: 26 V
  • 9x7 mm QFN package with dual thermal pads