Data Sheet
LMG2640 Integrated 650V GaN Half Bridge
1 Features
- 650V GaN power-FET half bridge
- 105mΩ low-side and high-side GaN FETs
- Integrated gate drivers with low propagation delays
- Current-sense emulation with high-bandwidth and high accuracy
- Low-side / high-side gate-drive interlock
- High-side gate-drive signal level shifter
- Smart-switched bootstrap diode function
- High-side start up : < 8µs
- Low-side / high-side cycle-by-cycle over-current protection
- Over-temperature protection with FLT pin reporting
- AUX idle quiescent current: 250μA
- AUX standby quiescent current: 50μA
- BST idle quiescent current: 65μA
- Maximum supply and input logic pin voltage: 26V
- 9×7mm QFN package with dual thermal pads
2 Applications
- AC/DC adapters and chargers
- AC/DC USB wall outlet power supplies
- AC/DC auxiliary power supplies
- Mobile wall charger design
- USB wall power outlet
Simplified Block Diagram
3 Description
The LMG2640 is a 650V GaN power-FET half bridge intended for switch mode power supply applications. The LMG2640 simplifies design, reduces component count, and reduces board space by integrating half-bridge power FETs, gate drivers, bootstrap diode, and high-side gate-drive level shifter in a 9mm by 7mm QFN package.
The low-side current-sense emulation reduces power dissipation compared to the traditional current-sense resistor and allows the low-side thermal pad to be connected to the cooling PCB power ground.
The high-side gate-drive signal level shifter eliminates noise and burst-mode power dissipation problems found with external solutions. The smart-switched GaN bootstrap FET has no diode forward-voltage drop, avoids overcharging the high-side supply, and has zero reverse-recovery charge.
The LMG2640 supports converter light-load efficiency requirements and burst-mode operation with low quiescent currents and fast start-up times. Protection features include FET turn-on interlock, under-voltage lockout (UVLO), cycle-by-cycle current limit, and over-temperature shut down.
(1) For more information, see the Section 11 section.
(2) The package size (length × width) is a
nominal value and includes pins, where applicable.
Package
View4 Pin Configuration and Functions
Figure 4-1 RRG Package, 40-Pin VQFN (Top
View)
Table 4-1 Pin Functions
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| NC1 | 1, 13 | NC | Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to DH. |
| DH | 2–12 | P | High-side GaN FET drain. Internally connected to NC1. |
| SW | 14–16 | P | GaN FET half-bridge switch node between the high-side GaN FET source and low-side GaN FET drain. Internally connected to PADH. |
| NC2 | 17, 21, 37 | NC | Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to AGND, SL, and PADL. |
| SL | 18–20, 22–27 | P | Low-side GaN FET source. Internally connected to AGND, PADL, and NC2. |
| EN | 28 | I | Enable. Used to toggle between active and standby modes. The standby mode has reduced quiescent current to support converter light load efficiency targets. There is a forward biased ESD diode from EN to AUX so avoid driving EN higher than AUX. |
| INH | 29 | I | High-side gate-drive control input. Referenced to AGND. Signal is level shifted internally to the high-side GaN FET driver. There is a forward biased ESD diode from INH to AUX so avoid driving INH higher than AUX. |
| INL | 30 | I | Low-side gate-drive control input. Referenced to AGND. There is a forward biased ESD diode from INL to AUX so avoid driving INL higher than AUX. |
| AGND | 31 | GND | Low-side analog ground. Internally connected to SL, PADL, and NC2. |
| CS | 32 | O | Current-sense emulation output. Outputs 0.616 ma/A scaled replica of the low-side GaN FET current. Feed output current into a resistor to create a current sense voltage signal. Reference the resistor to the power supply controller IC local ground. This function replaces the external current-sense resistor that is used in series with the low-side FET. |
| NC3 | 33 | NC | Used to anchor QFN package to PCB. Pin must be soldered to a PCB landing pad. The PCB landing pad is non-solder mask defined pad and must not be physically connected to any other metal on the PCB. Pin not connected internally. |
| FLT | 34 | O | Active-low fault output. Open-drain output that asserts during an over-temperature shutdown. |
| AUX | 35 | P | Auxiliary voltage rail. Low-side supply voltage. Connect a local bypass capacitor between AUX and AGND. |
| RDRVL | 36 | I | Short to AGND. |
| BST | 38 | P | Bootstrap voltage rail. High-side supply voltage. The bootstrap diode function between AUX and BST is internally provided. Connect an appropriately sized bootstrap capacitor between BST and SW. Recommend to make the SW connection using NC4 as a pass through connection to PADH (PADH = SW) as explained in the NC4 description. |
| RDRVH | 39 | I | Short to SW.Recommend to make the SW connection using NC4 as a pass through connection to PADH (PADH = SW) as explained in the NC4 description. |
| NC4 | 40 | NC | Pin is not functional. Pin is high impedance and referenced to SW. Recommend to connect pin to PADH (PADH = SW) to use as convenient connection for the BST bypass capacitor and the RDRVH. See the example board layout in the Layout Example section. |
| PADH | 41 | TP | High-side thermal pad. Internally connected to SW. All the SW current can be conducted with PADH (PADH = SW). |
| PADL | 42 | TP | Low-side thermal pad. Internally connected to SL, AGND, and NC2. All the SL current can be conducted with PADL (PADL = SL). |
(1) I = Input, O = Output, G =
Ground, P = Power, NC = No Connect, TP = Thermal Pad.
5 Specifications
5.1 Absolute Maximum Ratings
Unless otherwise noted: voltages are respect to AGND(1)
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| VDS(ls) | Low-side drain-source (SW to SL) voltage, FET off | 650 | V | ||
| VDS(surge)(ls) | Low-side drain-source (SW to SL) voltage, surge condition, FET off (2) | 720 | V | ||
| VDS(tr)(surge)(ls) | Low-side drain-source (SW to SL) transient ringing peak voltage, surge condition, FET off (2) | 800 | V | ||
| VDS(hs) | High-side drain source (DH to SW) voltage, FET off | 650 | V | ||
| VDS(surge)(hs) | High-side drain-source (DH to SW) voltage, surge condition, FET off (2) | 720 | V | ||
| VDS(tr)(surge)(hs) | High-side drain-source (DH to SW) transient ringing peak voltage, surge condition, FET off (2) | 800 | V | ||
| Pin voltage | AUX | –0.3 | 30 | V | |
| EN, INL, INH, FLT | –0.3 | VAUX + 0.3 | V | ||
| CS | –0.3 | 5.5 | V | ||
| RDRVL | –0.3 | 4 | V | ||
| Pin voltage to SW | BST | –0.3 | 30 | V | |
| RDRVH | –0.3 | 4 | V | ||
| ID(cnts)(ls) | Low-side drain (SW to SL) continuous current, FET on | –10 | Internally limited | A | |
| IS(cnts)(ls) | Low-side source (SL to SW) continuous current, FET off | 10 | A | ||
| ID(cnts)(hs) | High-side drain (DH to SW) continuous current, FET on | –10 | Internally limited | A | |
| IS(cnts)(hs) | High-side source (SW to DH) continuous current, FET off | 10 | A | ||
| Positive sink current | CS | 10 | mA | ||
| FLT (while asserted) | Internally limited | mA | |||
| TJ | Operating junction temperature | –40 | 150 | °C | |
| Tstg | Storage temperature | –65 | 150 | °C | |
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) See Section 7.3.1 for more information on the GaN power FET switching capability.