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  • LMH1218 Low Power Ultra HD Cable Driver With Integrated Reclocker

    • SNLS474E February   2015  – June 2018 LMH1218

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • LMH1218 Low Power Ultra HD Cable Driver With Integrated Reclocker
  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified SPI Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD
    2.     Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface AC Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Loss of Signal Detector
      2. 7.3.2 Continuous Time Linear Equalizer (CTLE)
      3. 7.3.3 2:1 Multiplexer
      4. 7.3.4 Clock and Data Recovery
      5. 7.3.5 Eye Opening Monitor (EOM)
      6. 7.3.6 Fast EOM
        1. 7.3.6.1 SMBus Fast EOM Operation
        2. 7.3.6.2 SPI Fast EOM Operation
      7. 7.3.7 LMH1218 Device Configuration
        1. 7.3.7.1 MODE_SEL
        2. 7.3.7.2 ENABLE
        3. 7.3.7.3 LOS_INT_N
        4. 7.3.7.4 LOCK
        5. 7.3.7.5 SMBus MODE
        6. 7.3.7.6 SMBus READ/WRITE Transaction
        7. 7.3.7.7 SPI Mode
          1. 7.3.7.7.1 SPI READ/WRITE Transaction
          2. 7.3.7.7.2 SPI Write Transaction Format
          3. 7.3.7.7.3 SPI Read Transaction Format
        8. 7.3.7.8 SPI Daisy Chain
          1. 7.3.7.8.1 SPI Daisy Chain Write Example
          2. 7.3.7.8.2 SPI Daisy Chain Write Read Example
            1. 7.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration
      8. 7.3.8 Power-On Reset
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 Global Registers
      2. 7.6.2 Receiver Registers
      3. 7.6.3 CDR Registers
      4. 7.6.4 Transmitter Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for All Applications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
    4. 8.4 Initialization Set Up
      1. 8.4.1 Selective Data Rate Lock
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Solder Profile
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RTW|24
    • MPQF167C
Thermal pad, mechanical data (Package|Pins)
  • RTW|24
    • QFND450A
Orderable Information
  • snls474e_oa
  • snls474e_pm
search No matches found.
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    • Full reading width
    • Comfortable reading width
    • Expanded reading width
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DATA SHEET

LMH1218 Low Power Ultra HD Cable Driver With Integrated Reclocker

1 Features

  • Supports ST-2082 (Proposed), ST-2081 (Proposed), SMPTE 424M, 344M, 292M, 259M, DVB-ASI, SFF-8431 (SFP+) and 10GbE Ethernet for SMPTE 2022-5/6
  • Locks to Rates 11.88 Gbps, 5.94 Gbps, 2.97 Gbps, 1.485 Gbps, or Divided by 1.001 Sub-Rates, DVB-ASI (270 Mbps) and 10GbE (10.3125 Gbps)
  • Reference-Free Operation With Fast Lock Time Covering All Supported or Selected Data Rates
  • 75-Ω and 100-Ω Transmitter Outputs
  • Integrated 2:1 Mux Input, 1:2 Demux/Fanout Outputs
  • Automatic Slew Rate Based on Input Rate Detect
  • On-Chip Eye Monitor
  • Low 300-mW Power Consumption With Automatic Power Down on Loss of Input Signal
  • Programmable Through SPI or SMBus Interface
  • Single 2.5-V Supply Operation
  • Small 4-mm × 4-mm 24-Pin WQFN Package
  • –40°C to +85°C Operating Temperature Range

2 Applications

  • UHDTV/4K/8K/HDTV/SDTV Video
  • Digital Video Routers and Switches
  • Digital Video Processing and Editing
  • DVB-ASI and Distribution Amplifiers
  • 10GbE for SMPTE 2022-5/6

3 Description

The LMH1218 device is a low-power cable driver with integrated reclocker to drive serial video data compatible to SMPTE-SDI, SMPTE 2022-5/6, 10GbE Ethernet, and DVB-ASI standards. The LMH1218 supports up to 11.88 Gbps to enable Ultra High Definition Video for 4K/8K applications. With 75-Ω and 50-Ω transmitter outputs, the LMH1218 enables multiple media options such as coax, fiber, and FR-4 PCB.

The integrated 2-to-1 MUX on the input of the LMH1218 enables selection between two video sources, while the programmable equalizer compensates for the printed-circuit board loss to extend signal reach. With a wide range clock-and-data recovery (CDR) circuit, the on-chip reclocker automatically detects and locks to serial data from 270 Mbps to 11.88 Gbps without the need for an external reference clock and loop filter component, thereby simplifying board design and lowering system cost. The reclocked serial data can be routed to either the 75-Ω or 50-Ω transmitter output, or both simultaneously (1-to-2 fanout mode). The output voltage swing is compatible to SFF-8431 (SFP+), ST-2082/1 (Proposed), SMPTE 424M, 344M, 292M, and 259M standards.

A non-disruptive eye monitor allows for real-time measurement of serial data to simplify system start-up or field tuning. The LMH1218 can be programmed using SPI or SMBus Interface.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LMH1218 WQFN (24) 4.00 mm × 4.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Device Images

Simplified SPI Schematic

LMH1218 simplified_spi_schem_no_pin_snls474.gif

4 Revision History

Changes from D Revision (December 2017) to E Revision

  • Changed the note under Float(Default) setting from: Reserved to: Power down until valid signal detectedGo
  • Changed MISO pin I/O description from 3-Level back to 2-LevelGo
  • Changed the Acknowledge (ACK) graphic text from: Clock Line Held Low by Receiver While Interrupt is Serviced to: Host may held clock line low to delay transactionGo
  • Changed Channel Register 0x80 default from: 0xXX to: 0x20 Go
  • Changed the OUT0_VOD bit 7 default from x to 0Go
  • Changed the bit description for the OUT0_VOD bits 7-3 from: drv_0_sel_vod[3:0] default value may change from part to part to: drv_0_sel_vod[3:0] is typically 42 mV per step.Go
  • Changed the OUT0_VOD bit 6 default from x to 0Go
  • Changed the OUT0_VOD bit 5 default from x to 1Go
  • Changed the OUT0_VOD bit 4 default from x to 0Go

Changes from C Revision (December 2016) to D Revision

  • Changed Channel Register 0x80 default value from 0101 0100’b to XXXX 0000’bGo

Changes from B Revision (February 2016) to C Revision

  • Changed MISO pin I/O description from 2-Level to 3-LevelGo
  • Added test conditions to the source transmit differential launch amplitude parametersGo
  • Changed OUT0 VOD_Scaling_PD description for bits 7 through 4Go

Changes from A Revision (March 2015) to B Revision

  • Changed ESD Ratings for Human-body model (HBM) From: ±2500 To ±4500 Go
  • Added typical launch amplitude for 20 and 30 inch FR4 trace in the Recommended Operating ConditionsGo
  • Added new Note to the Electrical Characteristics: "ATE Production tested using DC method.."Go
  • Changed the VVOD_OUT0 row information and values in the Electrical CharacteristicsGo
  • Added MAX value of 45 ps to TR_F_OUT0 in the Electrical CharacteristicsGo
  • Changed the TYP value From: 900 To: 950 ps, Added MIN and MAX values to TR_F_OUT0 (270 Mbps) in the Electrical CharacteristicsGo
  • Changed the TYP value to 3 ps, Added MAX value of 18 ps to TR_F_OUT0_delta in the Electrical CharacteristicsGo
  • Changed the TYP value From: 100 To: 72 ps, Added MAX value of 500 ps to TR_F_OUT0_delta (270 Mbps) in the Electrical CharacteristicsGo
  • Changed the VOVR_UDR_SHOOT row information and values in the Electrical CharacteristicsGo
  • Added tSU MIN = 4 ns in the Serial Parallel Interface (SPI) Bus Interface AC Timing SpecificationsGo
  • Added tH MIN = 4 ns in the Serial Parallel Interface (SPI) Bus Interface AC Timing SpecificationsGo
  • Added tSSSu MIN = 14 ns, Changed TYP value From: 14 To: 18 ns in the Serial Parallel Interface (SPI) Bus Interface AC Timing SpecificationsGo
  • Added tSSh MIN = 4 ns in the Serial Parallel Interface (SPI) Bus Interface AC Timing SpecificationsGo
  • Added Selective Data Rate Lock in Application and Implementation section. Go

Changes from * Revision (February 2015) to A Revision

  • Changed document status from Product Preview to Production Data Go

5 Pin Configuration and Functions

RTW Package
24-Pin WQFN
(Top View)
LMH1218 pin_configuration_2_16.gif

Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD

PIN TYPE DESCRIPTION
NAME NO.
CONTROL/INDICATOR I/O
ENABLE 6 Input, 4-Level Powers down device when pulled low
1 kΩ to VDD:
  • Power down until valid signal detected

Float(Default):
  • Power down until valid signal detected

20 kΩ to GND:
  • Reserved

1 kΩ to GND:
  • Power down including signal detects and Reset Registers upon power-up
LOCK 16 Output, 2.5-V LVCMOS, 2-Level Indicates CDR lock detect status
High:
  • CDR locked

Low:
  • CDR not locked
LOS_INT_N 13 Output,
LVCMOS Open-Drain, 2-Level		 Programmable Interrupt caused by change in LOS, violation of internal eye monitor threshold, or change in lock. External 4.7-kΩ pullup resistor is required. This pin is 3.3-V LVCMOS tolerant.
MISO 15 Output, 2.5-V LVCMOS, 2-Level SPI Master Input / Slave Output. LMH1218 SPI data transmit
MODE_SEL 1 Input, 4-Level Determines Device Configuration: SPI or SMBus
1 kΩ to VDD:
  • SPI mode. See Initialization Set Up.
MOSI 4 Input, 2-Level SPI Master Output / Slave Input. LMH1218 SPI data receive
RESERVED 5, 17, 18 — No Connect
SCK 3 Input, 2.5V LVCMOS, 2-Level SPI serial clock input
SMPTE_10GbE 14 — No Connect
SS_N 2 Input, 2-Level SPI Slave Select. This pin has internal pullup
HIGH-SPEED DIFFERENTIAL I/O
IN0+ 11 Input, Analog Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN0+ to IN0-. Inputs require 4.7-µF, AC-coupling capacitors.
IN0– 12 Input, Analog
IN1+ 8 Input, Analog Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN1+ to IN1-. Inputs require 4.7-µF, AC-coupling capacitors.
IN1– 9 Input, Analog
OUT0+ 20 Output, 75-Ω CML Compatible Inverting and noninverting 75-Ω outputs. An on-chip 75-Ω terminating resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7-µF, AC-coupling capacitors
OUT0– 19 Output, 75-Ω CML Compatible
OUT1+ 23 Output, Analog Inverting and noninverting differential outputs. An on-chip 100-Ω terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7-µF, AC-coupling capacitors
OUT1– 22 Output, Analog
POWER
DAP — Ground Exposed DAP, connect to GND using at least 5 vias (see package drawing)
VDD 7, 21 2.5-V Supply 2.5 V ± 5%
VSS 10, 24 Ground Ground

Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND

PIN TYPE DESCRIPTION
NAME NO.
ADDR0 2 Input, 4-Level 4-level strap pins used to set the SMBus address of the device. The pin state is read on power-up. The multi-level nature of these pins allows for 16 unique device addresses. Note the SMBus section for further details. The four strap options include:
1 kΩ to VDD:
  • Represents logic state 11’b

Float(Default): Represents logic state 10'b 7-bits SMBus address = 0x17
20 kΩ to GND:
  • Represents logic state 01'b

1 kΩ to GND:
  • Represents logic state 00'b
ADDR1 15
ENABLE 6 Input, 4-Level Powers down device when pulled low
1 kΩ to VDD:
  • Power down until valid signal detected

Float(Default): Reserved
20 kΩ to GND:
  • Reserved

1 kΩ to GND:
  • Power down including signal detects and Reset Registers upon power-up
LOCK 16 Output, 2.5-V LVCMOS, 2-Level Indicates CDR lock Status
High:
  • CDR locked

Low:
  • CDR not locked
LOS_INT_N 13 Output, LVCMOS
Open-Drain, 2-Level 		Programmable Interrupt caused by change in LOS, violation of internal eye monitor threshold, change in lock. External 4.7-kΩ pullup resistor is required. This pin is 3.3-V LVCMOS tolerant.
MODE_SEL 1 Input, 4-Level Determines Device Configuration: SPI or SMBus
1 kΩ to GND: SMBUS mode. See Initialization Set Up
RESERVED 5, 17, 18 — No Connect
SCL 3 Input, 2-Level SMBus clock input / open-drain. External 2-kΩ to 5-kΩ pullup resistor is required as per SMBus interface standard. This pin is 3.3-V LVCMOS tolerant.
SDA 4 I/O, Open-Drain, 2-Level SMBus data input / open-drain. External 2-kΩ to 5-kΩ pullup resistor is required as per SMBus interface standard. This pin is 3.3-V LVCMOS tolerant.
SMPTE_10GbE 14 No Connect
HIGH-SPEED DIFFERENTIAL I/O
DAP — Ground Exposed DAP, connect to GND using at least 5 vias (see package drawing)
IN0+ 11 Input, Analog Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN0+ to IN0–. Inputs require 4.7-µF, AC-coupling capacitors.
IN0– 12 Input, Analog
IN1+ 8 Input, Analog Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN0+ to IN0–. Inputs require 4.7-µF, AC-coupling capacitors.
IN1– 9 Input, Analog
OUT0+ 20 Output, 75-Ω CML Compatible Inverting and noninverting 75-Ω outputs. An on-chip 75-Ω terminating resistor connects OUT0+ and OUT0– to VDD. Outputs require 4.7-µF, AC-coupling capacitors
OUT0– 19 Output, 75-Ω CML Compatible
OUT1+ 23 Output, Analog Inverting and noninverting differential outputs. An on-chip 100 Ω terminating resistor connects OUT1+ to OUT1–. Outputs require 4.7-µF, AC-coupling capacitors
OUT1– 22 Output, Analog
VDD 7, 21 2.5-V Supply 2.5 V ± 5%
VSS 10, 24 Ground Ground

 
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