LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs

1 Features

Maximum Clock Output Frequency: 3255 MHz
Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
Ultra-Low Noise, at 2500 MHz:
- 54 fs RMS Jitter (12 kHz to 20 MHz)
- 64 fs RMS Jitter (100 Hz to 20 MHz)
- –157.6 dBc/Hz Noise Floor
Ultra-Low Noise, at 3200 MHz:
- 61 fs RMS Jitter (12 kHz to 20 MHz)
- 67 fs RMS Jitter (100 Hz to 100 MHz)
- –156.5 dBc/Hz Noise Floor
PLL2
- PLL FOM of –230 dBc/Hz
- PLL 1/f of –128 dBc/Hz
- Phase Detector Rate up to 320 MHz
- Two Integrated VCOs: 2440 to 2580 MHz
  and 2945 to 3255 MHz
Up to 14 Differential Device Clocks
- CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS Programmable Outputs
Up to 1 Buffered VCXO/XO Output
- LVPECL, LVDS, 2xLVCMOS Programmable
1-1023 CLKout Divider
1-8191 SYSREF Divider
25-ps Step Analog Delay for SYSREF Clocks
Digital Delay and Dynamic Digital Delay for Device Clock and SYSREF
Holdover Mode With PLL1
0-Delay with PLL1 or PLL2
Supports 105°C PCB Temperature
(Measured at Thermal Pad)