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LMX243x PLLatinum Dual High-Frequency Synthesizer for RF Personal Communications
SNAS187D
February 2003 – January 2016
LMX2430
,
LMX2433
,
LMX2434
PRODUCTION DATA.
CONTENTS
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LMX243x PLLatinum Dual High-Frequency Synthesizer for RF Personal Communications
1
Features
2
Applications
3
Description
4
Revision History
5
Description continued
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
Recommended Operating Conditions
7.3
Thermal Information
7.4
Electrical Characteristics
7.5
Timing Requirements
7.6
Typical Characteristics
7.6.1
Sensitivity
7.6.2
Charge Pump
7.6.3
Input Impedance
8
Parameter Measurement Information
8.1
Bench Test Setups
8.1.1
LMX243x Charge-Pump Test Setup
8.1.2
Charge-Pump Current Specification Definitions
8.1.2.1
Charge-Pump Output Current Variation vs Charge-Pump Output Voltage
8.1.2.2
Charge-Pump Sink Current vs Charge-Pump Output Source Current Mismatch
8.1.2.3
Charge-Pump Output Current Variation vs Temperature
8.1.3
LMX243x FinRF Sensitivity Test Setup
8.1.4
LMX243x OSCin Sensitivity Test Setup
8.1.5
LMX243x FinRF Input Impedance Test Setup
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Reference Oscillator Input
9.3.2
Reference Dividers (R Counters)
9.3.3
Prescalers
9.3.4
Programmable Feedback Dividers (N Counters)
9.3.5
Phase / Frequency Detectors
9.3.5.1
Phase Comparator and Internal Charge-Pump Characteristics
9.3.6
Charge Pumps
9.3.7
Microwire Serial Interface
9.3.8
Multi-Function Outputs
9.3.8.1
Push-Pull Analog Lock-Detect Output
9.3.8.2
Open-Drain Analog Lock-Detect Output
9.3.8.3
Digital Filtered Lock-Detect Output
9.3.8.4
Reference Divider and Feedback Divider Output
9.3.9
Fastlock Output
9.3.10
Counter Reset
9.4
Device Functional Modes
9.4.1
Power Control
9.4.1.1
Synchronous Power-Down Mode
9.4.1.2
Asynchronous Power-Down Mode
9.5
Programming
9.5.1
Microwire Interface
9.5.2
Control Register Location
9.6
Register Maps
9.6.1
Control Register Content Map
9.6.2
R0 Register
9.6.2.1
RF_R[14:0] - RF Synthesizer Programmable Reference Divider (R Counter) (R0[17:3])
9.6.2.2
RF_CPP - RF Synthesizer Phase Detector Polarity (R0[18])
9.6.2.3
RF_CPG - RF Synthesizer Charge-Pump Current Gain (R0[19])
9.6.2.4
RF_CPT - RF Synthesizer Charge-Pump Tri-State (R0[20])
9.6.2.5
RF_RST - RF Synthesizer Counter Reset (R0[21])
9.6.3
R1 Register
9.6.3.1
LMX243x RF Synthesizer Swallow Counter
9.6.3.1.1
RF_A[3:0] - LMX2430/33 RF Synthesizer Swallow Counter (A Counter) (R1[6:3])
9.6.3.1.2
RF_A[4:0] - LMX2434 RF Synthesizer Swallow Counter (A Counter) (R1[7:3])
9.6.3.2
LMX243x RF Synthesizer Programmable Binary Counter
9.6.3.2.1
RF_B[14:0] - LMX2430/33 RF Synthesizer Programmable Binary Counter (B Counter) (R1[21:7])
9.6.3.2.2
RF_B[13:0] - LMX2434 RF Synthesizer Programmable Binary Counter (B Counter) (R1[21:8])
9.6.3.3
LMX243x RF Synthesizer Prescaler Select
9.6.3.3.1
RF_P - LMX2430/33 RF Synthesizer Prescaler Select (R1[22])
9.6.3.3.2
RF_P - LMX2434 RF Synthesizer Prescaler Select (R1[22])
9.6.3.4
RF_PD - RF Synthesizer Power Down (R1[23])
9.6.4
R2 Register
9.6.4.1
RF_TOC[0:11] - RF Synthesizer Time-Out Counter (R2[14:3])
9.6.4.2
R3 Register
9.6.4.2.1
IF_R[14:0] - IF Synthesizer Programmable Reference Divider (R Counter) (R3[17:3])
9.6.4.2.2
IF_CPP - IF Synthesizer Phase Detector Polarity (R3[18])
9.6.4.2.3
IF_CPG - IF Synthesizer Charge-Pump Current Gain (R3[19])
9.6.4.2.4
IF_CPT - IF Synthesizer Charge-Pump Tri-State (R3[20])
9.6.4.2.5
IF_RST - IF Synthesizer Counter Reset (R3[21])
9.6.5
R4 Register
9.6.5.1
IF_A[3:0] - IF Synthesizer Swallow Counter (A Counter) (R4[6:3])
9.6.5.2
IF_B[13:0] - IF Synthesizer Programmable Binary Counter (B Counter) (R4[20:7])
9.6.5.2.1
IF_P - IF Synthesizer Prescaler Select (R4[22])
9.6.5.3
IF_PD - IF Synthesizer Power Down (R4[23])
9.6.6
R5 Register
9.6.6.1
IF_TOC[0:11] - IF Synthesizer Time-Out Counter (R5[14:3])
9.6.7
MUX[3:0] - Multifunction Output Select (R3[23:22]:R0[23:22])
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Device Support
13.1.1
Device Nomenclature
13.1.1.1
List of Definitions
13.2
Related Links
13.3
Community Resources
13.4
Trademarks
13.5
Electrostatic Discharge Caution
13.6
Glossary
14
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
NPE|20
MPLG058
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snas187d_oa
snas187d_pm
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