MSP430F677x, MSP430F676x, MSP430F674x Polyphase Metering SoCs
- SLAS768E September 2012 – September 2018 MSP430F6745 , MSP430F6746 , MSP430F6747 , MSP430F6748 , MSP430F6749 , MSP430F6765 , MSP430F6766 , MSP430F6767 , MSP430F6768 , MSP430F6769 , MSP430F6775 , MSP430F6776 , MSP430F6777 , MSP430F6778 , MSP430F6779
  
  PRODUCTION DATA.

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DATA SHEET

MSP430F677x, MSP430F676x, MSP430F674x Polyphase Metering SoCs

1 Device Overview

1.1 Features

Accuracy < 0.1% Over 2000:1 Dynamic Range for Phase Current
Meets or Exceeds ANSI C12.20 and IEC 62053 Standards
Support for Multiple Sensors Such as Current Transformers, Rogowski Coils, or Shunts
Power Measurement for up to Three Phases Plus Neutral
Dedicated Pulse Output Pins for Active and Reactive Energy for Calibration
Four-Quadrant Measurement per Phase or Cumulative
Exact Phase Angle Measurements
Digital Phase Correction for Current Transformers
Temperature Compensated Energy Measurements
40-Hz to 70-Hz Line Frequency Range Using Single Calibration
Flexible Power Supply Options With Automatic Switching
Display Operates at Very Low Power During AC Mains Failure: 3 µA in LPM3
LCD Driver With Contrast Control for up to 320 Segments
Password-Protected Real-Time Clock (RTC) With Crystal Offset Calibration and Temperature Compensation
Integrated Security Modules to Support Anti-Tamper and Encryption
Multiple Communication Interfaces for Smart Meter Implementations
High-Performance 25-MHz CPU With 32-Bit Multiplier
Wide Input Supply Voltage Range:
3.6 V Down to 1.8 V
Ultra-Low Power Consumption During Energy Measurement
- 2.9 mW at 10-MHz Operation (3 V)
Multiple Low-Power Modes
- Standby Mode (LPM3): 2.1 µA at 3 V,
  Wake up in Less Than 5 µs
- RTC Mode (LPM3.5): 0.34 µA at 3 V
- Shutdown Mode (LPM4.5): 0.18 µA at 3 V
Up to 512KB of Single-Cycle Flash
Up to 32KB of RAM With Single-Cycle Access
Up to Seven Independent 24-Bit Sigma-Delta ADCs With Differential Inputs and Variable Gain
System 10-Bit 200-ksps ADC
- Six Channels Plus Supply and Temperature Sensor Measurement
Integrated Hardware AES-128 Module for Encryption
Six Enhanced Communications Ports
- Configurable Among Four UART, Six SPI, and Two I²C Interfaces
Four 16-Bit Timers With Nine Total Capture/Compare Registers
128-Pin LQFP (PEU) Package With 90 I/O Pins
100-Pin LQFP (PZ) Package With 62 I/O Pins
Industrial Temperature Range of –40°C to 85°C
3-Phase Electronic Watt-Hour Meter Development Tool (Also See Tools and Software)
- EVM430-F6779 With Application Note
- Energy Measurement Design Center for MSP430™ MCUs

1.2 Applications

3-Phase Electronic Watt-Hour Meters
Utility Metering
Energy Monitoring

1.3 Description

The TI MSP430F677x family of polyphase metering SoCs are powerful highly integrated solutions for revenue meters that offer accuracy and low system cost with few external components. The F677x family of devices uses the low-power MSP430 CPU with a 32-bit multiplier to perform all energy calculations, metering applications such as tariff rate management, and communications with AMR and AMI modules.

The F677x devices feature TI's 24-bit sigma-delta converter technology, which provides better than 0.1% accuracy. Family members include up to 512KB of flash, 32KB of RAM, and an LCD controller with support for up to 320 segments.

The ultra-low-power nature of the F677x devices means that the system power supply can be minimized to reduce overall cost. Lowest standby power means that backup energy storage can be minimized and critical data retained longer in case of a mains power failure.

The F677x family of devices executes the TI energy measurement software library, which calculates all relevant energy and power results. The energy measurement software library is available with the F677x devices at no cost. Industry standard development tools and hardware platforms are available to speed development of meters that meet all of the ANSI and IEC standards globally.

For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE⁽²⁾
MSP430F6779IPEU	LQFP (128)	20 mm × 14 mm
MSP430F6779IPZ	LQFP (100)	14 mm × 14 mm

(1) For the most current device, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8.

1.4 Application Diagram

Figure 1-1 shows a typical application diagram.

MSP430F6779 MSP430F6778 MSP430F6777 MSP430F6776 MSP430F6775 MSP430F6769 MSP430F6768 MSP430F6767 MSP430F6766 MSP430F6765 MSP430F6749 MSP430F6748 MSP430F6747 MSP430F6746 MSP430F6745 App_Circuit.gif

Figure 1-1 3-Phase 4-Wire Star Connection Using MSP430F677x

2 Revision History

Changes from December 19, 2013 to September 28, 2018

Document format changes throughout, including addition of section numbering Go
Added Device Information tableGo
Added Section 3, Device Comparison, and moved Table 3-1 to itGo
Added Section 3.1, Related ProductsGo
Added Section 4 and moved pinouts and terminal functions tables to itGo
Corrected the port number (P4.2) on pin 61 in Figure 4-2, 100-Pin PZ Package (Top View)Go
Added note to P1.3/ADC10CLK/A3 (pin 8) in Table 4-3, Terminal Functions – PEU PackageGo
Added typical conditions statements at the beginning of Section 5, SpecificationsGo
Moved all electrical specifications to Section 5Go
Added SD24_B input pins and AUXVCCx pins to exception list on "Voltage applied to pins" parameter, and added SD24_B input pin limits in "Diode current at pins" parameter in Section 5.1, Absolute Maximum RatingsGo
Added Section 5.2, ESD RatingsGo
Added note to C_VCOREGo
Added Section 5.7, Thermal Packaging CharacteristicsGo
Changed the TYP value of the C_L,eff parameter with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF in Section 5.16, Crystal Oscillator, XT1, Low-Frequency ModeGo
Updated notes (1) and (2) and added note (3) in Section 5.26, Wake-up Times From Low-Power Modes and ResetGo
Corrected the names of the AUXVCC1, AUXVCC2, and AUXVCC3 pins in Auxiliary Supplies tablesGo
Corrected the bit name in the Test Conditions of the R_CHARGE parameter (changed CHCx to AUXCHCx) in Section 5.34, Auxiliary Supplies, Charge Limiting ResistorGo
Replaced f_Frame parameter with f_LCD, f_FRAME,4mux, and f_FRAME,8mux parameters in Section 5.46, LCD_C Recommended Operating ConditionsGo
On the V_ID,FS parameter in Section 5.48, SD24_B Power Supply and Recommended Operating Conditions: Changed the MIN value from "V_REF/GAIN" to "–V_REF/GAIN"; Removed "Unipolar mode" test condition (mode is not supported)Go
Removed ADC10DIV from the formula for the TYP value in the second row of the t_CONVERT parameter in Section 5.57, 10-Bit ADC Switching Characteristics, because ADC10CLK is after divisionGo
Changed Test Conditions for all parameters in Section 5.58, 10-Bit ADC Linearity Parameters: Removed "V_REF–"; Changed from "(V_eREF+ – V_eREF–)min ≤ (V_eREF+ – V_eREF–)" to "1.4 V ≤ (V_eREF+ – V_eREF–)"; Changed from "C_VREF+ = 20 pF" to "C_VeREF+ = 20 pF"; Added "C_VeREF+ = 20 pF" to E_I; Added "ADC10SREFx = 11b" to E_T and E_GGo
Removed "V_REF–" from the Test Conditions for the V_eREF+, V_eREF–, and (V_eREF+ – V_eREF–) parameters in Section 5.59, 10-Bit ADC External ReferenceGo
Changed MIN value of AV_CC(min) parameter with Test Conditions of "REFVSEL = {0} for 1.5 V" from 2.2 V to 1.8 V in Section 5.60, REF Built-In ReferenceGo
Changed the MAX value of the t_{EN_CMP} parameter with Test Conditions of "CBPWRMD = 10" from 50 µs to 100 µs in Section 5.61, Comparator_BGo
Throughout document, changed all instances of "bootstrap loader" to "bootloader"Go
Corrected spelling of NMIIFG in Table 6-13, System Module Interrupt Vector RegistersGo
Added Section 7 and moved Development Tools Support, Device and Development Tool Nomenclature, and Trademarks sections to itGo
Replaced former section Development Tools Support with Section 7.3, Tools and SoftwareGo
Added Section 8, Mechanical, Packaging, and Orderable InformationGo

3 Device Comparison

Table 3-1 summarizes the available family members.

Table 3-1 Device Comparison⁽¹⁾⁽²⁾

DEVICE	FLASH (KB)	SRAM (KB)	SD24_B CONVERTERS	ADC10_A CHANNELS	Timer_A⁽³⁾	eUSCI_A: UART, IrDA, SPI	eUSCI_B: SPI, I²C	I/Os	PACKAGE
MSP430F6779IPEU	512	32	7	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6778IPEU	512	16	7	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6777IPEU	256	32	7	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6776IPEU	256	16	7	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6775IPEU	128	16	7	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6769IPEU	512	32	6	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6768IPEU	512	16	6	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6767IPEU	256	32	6	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6766IPEU	256	16	6	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6765IPEU	128	16	6	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6749IPEU	512	32	4	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6748IPEU	512	16	4	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6747IPEU	256	32	4	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6746IPEU	256	16	4	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6745IPEU	128	16	4	6 ext, 2 int	3, 2, 2, 2	4	2	90	128 PEU
MSP430F6779IPZ	512	32	7	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ
MSP430F6778IPZ	512	16	7	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ
MSP430F6777IPZ	256	32	7	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ
MSP430F6776IPZ	256	16	7	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ
MSP430F6775IPZ	128	16	7	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ
MSP430F6769IPZ	512	32	6	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ
MSP430F6768IPZ	512	16	6	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ
MSP430F6767IPZ	256	32	6	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ
MSP430F6766IPZ	256	16	6	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ
MSP430F6765IPZ	128	16	6	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ
MSP430F6749IPZ	512	32	4	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ
MSP430F6748IPZ	512	16	4	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ
MSP430F6747IPZ	256	32	4	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ
MSP430F6746IPZ	256	16	4	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ
MSP430F6745IPZ	128	16	4	6 ext, 2 int	3, 2, 2, 2	4	2	62	100 PZ

(1) For the most current device, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

Products for TI Microcontrollers

TI's low-power and high-performance MCUs, with wired and wireless connectivity options, are optimized for a broad range of applications.

Products for MSP430 Ultra-Low-Power Microcontrollers

One platform. One ecosystem. Endless possibilities. Enabling the connected world with innovations in ultra-low-power microcontrollers with advanced peripherals for precise sensing and measurement.

Companion Products for MSP430F6779

Review products that are frequently purchased or used with this product.

Reference Designs for MSP430F6779

The TI Designs Reference Design Library is a robust reference design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pinout for the MSP430F677x devices in the 128-pin PEU package. Table 4-1 lists the differences among the pinouts for the MSP430F677x, MSP430F676x, and MSP430F674x devices.

A. The secondary digital functions on Ports P2, P3 and P4 are fully mappable. This pinout shows only the default mapping. See Table 6-11 for details.

B. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on the board for proper device operation.

C. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used.

Figure 4-1 128-Pin PEU Package (Top View)

Table 4-1 Pinout Differences for MSP430F677xIPEU , MSP430F676xIPEU , and MSP430F674xIPEU

PIN NUMBER	PIN NAME
PIN NUMBER	MSP430F677xIPEU	MSP430F676xIPEU	MSP430F674xIPEU
46	P6.1/SD4DIO/S39	P6.1/SD4DIO/S39	P6.1/S39
47	P6.2/SD5DIO/S38	P6.2/SD5DIO/S38	P6.2/S38
48	P6.3/SD6DIO/S37	P6.3/S37	P6.3/S37
113	VREF	VREF	VREF
114	SD4P0	SD4P0	NC
115	SD4N0	SD4N0	NC
116	SD5P0	SD5P0	NC
117	SD5N0	SD5NO	NC
118	SD6P0	NC	NC
119	SD6N0	NC	NC

Figure 4-2 shows the pinout for the MSP430F677x devices in the 100-pin PZ package. Table 4-2 lists the differences among the pinouts for the MSP430F677x, MSP430F676x, and MSP430F674x devices.

A. The secondary digital functions on Ports P2, P3 and P4 are fully mappable. This pinout shows only the default mapping. See Table 6-11 for details.

B. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on the board for proper device operation.

C. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used.

Figure 4-2 100-Pin PZ Package (Top View)

Table 4-2 Pinout Differences for MSP430F677xIPZ , MSP430F676xIPZ , and MSP430F674xIPZ

PIN NUMBER	PIN NAME
PIN NUMBER	MSP430F677xIPZ	MSP430F676xIPZ	MSP430F674xIPZ
11	VREF	VREF	VREF
12	SD4P0	SD4P0	NC
13	SD4N0	SD4N0	NC
14	SD5P0	SD5P0	NC
15	SD5N0	SD5NO	NC
16	SD6P0	NC	NC
17	SD6N0	NC	NC
72	P5.5/SD4DIO/S19	P5.5/SD4DIO/S19	P5.5/S19
73	P5.6/SD5DIO/S18	P5.6/SD5DIO/S18	P5.6/S18
74	P5.7/SD6DIO/S17	P5.7/S17	P5.7/S17

4.2 Signal Descriptions

Table 4-3 describes the signals for devices in the PEU package. See Table 4-4 for the PZ package signal descriptions.

Table 4-3 Terminal Functions – PEU Package

TERMINAL		I/O⁽¹⁾	DESCRIPTION
NAME	NO.
NAME	PEU
XIN	1	I/O	Input terminal for crystal oscillator
XOUT	2	I/O	Output terminal for crystal oscillator
AUXVCC3	3		Auxiliary power supply AUXVCC3 for back up subsystem
RTCCAP1	4	I	External time capture pin 1 for RTC_C
RTCCAP0	5	I	External time capture pin 0 for RTC_C
P1.5/SMCLK/CB0/A5	6	I/O	General-purpose digital I/O with port interrupt
			SMCLK clock output
			Comparator_B input CB0
			Analog input A5 for 10-bit ADC
P1.4/MCLK/CB1/A4	7	I/O	General-purpose digital I/O with port interrupt
			MCLK clock output
			Comparator_B input CB1
			Analog input A4 for 10-bit ADC
P1.3/ADC10CLK/A3⁽³⁾	8	I/O	General-purpose digital I/O with port interrupt
			ADC10_A clock output
			Analog input A3 for 10-bit ADC
P1.2/ACLK/A2	9	I/O	General-purpose digital I/O with port interrupt
			ACLK clock output
			Analog input A2 for 10-bit ADC
P1.1/TA2.1/VeREF+/A1	10	I/O	General-purpose digital I/O with port interrupt
			Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output
			Positive terminal for the ADC reference voltage for an external applied reference voltage
			Analog input A1 for 10-bit ADC
P1.0/TA1.1/VeREF-/A0	11	I/O	General-purpose digital I/O with port interrupt
			Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output
			Negative terminal for the ADC reference voltage for an external applied reference voltage
			Analog input A0 for 10-bit ADC
P2.4/PM_TA2.0	12	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
P2.5/PM_UCB0SOMI/ PM_UCB0SCL	13	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_B0 SPI slave out master in Default mapping: eUSCI_B0 I²C clock
P2.6/PM_UCB0SIMO/ PM_UCB0SDA	14	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_B0 SPI slave in master out Default mapping: eUSCI_B0 I²C data
P2.7/PM_UCB0CLK	15	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_B0 clock input/output
P3.0/PM_UCA0RXD/ PM_UCA0SOMI	16	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A0 UART receive data Default mapping: eUSCI_A0 SPI slave out master in
P3.1/PM_UCA0TXD/ PM_UCA0SIMO	17	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A0 UART transmit data Default mapping: eUSCI_A0 SPI slave in master out
P3.2/PM_UCA0CLK	18	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A0 clock input/output
P3.3/PM_UCA1CLK	19	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A1 clock input/output
P3.4/PM_UCA1RXD/ PM_UCA1SOMI	20	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A1 UART receive data Default mapping: eUSCI_A1 SPI slave out master in
P3.5/PM_UCA1TXD/ PM_UCA1SIMO	21	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A1 UART transmit data Default mapping: eUSCI_A1 SPI slave in master out
COM0	22	O	LCD common output COM0 for LCD backplane
COM1	23	O	LCD common output COM1 for LCD backplane
P1.6/COM2	24	I/O	General-purpose digital I/O with port interrupt LCD common output COM2 for LCD backplane
P1.7/COM3	25	I/O	General-purpose digital I/O with port interrupt LCD common output COM3 for LCD backplane
P5.0/COM4	26	I/O	General-purpose digital I/O LCD common output COM4 for LCD backplane
P5.1/COM5	27	I/O	General-purpose digital I/O LCD common output COM5 for LCD backplane
P5.2/COM6	28	I/O	General-purpose digital I/O LCD common output COM6 for LCD backplane
P5.3/COM7	29	I/O	General-purpose digital I/O LCD common output COM7 for LCD backplane
LCDCAP/R33	30	I/O	LCD capacitor connection Input/output port of most positive analog LCD voltage (V1) CAUTION: This pin must be connected to DVSS if not used.
P5.4/SDCLK/R23	31	I/O	General-purpose digital I/O SD24_B bit stream clock input/output Input/output port of second most positive analog LCD voltage (V2)
P5.5/SD0DIO/ LCDREF/R13	32	I/O	General-purpose digital I/O SD24_B converter 0 bit stream data input/output External reference voltage input for regulated LCD voltage Input/output port of third most positive analog LCD voltage (V3 or V4)
P5.6/SD1DIO/R03	33	I/O	General-purpose digital I/O SD24_B converter 1 bit stream data input/output Input/output port of lowest analog LCD voltage (V5)
P5.7/SD2DIO/CB2	34	I/O	General-purpose digital I/O SD24_B converter 2 bit stream data input/output Comparator_B input CB2
P6.0/SD3DIO	35	I/O	General-purpose digital I/O SD24_B converter 3 bit stream data input/output
P3.6/PM_UCA2RXD/ PM_UCA2SOMI	36	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A2 UART receive data Default mapping: eUSCI_A2 SPI slave out master in
P3.7/PM_UCA2TXD/ PM_UCA2SIMO	37	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A2 UART transmit data Default mapping: eUSCI_A2 SPI slave in master out
P4.0/PM_UCA2CLK	38	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A2 clock input/output
P4.1/PM_UCA3RXD/ PM_UCA3SOMI	39	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A3 UART receive data Default mapping: eUSCI_A3 SPI slave out master in
P4.2/PM_UCA3TXD/ PM_UCA3SIMO	40	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A3 UART transmit data Default mapping: eUSCI_A3 SPI slave in master out
P4.3/PM_UCA3CLK	41	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A3 clock input/output
P4.4/PM_UCB1SOMI/ PM_UCB1SCL	42	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_B1 SPI slave out, master in Default mapping: eUSCI_B1 I²C clock
P4.5/PM_UCB1SIMO/ PM_UCB1SDA	43	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_B1 SPI slave in, master out Default mapping: eUSCI_B1 I²C data
P4.6/PM_UCB1CLK	44	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_B1 clock input/output
P4.7/PM_TA3.0	45	I/O	General-purpose digital I/O with mappable secondary function Default mapping: Timer TA3 capture CCR0: CCI0A input, compare: Out0 output
P6.1/SD4DIO/S39	46	I/O	General-purpose digital I/O SD24_B converter 4 bit stream data input/output (not available in F674x devices) LCD segment output S39
P6.2/SD5DIO/S38	47	I/O	General-purpose digital I/O SD24_B converter 5 bit stream data input/output (not available in F674x devices) LCD segment output S38
P6.3/SD6DIO/S37	48	I/O	General-purpose digital I/O SD24_B converter 6 bit stream data input/output (not available in F674x, F676x devices) LCD segment output S37
P6.4/S36	49	I/O	General-purpose digital I/O LCD segment output S36
P6.5/S35	50	I/O	General-purpose digital I/O LCD segment output S35
P6.6/S34	51	I/O	General-purpose digital I/O LCD segment output S34
P6.7/S33	52	I/O	General-purpose digital I/O LCD segment output S33
P7.0/S32	53	I/O	General-purpose digital I/O LCD segment output S32
P7.1/S31	54	I/O	General-purpose digital I/O LCD segment output S31
P7.2/S30	55	I/O	General-purpose digital I/O LCD segment output S30
P7.3/S29	56	I/O	General-purpose digital I/O LCD segment output S29
P7.4/S28	57	I/O	General-purpose digital I/O LCD segment output S28
P7.5/S27	58	I/O	General-purpose digital I/O LCD segment output S27
P7.6/S26	59	I/O	General-purpose digital I/O LCD segment output S26
P7.7/S25	60	I/O	General-purpose digital I/O LCD segment output S25
P8.0/S24	61	I/O	General-purpose digital I/O LCD segment output S24
P8.1/S23	62	I/O	General-purpose digital I/O LCD segment output S23
P8.2/S22	63	I/O	General-purpose digital I/O LCD segment output S22
P8.3/S21	64	I/O	General-purpose digital I/O LCD segment output S21
P8.4/S20	65	I/O	General-purpose digital I/O LCD segment output S20
P8.5/S19	66	I/O	General-purpose digital I/O LCD segment output S19
P8.6/S18	67	I/O	General-purpose digital I/O LCD segment output S18
P8.7/S17	68	I/O	General-purpose digital I/O LCD segment output S17
VDSYS2⁽⁶⁾	69		Digital power supply for I/Os
DVSS2	70		Digital ground supply
P9.0/S16	71	I/O	General-purpose digital I/O LCD segment output S16
P9.1/S15	72	I/O	General-purpose digital I/O LCD segment output S15
P9.2/S14	73	I/O	General-purpose digital I/O LCD segment output S14
P9.3/S13	74	I/O	General-purpose digital I/O LCD segment output S13
P9.4/S12	75	I/O	General-purpose digital I/O LCD segment output S12
P9.5/S11	76	I/O	General-purpose digital I/O LCD segment output S11
P9.6/S10	77	I/O	General-purpose digital I/O LCD segment output S10
P9.7/S9	78	I/O	General-purpose digital I/O LCD segment output S9
P10.0/S8	79	I/O	General-purpose digital I/O LCD segment output S8
P10.1/S7	80	I/O	General-purpose digital I/O LCD segment output S7
P10.2/S6	81	I/O	General-purpose digital I/O LCD segment output S6
P10.3/S5	82	I/O	General-purpose digital I/O LCD segment output S5
P10.4/S4	83	I/O	General-purpose digital I/O LCD segment output S4
P10.5/S3	84	I/O	General-purpose digital I/O LCD segment output S3
P10.6/S2	85	I/O	General-purpose digital I/O LCD segment output S2
P10.7/S1	86	I/O	General-purpose digital I/O LCD segment output S1
P11.0/S0	87	I/O	General-purpose digital I/O LCD segment output S0
P11.1/TA3.1/CB3	88	I/O	General-purpose digital I/O Timer TA3 capture CCR1: CCI1A input, compare: Out1 output Comparator_B input CB3
P11.2/TA1.1	89	I/O	General-purpose digital I/O Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
P11.3/TA2.1	90	I/O	General-purpose digital I/O Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
P11.4/CBOUT	91	I/O	General-purpose digital I/O Comparator_B Output
P11.5/TACLK/RTCCLK	92	I/O	General-purpose digital I/O Timer clock input TACLK for TA0, TA1, TA2, TA3 RTCCLK clock output
P2.0/PM_TA0.0/BSL_TX	93	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA0 capture CCR0: CCI0A input, compare: Out0 output Bootloader: Data transmit
P2.1/PM_TA0.1/BSL_RX	94	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA0 capture CCR1: CCI1A input, compare: Out1 output Bootloader: Data receive
P2.2/PM_TA0.2	95	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
P2.3/PM_TA1.0	96	I/O	General-purpose digital I/O port interrupt and with mappable secondary function Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
TEST/SBWTCK	97	I	Test mode pin – select digital I/O on JTAG pins Spy-Bi-Wire input clock
PJ.0/TDO	98	I/O	General-purpose digital I/O Test data output
PJ.1/TDI/TCLK	99	I/O	General-purpose digital I/O Test data input or Test clock input
PJ.2/TMS	100	I/O	General-purpose digital I/O Test mode select
PJ.3/TCK	101	I/O	General-purpose digital I/O Test clock
RST/NMI/SBWTDIO	102	I/O	Reset input active low⁽⁴⁾ Nonmaskable interrupt input Spy-By-Wire data input/output
SD0P0	103	I	SD24_B positive analog input for converter 0⁽⁵⁾
SD0N0	104	I	SD24_B negative analog input for converter 0⁽⁵⁾
SD1P0	105	I	SD24_B positive analog input for converter 1⁽⁵⁾
SD1N0	106	I	SD24_B negative analog input for converter 1⁽⁵⁾
SD2P0	107	I	SD24_B positive analog input for converter 2⁽⁵⁾
SD2N0	108	I	SD24_B negative analog input for converter 2⁽⁵⁾
SD3P0	109	I	SD24_B positive analog input for converter 3⁽⁵⁾
SD3N0	110	I	SD24_B negative analog input for converter 3⁽⁴⁾
VASYS2	111		Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of C_VSYS
AVSS2	112		Analog ground supply
VREF	113	I	SD24_B external reference voltage
SD4P0	114	I	SD24_B positive analog input for converter 4⁽⁵⁾ (not available on F674x devices)
SD4N0	115	I	SD24_B negative analog input for converter 4⁽⁵⁾ (not available on F674x devices)
SD5P0	116	I	SD24_B positive analog input for converter 5⁽⁵⁾ (not available on F674x devices)
SD5N0	117	I	SD24_B negative analog input for converter 5⁽⁵⁾ (not available on F674x devices)
SD6P0	118	I	SD24_B positive analog input for converter 6⁽⁵⁾ (not available on F676x, F674x devices)
SD6N0	119	I	SD24_B negative analog input for converter 6⁽⁵⁾ (not available on F676x, F674x devices)
AVSS1	120		Analog ground supply
AVCC	121		Analog power supply
VASYS1	122		Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of C_VSYS.
AUXVCC2	123		Auxiliary power supply AUXVCC2
AUXVCC1	124		Auxiliary power supply AUXVCC1
VDSYS1⁽⁶⁾	125		Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of C_VSYS.
DVCC	126		Digital power supply
DVSS1	127		Digital ground supply
VCORE⁽²⁾	128		Regulated core power supply (internal use only, no external current loading)

(1) I = input, O = output

(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, C_VCORE.

(3) Before enabling the analog function (A3), pull this pin low by setting the port function to output low or to input with the internal pulldown resistor enabled.

(4) When this pin is configured as reset, the internal pullup resistor is enabled by default.

(5) Short unused analog input pairs and connect them to analog ground.

(6) The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation.

Table 4-4 describes the signals for devices in the PZ package. See Table 4-3 for the PEU package signal descriptions.

Table 4-4 Terminal Functions – PZ Package

TERMINAL		I/O⁽¹⁾	DESCRIPTION
NAME	NO.
NAME	PZ
SD0P0	1	I	SD24_B positive analog input for converter 0⁽²⁾
SD0N0	2	I	SD24_B negative analog input for converter 0⁽²⁾
SD1P0	3	I	SD24_B positive analog input for converter 1⁽²⁾
SD1N0	4	I	SD24_B negative analog input for converter 1⁽²⁾
SD2P0	5	I	SD24_B positive analog input for converter 2⁽²⁾
SD2N0	6	I	SD24_B negative analog input for converter 2⁽²⁾
SD3P0	7	I	SD24_B positive analog input for converter 3⁽²⁾
SD3N0	8	I	SD24_B negative analog input for converter 3⁽²⁾
VASYS2	9		Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of C_VSYS.
AVSS2	10		Analog ground supply
VREF	11	I	SD24_B external reference voltage
SD4P0	12	I	SD24_B positive analog input for converter 4⁽²⁾ (not available on F674x devices)
SD4N0	13	I	SD24_B negative analog input for converter 4⁽²⁾ (not available on F674x devices)
SD5P0	14	I	SD24_B positive analog input for converter 5⁽²⁾ (not available on F674x devices)
SD5N0	15	I	SD24_B negative analog input for converter 5⁽²⁾ (not available on F674x devices)
SD6P0	16	I	SD24_B positive analog input for converter 6⁽²⁾ (not available on F676x, F674x devices)
SD6N0	17	I	SD24_B negative analog input for converter 6⁽²⁾ (not available on F676x, F674x devices)
AVSS1	18		Analog ground supply
AVCC	19		Analog power supply
VASYS1	20		Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of C_VSYS
AUXVCC2	21		Auxiliary power supply AUXVCC2
AUXVCC1	22		Auxiliary power supply AUXVCC1
VDSYS1 ⁽⁶⁾	23		Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of C_VSYS.
DVCC	24		Digital power supply
DVSS1	25		Digital ground supply
VCORE ⁽²⁾	26		Regulated core power supply (internal use only, no external current loading)
XIN	27	I/O	Input terminal for crystal oscillator
XOUT	28	I/O	Output terminal for crystal oscillator
AUXVCC3	29		Auxiliary power supply AUXVCC3 for back up subsystem
RTCCAP1	30	I	External time capture pin 1 for RTC_C
RTCCAP0	31	I	External time capture pin 0 for RTC_C
P1.5/SMCLK/CB0/A5	32	I/O	General-purpose digital I/O with port interrupt SMCLK clock output Comparator_B input CB0 Analog input A5 for 10-bit ADC
P1.4/MCLK/CB1/A4	33	I/O	General-purpose digital I/O with port interrupt MCLK clock output Comparator_B input CB1 Analog input A4 for 10-bit ADC
P1.3/ADC10CLK/A3	34	I/O	General-purpose digital I/O with port interrupt ADC10_A clock output Analog input A3 for 10-bit ADC
P1.2/ACLK/A2	35	I/O	General-purpose digital I/O with port interrupt ACLK clock output Analog input A2 for 10-bit ADC
P1.1/TA2.1/CBOUT/ VeREF+/A1	36	I/O	General-purpose digital I/O with port interrupt Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output Comparator_B Output Positive terminal for the ADC reference voltage for an external applied reference voltage Analog input A1 for 10-bit ADC
P1.0/TA1.1/VeREF-/A0	37	I/O	General-purpose digital I/O with port interrupt Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output Negative terminal for the ADC reference voltage for an external applied reference voltage Analog input A0 for 10-bit ADC
COM0	38	I/O	LCD common output COM0 for LCD backplane
COM1	39	I/O	LCD common output COM1 for LCD backplane
P1.6/COM2	40	I/O	General-purpose digital I/O with port interrupt LCD common output COM2 for LCD backplane
P1.7/COM3	41	I/O	General-purpose digital I/O with port interrupt LCD common output COM3 for LCD backplane
P2.0/PM_TA0.0/ BSL_TX/COM4	42	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default Mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output Bootloader: Data transmit LCD common output COM4 for LCD backplane
P2.1/PM_TA0.1/ BSL_RX/COM5	43	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default Mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output Bootloader: Data receive LCD common output COM5 for LCD backplane
P2.2/PM_TA0.2/COM6	44	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default Mapping: Timer TA0 CCR0 capture: CCI2A input, compare: Out2 output LCD common output COM6 for LCD backplane
P2.3/PM_TA1.0/COM7	45	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default Mapping: Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output LCD common output COM7 for LCD backplane
LCDCAP/R33	46	I/O	LCD capacitor connection Input/output port of most positive analog LCD voltage (V1) CAUTION: This pin must be connected to DVSS if not used.
P2.4/PM_TA2.0/R23	47	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default Mapping: Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output Input/output port of second most positive analog LCD voltage (V2)
P2.5/PM_UCB0SOMI/ PM_UCB0SCL/LCDREF/ R13	48	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_B0 SPI slave out, master in Default mapping: eUSCI_B0 I²C clock External reference voltage input for regulated LCD voltage Input/output port of third most positive analog LCD voltage (V3 or V4)
P2.6/PM_UCB0SIMO/ PM_UCB0SDA/R03	49	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_B0 SPI slave in, master out Default mapping: eUSCI_B0 I²C data Input/output port of lowest analog LCD voltage (V5)
P2.7/PM_UCB0CLK/CB2	50	I/O	General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_B0 clock input/output Comparator_B input CB2
P3.0/PM_UCA0RXD/ PM_UCA0SOMI	51	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A0 UART receive data Default mapping: eUSCI_A0 SPI slave out, master in
P3.1/PM_UCA0TXD/ PM_UCA0SIMO/S39	52	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A0 UART transmit data Default mapping: eUSCI_A0 SPI slave in, master out LCD segment output S39
P3.2/PM_UCA0CLK/S38	53	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A0 clock input/output LCD segment output S38
P3.3/PM_UCA1CLK/S37	54	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A1 clock input/output LCD segment output S37
P3.4/PM_UCA1RXD/ PM_UCA1SOMI/S36	55	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A1 UART receive data Default mapping: eUSCI_A1 SPI slave out, master in LCD segment output S36
P3.5/PM_UCA1TXD/ PM_UCA1SIMO/S35	56	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A1 UART transmit data Default mapping: eUSCI_A1 SPI slave in, master out LCD segment output S35
P3.6/PM_UCA2RXD/ PM_UCA2SOMI/S34	57	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A2 UART receive data Default mapping: eUSCI_A2 SPI slave out, master in LCD segment output S34
P3.7/PM_UCA2TXD/ PM_UCA2SIMO/S33	58	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A2 UART transmit data Default mapping: eUSCI_A2 SPI slave in, master out LCD segment output S33
P4.0/PM_UCA2CLK/S32	59	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A2 clock input/output LCD segment output S32
P4.1/PM_UCA3RXD/ PM_UCA3SOMI/S31	60	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A3 UART receive data Default mapping: eUSCI_A3 SPI slave out, master in LCD segment output S31
P4.2/PM_UCA3TXD/ PM_UCA3SIMO/S30	61	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A3 UART transmit data Default mapping: eUSCI_A3 SPI slave in, master out LCD segment output S30
P4.3/PM_UCA3CLK/S29	62	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A3 clock input/output LCD segment output S29
P4.4/PM_UCB1SOMI/ PM_UCB1SCL/S28	63	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_B1 SPI slave out, master in Default mapping: eUSCI_B1 I²C clock LCD segment output S28
P4.5/PM_UCB1SIMO/ PM_UCB1SDA/S27	64	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_B1 SPI slave in, master out Default mapping: eUSCI_B1 I²C data LCD segment output S27
P4.6/PM_UCB1CLK/S26	65	I/O	General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_B1 clock input/output LCD segment output S26
P4.7/PM_TA3.0/S25	66	I/O	General-purpose digital I/O with mappable secondary function Default Mapping: Timer TA3 CCR0 capture: CCI0A input, compare: Out0 output LCD segment output S25
P5.0/SDCLK/S24	67	I/O	General-purpose digital I/O SD24_B bit stream clock input/output LCD segment output S24
P5.1/PM_SD0DIO/S23	68	I/O	General-purpose digital I/O Default mapping: SD24_B converter 0 bit stream data input/output LCD segment output S23
P5.2/PM_SD1DIO/S22	69	I/O	General-purpose digital I/O Default mapping: SD24_B converter 1 bit stream data input/output LCD segment output S22
P5.3/PM_SD2DIO/S21	70	I/O	General-purpose digital I/O Default mapping: SD24_B converter 2 bit stream data input/output LCD segment output S21
P5.4/PM_SD3DIO/S20	71	I/O	General-purpose digital I/O Default mapping: SD24_B converter 3 bit stream data input/output LCD segment output S20
P5.5/PM_SD4DIO/S19	72	I/O	General-purpose digital I/O Default mapping: SD24_B converter 4 bit stream data input/output (not available on F674x devices) LCD segment output S19
P5.6/PM_SD5DIO/S18	73	I/O	General-purpose digital I/O Default mapping: SD24_B converter 5 bit stream data input/output (not available on F674x devices) LCD segment output S18
P5.7/PM_SD6DIO/S17	74	I/O	General-purpose digital I/O Default mapping: SD24_B converter 4 bit stream data input/output (not available on F676x, F674x devices) LCD segment output S17
VDSYS2⁽³⁾	75		Digital power supply for I/Os
DVSS2	76		Digital ground supply
P6.0/S16	77	I/O	General-purpose digital I/O LCD segment output S16
P6.1/S15	78	I/O	General-purpose digital I/O LCD segment output S15
P6.2/S14	79	I/O	General-purpose digital I/O LCD segment output S14
P6.3/S13	80	I/O	General-purpose digital I/O LCD segment output S13
P6.4/S12	81	I/O	General-purpose digital I/O LCD segment output S12
P6.5/S11	82	I/O	General-purpose digital I/O LCD segment output S11
P6.6/S10	83	I/O	General-purpose digital I/O LCD segment output S10
P6.7/S9	84	I/O	General-purpose digital I/O LCD segment output S9
P7.0/S8	85	I/O	General-purpose digital I/O LCD segment output S8
P7.1/S7	86	I/O	General-purpose digital I/O LCD segment output S7
P7.2/S6	87	I/O	General-purpose digital I/O LCD segment output S6
P7.3/S5	88	I/O	General-purpose digital I/O LCD segment output S5
P7.4/S4	89	I/O	General-purpose digital I/O LCD segment output S4
P7.5/S3	90	I/O	General-purpose digital I/O LCD segment output S3
P7.6/S2	91	I/O	General-purpose digital I/O LCD segment output S2
P7.7/S1	92	I/O	General-purpose digital I/O LCD segment output S1
P8.0/S0	93	I/O	General-purpose digital I/O LCD segment output S0
P8.1/TACLK/RTCCLK/CB3	94	I/O	General-purpose digital I/O Timer clock input TACLK for TA0, TA1, TA2, TA3 RTCCLK clock output Comparator_B input CB3
TEST/SBWTCK	95	I	Test mode pin – select digital I/O on JTAG pins Spy-By-Wire input clock
PJ.0/TDO	96	I/O	General-purpose digital I/O Test data output
PJ.1/TDI/TCLK	97	I/O	General-purpose digital I/O Test data input or Test clock input
PJ.2/TMS	98	I/O	General-purpose digital I/O Test mode select
PJ.3/TCK	99	I/O	General-purpose digital I/O Test clock
RST/NMI/SBWTDIO	100	I/O	Reset input, active low⁽⁴⁾ Nonmaskable interrupt input Spy-By-Wire data input/output

(1) I = input, O = output

(2) Short unused analog input pairs and connect them to analog ground.

(3) The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation.

5 Specifications

All graphs in this section are for typical conditions, unless otherwise noted.

Typical (TYP) values are specified at V_CC = 3.3 V and T_A = 25°C, unless otherwise noted.

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage applied at DVCC to DVSS		–0.3	4.1	V
Voltage applied to pins⁽²⁾	All pins except VCORE, SD24_B input pins (SDxN0, SDxP0)⁽³⁾, AUXVCC1, AUXVCC2, and AUXVCC3⁽⁴⁾	–0.3	V_CC + 0.3	V
Diode current at pins	All pins except SD24_B input pins (SDxN0, SDxP0)		±2	mA
Diode current at pins	SD0N0, SD0P0, SD1N0, SD1P0, SD2N0, SD2P0, SD3N0, SD3P0, SD4N0, SD4P0, SD5N0, SD5P0, SD6N0, SD6P0⁽⁵⁾		2	mA
Maximum junction temperature, T_J			95	°C
Storage temperature, T_stg⁽⁶⁾		–55	105	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS = V_DVSS = V_AVSS.

(3) See Section 5.48 for SD24_B specifications.

(4) See Section 5.27 for AUX specifications.

(5) A protection diode is connected to V_CC for the SD24_B input pins. No protection diode is connected to V_SS.

(6) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance.

5.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
V_CC	Supply voltage during program execution and flash programming. V_AVCC = V_DVCC = V_CC⁽¹⁾⁽²⁾	PMMCOREVx = 0	1.8		3.6	V
		PMMCOREVx = 0, 1	2.0		3.6
		PMMCOREVx = 0, 1, 2	2.2		3.6
		PMMCOREVx = 0, 1, 2, 3	2.4		3.6
V_SS	Supply voltage V_AVSS = V_DVSS = V_SS			0		V
T_A	Operating free-air temperature	I version	–40		85	°C
T_J	Operating junction temperature	I version	–40		85	°C
C_VCORE	Recommended capacitor at VCORE⁽³⁾			470		nF
C_DVCC/ C_VCORE	Capacitor ratio of DVCC to VCORE		10
f_SYSTEM	Processor frequency (maximum MCLK frequency)⁽⁴⁾⁽⁵⁾ (see Figure 5-1)	PMMCOREVx = 0, 1.8 V ≤ V_CC ≤ 3.6 V (default condition)	0		8.0	MHz
		PMMCOREVx = 1, 2 V ≤ V_CC ≤ 3.6 V	0		12.0
		PMMCOREVx = 2, 2.2 V ≤ V_CC ≤ 3.6 V	0		20.0
		PMMCOREVx = 3, 2.4 V ≤ V_CC ≤ 3.6 V	0		25.0
I_{LOAD, DVCCD}	Maximum load current that can be drawn from DVCC for core and IO (I_LOAD = I_CORE + I_IO)				20	mA
I_{LOAD, AUX1D}	Maximum load current that can be drawn from AUXVCC1 for core and IO (I_LOAD = I_CORE + I_IO)				20	mA
I_{LOAD, AUX2D}	Maximum load current that can be drawn from AUXVCC2 for core and IO (I_LOAD = I_CORE + I_IO)				20	mA
I_{LOAD, AVCCA}	Maximum load current that can be drawn from AVCC for analog modules (I_LOAD = I_Modules)				10	mA
I_{LOAD, AUX1A}	Maximum load current that can be drawn from AUXVCC1 for analog modules (I_LOAD = I_Modules)				5	mA
I_{LOAD, AUX2A}	Maximum load current that can be drawn from AUXVCC2 for analog modules (I_LOAD = I_Modules)				5	mA
P_INT	Internal power dissipation		V_CC × I_DVCC			W
P_IO	I/O power dissipation of the I/O pins powered by DVCC		(V_CC – V_IOH) × I_IOH + V_IOL × I_IOL			W
P_MAX	Maximum allowed power dissipation, P_MAX > P_IO + P_INT		(T_J – T_A)/θ_JA			W

(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between V_AVCC and V_DVCC can be tolerated during power up and operation.

(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in Section 5.22 for the exact values and more details.

(3) A capacitor tolerance of ±20% or better is required.

(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of the specified maximum frequency.

(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

Figure 5-1 Maximum System Frequency

5.4 Active Mode Supply Current Into V_CC Excluding External Current

over recommended operating free-air temperature (unless otherwise noted)⁽¹⁾⁽²⁾⁽³⁾

PARAMETER	EXECUTION MEMORY	V_CC	PMM COREVx	FREQUENCY (f_DCO = f_MCLK = f_SMCLK)										UNIT
				1 MHz		8 MHz		12 MHz		20 MHz		25 MHz
				TYP	MAX	TYP	MAX	TYP	MAX	TYP	MAX	TYP	MAX
I_{AM, Flash}⁽⁴⁾	Flash	3 V	0	0.32	0.50	2.08	2.84							mA
			1	0.35		2.35		3.50	4.76
			2	0.39		2.68		3.99		6.61	8.3
			3	0.41		2.83		4.22		6.98		8.67	11.75
I_{AM, RAM}⁽⁵⁾	RAM	3 V	0	0.19		1.04								mA
			1	0.21		1.20		1.77
			2	0.23		1.38		2.04		3.35
			3	0.24		1.47		2.18		3.58		4.44

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF.

(3) Characterized with program executing typical data processing.
f_ACLK = 32786 Hz, f_DCO = f_MCLK = f_SMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.

(4) Active mode supply current when program executes in flash at a nominal supply voltage of 3 V.

(5) Active mode supply current when program executes in RAM at a nominal supply voltage of 3 V.