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  • MSPM0G150x Mixed-Signal Microcontrollers

    • SLASEW9D February   2023  – March 2025 MSPM0G1505 , MSPM0G1506 , MSPM0G1507

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  • CONTENTS
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  • MSPM0G150x Mixed-Signal Microcontrollers
  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
        1. 7.6.1.1 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 SYSOSC Typical Frequency Accuracy
        1. 7.9.2.1 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
    13. 7.13 Typical Connection Diagram
    14. 7.14 Temperature Sensor
    15. 7.15 VREF
      1. 7.15.1 Voltage Characteristics
      2. 7.15.2 Electrical Characteristics
    16. 7.16 Comparator (COMP)
      1. 7.16.1 Comparator Electrical Characteristics
    17. 7.17 DAC
      1. 7.17.1 DAC_Supply Specifications
      2. 7.17.2 DAC Output Specifications
      3. 7.17.3 DAC Dynamic Specifications
      4. 7.17.4 DAC Linearity Specifications
      5. 7.17.5 DAC Timing Specifications
    18. 7.18 GPAMP
      1. 7.18.1 Electrical Characteristics
      2. 7.18.2 Switching Characteristics
    19. 7.19 OPA
      1. 7.19.1 Electrical Characteristics
      2. 7.19.2 Switching Characteristics
      3. 7.19.3 PGA Mode
    20. 7.20 I2C
      1. 7.20.1 I2C Characteristics
      2. 7.20.2 I2C Filter
        1. 7.20.2.1 I2C Timing Diagram
    21. 7.21 SPI
      1. 7.21.1 SPI
      2. 7.21.2 SPI Timing Diagram
    22. 7.22 UART
    23. 7.23 TIMx
    24. 7.24 TRNG
      1. 7.24.1 TRNG Electrical Characteristics
      2. 7.24.2 TRNG Switching Characteristics
    25. 7.25 Emulation and Debug
      1. 7.25.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G150x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 COMP
    16. 8.16 DAC
    17. 8.17 OPA
    18. 8.18 GPAMP
    19. 8.19 TRNG
    20. 8.20 AES
    21. 8.21 CRC
    22. 8.22 UART
    23. 8.23 I2C
    24. 8.24 SPI
    25. 8.25 WWDT
    26. 8.26 RTC
    27. 8.27 Timers (TIMx)
    28. 8.28 Device Analog Connections
    29. 8.29 Input/Output Diagrams
    30. 8.30 Serial Wire Debug Interface
    31. 8.31 Bootstrap Loader (BSL)
    32. 8.32 Device Factory Constants
    33. 8.33 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • PM|64
    • MTQF008B
  • PT|48
    • MTQF003C
  • RGE|24
    • MPQF124G
  • DGS|28
    • MPSS139
  • RGZ|48
    • MPQF123F
  • RHB|32
    • MPQF130D
Thermal pad, mechanical data (Package|Pins)
  • RGE|24
    • QFND136Y
  • RGZ|48
    • QFND014T
  • RHB|32
    • QFND029X
Orderable Information
  • slasew9d_oa
  • slasew9d_pm
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

Data Sheet

MSPM0G150x Mixed-Signal Microcontrollers

1 Features

  • Core
    • Arm® 32-bit Cortex®-M0+ CPU with memory protection unit, frequency up to 80MHz
  • Functional Safety Quality-Managed
    • Functional Safety Manual and FMEDA available to aid in functional safety system design
  • Operating characteristics
    • Extended temperature: –40°C up to 125°C
    • Wide supply voltage range: 1.62V to 3.6V
  • Memories
    • Up to 128KB of flash memory with error correction code (ECC)
    • Up to 32KB of SRAM with hardware parity
  • High-performance analog peripherals
    • Two simultaneous sampling 12-bit 4Msps analog-to-digital converters (ADCs) with up to 17 external channels
      • 14-bit effective resolution at 250ksps with hardware averaging
    • One 12-bit 1Msps digital-to-analog converter with integrated output buffer (DAC)
    • Two zero-drift zero-crossover chopper op-amps (OPA)
      • 0.5µV/°C drift with chopping
      • Integrated programmable gain stage, up to 32x
    • One general-purpose amplifier (GPAMP)
    • Three high-speed comparators (COMP) with 8-bit reference DACs
      • 32ns propagation delay in high-speed mode
      • Support low-power mode operation down to 0.7µA
    • Programmable analog connections between ADC, OPAs, COMP and DAC
    • Configurable 1.4V or 2.5V internal shared voltage reference (VREF)
    • Integrated temperature sensor
    • Integrated supply monitor
  • Optimized low-power modes
    • RUN: 101µA/MHz (CoreMark)
    • SLEEP: 487µA at 4MHz
    • STOP: 47µA at 32kHz
    • STANDBY: 1.5µA with RTC and SRAM retention
    • SHUTDOWN: 80nA with IO wake-up capability
  • Intelligent digital peripherals
    • 7-channel DMA controller
    • Math accelerator supports DIV, SQRT, MAC and TRIG computations
    • Seven timers supporting up to 22 PWM channels
      • One 16-bit general-purpose timer
      • One 16-bit general-purpose timer supports QEI
      • Two 16-bit general-purpose timers support low-power operation in STANDBY mode
      • One 32-bit high-resolution general-purpose timer
      • Two 16-bit advanced timers with deadband support up to 12 PWM channels
    • Two window-watchdog timers
    • RTC with alarm and calendar mode
  • Enhanced communication interfaces
    • Four UART interfaces; one supports LIN, IrDA, DALI, Smart Card, Manchester, and three support low-power operation in STANDBY mode
    • Two I2C interfaces support up to FM+ (1Mbit/s), SMBus/PMBus, and wakeup from STOP mode

    • Two SPIs, one SPI supports up to 32Mbits/s

  • Clock system
    • Internal 4MHz to 32MHz oscillator with up to ±1.2% accuracy (SYSOSC)
    • Phase-locked loop (PLL) up to 80MHz
    • Internal 32kHz low-frequency oscillator (LFOSC) with ±3% accuracy
    • External 4MHz to 48MHz crystal oscillator (HFXT)
    • External 32kHz crystal oscillator(LFXT)
    • External clock input
  • Data integrity and encryption
    • Cyclic redundancy checker (CRC-16, CRC-32)
    • True random number generator (TRNG)
    • AES encryption with 128- or 256-bit key
  • Flexible I/O features
    • Up to 60 GPIOs
      • Two 5V-tolerant IOs
      • Two high-drive IOs with 20mA drive strength
  • Development support
    • 2-pin serial wire debug (SWD)
  • Package options
    • 64-pin LQFP
    • 48-pin LQFP, VQFN
    • 32-pin VQFN
    • 32 and 28-pin VSSOP
    • 28-pin WCSP
    • 24-pin VQFN
  • Family members (also see Device Comparison)
    • MSPM0G1505: 32KB flash, 16KB RAM
    • MSPM0G1506: 64KB flash, 32KB RAM
    • MSPM0G1507: 128KB flash, 32KB RAM
  • Development kits and software (also see Tools and Software)
    • LP-MSPM0G3507 LaunchPad™ development kit
    • MSP Software Development Kit (SDK)

2 Applications

  • Motor control
  • Home appliances
  • Uninterruptible power supplies and inverters
  • Electronic point of sale systems
  • Medical and healthcare
  • Test and measurement
  • Factory automation and control
  • Industrial transport
  • Grid infrastructure
  • Smart metering
  • Communication modules
  • Lighting

3 Description

MSPM0G150x microcontrollers (MCUs) are part of the MSP highly integrated, ultra-low-power 32-bit MCU family based on the enhanced Arm®Cortex®-M0+ 32-bit core platform operating at up to 80-MHz frequency. These cost-optimized MCUs offer high-performance analog peripheral integration, support extended temperature ranges from -40°C to 125°C, and operate with supply voltages ranging from 1.62 V to 3.6 V.

The MSPM0G150x devices provide up to 128KB embedded flash program memory with built-in error correction code (ECC) and up to 32KB SRAM with hardware parity option. These MCUs also incorporate a memory protection unit, 7-channel DMA, math accelerator, and a variety of high-performance analog peripherals such as two 12-bit 4-Msps ADCs, configurable internal shared voltage reference, one 12-bit 1-Msps DAC, three high speed comparators with built-in reference DACs, two zero-drift zero-crossover op-amps with programmable gain, and one general-purpose amplifier. These devices also offer intelligent digital peripherals such as two 16-bit advanced control timers, five general-purpose timers (with one 16-bit general-purpose timer for QEI interface, two 16-bit general-purpose timers for STANDBY mode, and one 32-bit general-purpose timer), two windowed-watchdog timers, and one RTC with alarm and calendar modes. These devices provide data integrity and encryption peripherals (AES, CRC, TRNG) and enhanced communication interfaces (four UART, two I2C, two SPI).

The TI MSPM0 family of low-power MCUs consists of devices with varying degrees of analog and digital integration allowing for customers find the MCU that meets their project's needs. The MSPM0 MCU platform combines the Arm Cortex-M0+ platform with a holistic ultra-low-power system architecture, allowing system designers to increase performance while reducing energy consumption.

MSPM0G150x MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get the design started quickly. Development kits include a LaunchPad available for purchase. TI also provides a free MSP Software Development Kit (SDK), which is available as a component of Code Composer Studio™ IDE desktop and cloud version within the TI Resource Explorer. MSPM0 MCUs are also supported by extensive online collateral, training with MSP Academy, and online support through the TI E2E™ support forums.

For complete module descriptions, see the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.

CAUTION:

System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturbing of data or code memory. See MSP430™ System-Level ESD Considerations for more information. The principles in this application note are applicable to MSPM0 MCUs.

4 Functional Block Diagram

Figure 4-1 shows the MSPM0G150x functional block diagram.

MSPM0G1507 MSPM0G1506 MSPM0G1505 MSPM0G150x Functional Block Diagram Figure 4-1 MSPM0G150x Functional Block Diagram

5 Device Comparison

The following table summarizes the features of each device that is described in this data sheet.

Table 5-1 Device Comparison
DEVICE NAME(1)(4) FLASH /SRAM (KB) QUAL(2) MATH ACCEL ADC / CHAN COMP DAC OPA GPAMP UART / I2C / SPI TIMA TIMG GPIO PACKAGE [PACKAGE SIZE] (3)
MSPM0G1505xPM 32 / 16 S Y 2 / 17 3 1 2 1 4 / 2 / 2 2 5 60 64 LQFP
[12mm × 12mm]
MSPM0G1506xPM 64 / 32
MSPM0G1507xPM 128 / 32
MSPM0G1505xPT 32 / 16 S Y 2 / 16 3 1 2 1 4 / 2 / 2 2 5 44 48 LQFP
[9mm × 9mm]
MSPM0G1506xPT 64 / 32
MSPM0G1507xPT 128 / 32
MSPM0G1505xRGZ 32 / 16 S Y 2 / 16 3 1 2 1 4 / 2 / 2 2 5 44 48 VQFN
[7mm × 7mm]
MSPM0G1506xRGZ 64 / 32
MSPM0G1507xRGZ 128 / 32
MSPM0G1505xRHB 32 / 16 S Y 2 / 11 3 1 2 1 4 / 2 / 2 2 5 28 32 VQFN
[5mm × 5mm]
MSPM0G1506xRHB 64 / 32
MSPM0G1507xRHB 128 / 32
MSPM0G1505xDGS28 32 / 16 S Y 2 / 11 3 1 2 1 4 / 2 / 2 2 5 24 28 VSSOP
[7.1mm × 4.9mm]
MSPM0G1506xDGS28 64 / 32
MSPM0G1507xDGS28 128 / 32
MSPM0G1505xRGE 32 / 16 S Y 2 / 9 3 1 2 1 4 / 2 / 2 2 5 20 24 VQFN
[4mm × 4mm]
MSPM0G1506xRGE 64 / 32
MSPM0G1507xRGE 128 / 32
MSPM0G1506xYCJ 64 / 32 S Y 2 / 10 2 1 1 1 3 / 2 / 2 2 5 24 28 WCSP
[2.65 mm × 1.57 mm]
MSPM0G1507xYCJ 128 / 32
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 12, or see the TI website.
(2) Device Qualifications:
  • S = –40°C to 125°C
(3) The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, see Section 12.
(4) For more information about the device name, see Section 10.2

6 Pin Configuration and Functions

The System Configuration tool provides a graphical interface to enable, configurable, and generate initialization code for pin multiplexing and simplifying pin settings. The following pin diagrams show the primary peripheral functions, some of the integrated device features, and available clock signals to simplify the device pinout. For full descriptions of the pin functions, see the Pin Attributes and Signal Descriptions sections.

6.1 Pin Diagrams

MSPM0G1507 MSPM0G1506 MSPM0G1505 Pin Diagram Color Coding Figure 6-1 Pin Diagram Color Coding
MSPM0G1507 MSPM0G1506 MSPM0G1505 64-Pin PM (LQFP) (Top View) Figure 6-2 64-Pin PM (LQFP) (Top View)
MSPM0G1507 MSPM0G1506 MSPM0G1505 48-Pin PT (LQFP) (Top View) Figure 6-3 48-Pin PT (LQFP) (Top View)
MSPM0G1507 MSPM0G1506 MSPM0G1505 48-Pin RGZ (VQFN) (Top View) Figure 6-4 48-Pin RGZ (VQFN) (Top View)
MSPM0G1507 MSPM0G1506 MSPM0G1505 32-Pin RHB (VQFN) (Top View) Figure 6-5 32-Pin RHB (VQFN) (Top View)
MSPM0G1507 MSPM0G1506 MSPM0G1505 28-Pin DGS28 (VSSOP) (Top View) Figure 6-6 28-Pin DGS28 (VSSOP) (Top View)
MSPM0G1507 MSPM0G1506 MSPM0G1505 24-Pin RGE (VQFN) (Top View) Figure 6-7 24-Pin RGE (VQFN) (Top View)
MSPM0G1507 MSPM0G1506 MSPM0G1505 28-Pin YCJ (WCSP) (Top View) Figure 6-8 28-Pin YCJ (WCSP) (Top View)
Note: For full pin configuration and functions for each package option, refer to

Pin Attributes and Signal Descriptions.

6.2 Pin Attributes

The following table describes the functions available on every pin for each device package.

Note: Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits.
Table 6-1 Pin Attributes
PINCMx PIN NAME SIGNAL NAMES PIN NUMBER IO STRUCTURE
ANALOG DIGITAL [PIN FUNCTION] (1) 64 LQFP 48 LQFP, VQFN 32 VQFN 28 VSSOP 24 VQFN 28 WCSP
N/A VDD 40 6 4 7 3 C4 Power
N/A VSS 41 7 5 8 4 D4 Power
N/A VCORE 32 48 32 3 23 A4 Power
N/A NRST 38 4 3 6 2 B4 Reset
1 PA0 UART0_TX [2] / I2C0_SDA [3] / TIMA0_C0 [4] / TIMA_FAL1 [5] / TIMG8_C1 [6] / FCC_IN [7]/(Default BSL I2C_SDA) 33 1 1 4 24 D3 5V-tolerant open drain
2 PA1 UART0_RX [2] / I2C0_SCL [3] / TIMA0_C1 [4] / TIMA_FAL2 [5] / TIMG8_IDX [6] / TIMG8_C0 [7]/(Default BSL I2C_SCL) 34 2 2 5 1 E3 5V-tolerant open drain
7 PA2 ROSC TIMG8_C1 [2] / SPI0_CS0 [3] / TIMG7_C1 [4] / SPI1_CS0 [5] 42 8 6 9 5 E4 Standard
8 PA3 LFXIN TIMG8_C0 [2] / SPI0_CS1 [3] / UART2_CTS [4] / TIMA0_C2 [5] / COMP1_OUT [6] / TIMG7_C0 [7] / TIMA0_C1 [8] / I2C1_SDA [9] 43 9 7 10 6 F4 Standard
9 PA4 LFXOUT TIMG8_C1 [2] / SPI0_POCI [3] / UART2_RTS [4] / TIMA0_C3 [5] / LFCLK_IN [6] / TIMG7_C1 [7] / TIMA0_C1N [8] / I2C1_SCL [9] 44 10 8 11 7 G4 Standard
10 PA5 HFXIN TIMG8_C0 [2] / SPI0_PICO [3] / TIMA_FAL1 [4] / TIMG0_C0 [5]/ TIMG6_C0 [6] / FCC_IN [7] 45 11 9 12 - F3 Standard
11 PA6 HFXOUT TIMG8_C1 [2] / SPI0_SCK [3] / TIMA_FAL0 [4] / TIMG0_C1 [5] / HFCLK_IN [6] / TIMG6_C1 [ 7] / TIMA0_C2N [8] 46 12 10 13 - G3 Standard
14 PA7 COMP0_OUT [2] / CLK_OUT [3] / TIMG8_C0 [4] / TIMA0_C2 [5] / TIMG8_IDX [6] / TIMG7_C1 [7] / TIMA0_C1 [8] 49 13 11 - - - Standard
19 PA8 UART1_TX [2] / SPI0_CS0 [3] / UART0_RTS [4] / TIMA0_C0 [5] / TIMA1_C0N [6] 54 16 12 - - - Standard
20 PA9 UART1_RX [2] / SPI0_PICO [3] / UART0_CTS [4] / TIMA0_C1 [5] / RTC_OUT [6] / TIMA0_C0N [7] / TIMA1_C1N [8] / CLK_OUT [9] 55 17 13 14 8 F2 High-Speed
21 PA10 UART0_TX [2] / SPI0_POCI [3] / I2C0_SDA [4] / TIMA1_C0 [5] / TIMG12_C0 [6] / TIMA0_C2 [7] / I2C1_SDA [8] / CLK_OUT [9]/(Default BSL UART_TX) 56 18 14 15 9 G1 High-Drive
22 PA11 UART0_RX [2] / SPI0_SCK [3] / I2C0_SCL [4] / TIMA1_C1 [5] / COMP0_OUT [6]/ TIMA0_C2N [7] / I2C1_SCL [8]/(Default BSL UART_RX) 57 19 15 16 10 G2 High-Drive
34 PA12 UART3_CTS [2] / SPI0_SCK [3] / TIMG0_C0 [4] / TIMA0_C3 [6] / FCC_IN [7] 5 27 16 - - - High-Speed
35 PA13 COMP0_IN2- UART3_RTS [2] / SPI0_POCI [3] / UART3_RX [4] / TIMG0_C1 [5] / TIMA0_C3N [7] 6 28 17 - - - High-Speed
36 PA14 COMP0_IN2+ / A0_12 UART0_CTS [2] / SPI0_PICO [3] / UART3_TX [4] / TIMG12_C0 [5] / CLK_OUT [6] 7 29 18 17 - - High-Speed
37 PA15 A1_0 / DAC_OUT / OPA0_IN2+ / OPA1_IN2+/ COMP0_IN3+ /COMP1_IN3+ UART0_RTS [2] / SPI1_CS2 [3] / I2C1_SCL [4] / TIMA1_C0 [5] / TIMG8_IDX [6] / TIMA1_C0N [7] / TIMA0_C2 [8] 8 30 19 18 11 F1 Standard
38 PA16 A1_1 / OPA1_OUT COMP2_OUT [2] / SPI1_POCI [3] / I2C1_SDA [4] / TIMA1_C1 [5] / TIMA1_C1N [6] / TIMA0_C2N [7] / FCC_IN [8] 9 31 20 19 12 E1 Standard
39 PA17 A1_2 / OPA1_IN1- / COMP0_IN1- UART1_TX [2] / SPI1_SCK [3] / I2C1_SCL [4] / TIMA0_C3 [5] / TIMG7_C0 [6] / TIMA1_C0 [7] 10 32 21 20 13 - Standard with wake(2)
40 PA18 A1_3 / OPA1_IN1+ / COMP0_IN1+ / GPAMP_IN- UART1_RX [2] / SPI1_PICO [3] / I2C1_SDA [4] / TIMA0_C3N [5] / TIMG7_C1 [6] / TIMA1_C1 [7]/Default BSL_Invoke 11 33 22 21 14 B1 Standard with wake(2)
41 PA19 SWDIO [2] 12 34 23 22 15 C1 High-Speed
42 PA20 SWCLK [2] 13 35 24 23 16 D1 Standard
46 PA21 A1_7 / COMP2_IN1- / VREF- UART2_TX [2] / TIMG8_C0 [3] / UART1_CTS [4] / TIMA0_C0 [5] / TIMG6_C0 [6] 17 39 25 24 17 D2 Standard
47 PA22 A0_7 / GPAMP_OUT / OPA0_OUT UART2_RX [2] / TIMG8_C1 [3] / UART1_RTS [4] / TIMA0_C1 [5] / CLK_OUT [6] / TIMA0_C0N [7] / TIMG6_C1 [8] 18 40 26 25 18 C2 Standard
53 PA23 COMP1_IN1- / VREF+ UART2_TX [2] / SPI0_CS3 [3] / TIMA0_C3 [4] / TIMG0_C0 [5] / UART3_CTS [6] / TIMG7_C0 [7]/ TIMG8_C0 [8] 24 43 27 26 19 A2 Standard
54 PA24 A0_3 / OPA0_IN1- UART2_RX [2] / SPI0_CS2 [3] / TIMA0_C3N [4] / TIMG0_C1 [5] / UART3_RTS [6] / TIMG7_C1 [7] / TIMA1_C1 [8] 25 44 28 27 20 A3 Standard
55 PA25 A0_2 / OPA0_IN1+ UART3_RX [2] / SPI1_CS3 [3] / TIMG12_C1 [4] / TIMA0_C3 [5] / TIMA0_C1N [6] 26 45 29 28 21 E2 Standard
59 PA26 A0_1 / COMP0_IN0+ / OPA0_IN0+ / GPAMP_IN+ UART3_TX [2] / SPI1_CS0 [3] / TIMG8_C0 [4] / TIMA_FAL0 [5] / TIMG7_C0 [7] 30 46 30 1 22 B3 Standard
60 PA27 A0_0 / COMP0_IN0- / OPA0_IN0- RTC_OUT [2] / SPI1_CS1 [3] / TIMG8_C1 [4] / TIMA_FAL2 [5] / TIMG7_C1 [7] 31 47 31 2 - C3 Standard
3 PA28 UART0_TX [2] / I2C0_SDA [3] / TIMA0_C3 [4] / TIMA_FAL0 [5] / TIMG7_C0 [6] / TIMA1_C0 [ 7] 35 3 - - - - High-Drive
4 PA29 I2C1_SCL [2] / UART2_RTS [3] / TIMG8_C0 [4] / TIMG6_C0 [5] 36 - - - - - Standard
5 PA30 I2C1_SDA [2] / UART2_CTS [3] / TIMG8_C1 [4] / TIMG6_C1 [5] 37 - - - - - Standard
6 PA31 UART0_RX [2] / I2C0_SCL [3] / TIMA0_C3N [4] / TIMG12_C1 [5] / CLK_OUT [6]/ TIMG7_C1 [7] / TIMA1_C1 [8] 39 5 - - - - High-Drive
12 PB0 UART0_TX [2] / SPI1_CS2 [3] / TIMA1_C0 [4] / TIMA0_C2 [5] 47 - - - - - Standard
13 PB1 UART0_RX [2] / SPI1_CS3 [3] / TIMA1_C1 [4] / TIMA0_C2N [5] 48 – – - - - Standard
15 PB2 UART3_TX [2] / UART2_CTS [3] / I2C1_SCL [4] / TIMA0_C3 [5] / UART1_CTS [6] / TIMG6_C0 [ 7] / TIMA1_C0 [8] 50 14 – - - - Standard
16 PB3 UART3_RX [2] / UART2_RTS [3] / I2C1_SDA [4] / TIMA0_C3N[5] / UART1_RTS [6] / TIMG6_C1 [7] / TIMA1_C1 [8] 51 15 – - - - Standard
17 PB4 UART1_TX [2] / UART3_CTS [3] / TIMA1_C0 [4] /TIMA0_C2 [5] / TIMA1_C0N [6] 52 – – - - - Standard
18 PB5 UART1_RX [2] / UART3_RTS [3] / TIMA1_C1 [4] / TIMA0_C2N [5] / TIMA1_C1N [6] 53 - - - - - Standard
23 PB6 UART1_TX [2] / SPI1_CS0 [3] / SPI0_CS1 [4] / TIMG8_C0 [5] / UART2_CTS [6] / TIMG6_C0 [7] / TIMA1_C0N [8] 58 20 - - - - Standard
24 PB7 UART1_RX [2] / SPI1_POCI [3] / SPI0_CS2 [4] / TIMG8_C1 [5] / UART2_RTS [6] / TIMG6_C1 [7] /TIMA1_C1N [8] 59 21 - - - - Standard
25 PB8 UART1_CTS [2] / SPI1_PICO [3] / TIMA0_C0 [4] / COMP1_OUT [5] 60 22 - - - - Standard
26 PB9 UART1_RTS [2] / SPI1_SCK [3] / TIMA0_C1 [4] / TIMA0_C0N [5] 61 23 - - - - Standard
27 PB10 TIMG0_C0 [2] / TIMG8_C0 [3] / COMP1_OUT [4] / TIMG6_C0 [5] 62 - - - - - Standard
28 PB11 TIMG0_C1 [2] / TIMG8_C1 [3] / CLK_OUT [4] / TIMG6_C1 [5] 63 - - - - - Standard
29 PB12 UART3_TX [2] / TIMA0_C2 [3] / TIMA_FAL1 [4] / TIMA0_C1 [5] 64 - - - - - Standard
30 PB13 UART3_RX [2] / TIMA0_C3 [3] / TIMG12_C0 [4] / TIMA0_C1N [5] 1 - - - - - Standard
31 PB14 SPI1_CS3 [2] / SPI1_POCI [3] / SPI0_CS3 [4] / TIMG12_C1 [5] / TIMG8_IDX [6] / TIMA0_C0 [7] 2 24 - - - - Standard
32 PB15 UART2_TX [2] / SPI1_PICO [3] / UART3_CTS [4] / TIMG8_C0 [5] / TIMG7_C0 [6] 3 25 - - - - Standard
33 PB16 UART2_RX [2] / SPI1_SCK [3] / UART3_RTS [4] / TIMG8_C1 [5] / TIMG7_C1 [6] 4 26 - - - - Standard
43 PB17 A1_4 / COMP1_IN2- UART2_TX [2] / SPI0_PICO [3] / SPI1_CS1 [4] / TIMA1_C0 [5] / TIMA0_C2 [6] 14 36 - - - - Standard
44 PB18 A1_5 / COMP1_IN2+ UART2_RX [2] / SPI0_SCK [3] / SPI1_CS2 [4] / TIMA1_C1 [5] / TIMA0_C2N [6] 15 37 - - - - Standard
45 PB19 A1_6 / COMP2_IN1+ / OPA1_IN0+ COMP2_OUT [2] / SPI0_POCI [3] / TIMG8_C1 [4] / UART0_CTS [5] / TIMG7_C1 [6] 16 38 - - - A1 Standard
48 PB20 A0_6 / OPA1_IN0- SPI0_CS2 [2] / SPI1_CS0 [3] / TIMA0_C2 [4] / TIMG12_C0 [5] / TIMA_FAL1 [6] / TIMA0_C1 [7] / TIMA1_C1N [8] 19 41 - - - - Standard
49 PB21 COMP2_IN0+ SPI1_POCI [2] / TIMG8_C0 [3] 20 - - - - - Standard
50 PB22 COMP2_IN0- SPI1_PICO [2] / TIMG8_C1 [3] 21 - - - - - Standard
51 PB23 SPI1_SCK [2] / COMP0_OUT [3] / TIMA_FAL0 [4] 22 - - - - B2 Standard
52 PB24 A0_5 / COMP1_IN1+ SPI0_CS3 [2] / SPI0_CS1 [3] / TIMA0_C3 [4] / TIMG12_C1 [5] / TIMA0_C1N [6] / TIMA1_C0N [7] 23 42 - - - - Standard
56 PB25 A0_4 UART0_CTS [2] / SPI0_CS0 [3] / TIMA_FAL2 [4] 27 - - - - - Standard
57 PB26 COMP1_IN0+ UART0_RTS [2] / SPI0_CS1 [3] / TIMA0_C3 [4] / TIMG6_C0 [5] 28 - - - - - Standard
58 PB27 COMP1_IN0- COMP2_OUT [2] / SPI1_CS1 [3] / TIMA0_C3N [4] / TIMG6_C1 [5] / TIMA1_C1 [6] 29 - - - - - Standard
(1) Set PINCM.PF and PINCM.PC in IOMUX to 0 for analog functions (for example, OPA inputs/outputs or COMP inputs). Each digital I/O on a device is mapped to a specific Pin Control Management register (PINCMx) that lets users configure the desired pin function using the PINCM.PF control bits.
(2) Standard with Wake allows the I/O to wake up the device from the lowest low-power mode of SHUTDOWN. All I/O can be configured to wakeup the MCU from higher low-power modes. See section GPIO FastWake in the MSPM0 G-Series 80MHz Microcontrollers Technical Reference Manual for details.
Table 6-2 Digital IO Features by IO Type
IO STRUCTURE INVERSION CONTROL DRIVE STRENGTH CONTROL HYSTERESIS CONTROL PULLUP RESISTOR PULLDOWN RESISTOR WAKEUP LOGIC
Standard-drive Y Y Y
Standard-drive with wake(1) Y Y Y Y
High-drive Y Y Y Y Y
High-speed Y Y Y Y
5V-tolerant open drain Y Y Y Y
(1) Standard with Wake allows the I/O to wake up the device from the lowest low-power mode of SHUTDOWN. All I/O can be configured to wakeup the MCU from higher low-power modes. See section GPIO FastWake in the MSPM0 G-Series 80MHz Microcontrollers Technical Reference Manual for details.

6.3 Signal Descriptions

Table 6-3 Signal Descriptions
FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION
64 PM 48 PT, RGZ 32 RHB 28 DGS28 24 VQFN 28 WCSP
ADC A0_0 31 47 31 2 – C3 I ADC0 analog input 0
A0_1 30 46 30 1 22 B3 I ADC0 analog input 1
A0_2 26 45 29 28 21 E2 I ADC0 analog input 2
A0_3 25 44 28 27 20 A3 I ADC0 analog input 3
A0_4 27 – – – – – I ADC0 analog input 4
A0_5 23 42 – – – – I ADC0 analog input 5
A0_6 19 41 – – – – I ADC0 analog input 6
A0_7 18 40 26 25 18 C2 I ADC0 analog input 7
A0_12 7 29 18 17 – - I ADC0 analog input 12
A1_0 8 30 19 18 11 F1 I ADC1 analog input 0
A1_1 9 31 20 19 12 E1 I ADC1 analog input 1
A1_2 10 32 21 20 13 - I ADC1 analog input 2
A1_3 11 33 22 21 14 B1 I ADC1 analog input 3
A1_4 14 36 – – – – I ADC1 analog input 4
A1_5 15 37 – – – – I ADC1 analog input 5
A1_6 16 38 – – – A1 I ADC1 analog input 6
A1_7 17 39 25 24 17 D2 I ADC1 analog input 7
BSL BSL_invoke 11 33 22 21 14 B1 I Input pin used to invoke bootloader
BSL (I2C) BSLSCL 34 2 2 5 1 E3 I/O Default I2C BSL clock
BSLSDA 33 1 1 4 24 D3 I/O Default I2C BSL data
BSL (UART) BSLRX 57 19 15 16 10 G2 I Default UART BSL receive
BSLTX 56 18 14 15 9 G1 O Default UART BSL transmit
Clock CLK_OUT 7
18
39
49
55
56
63		 5
13
17
18
29
40		 11
13
14
18
26		 14
15
17
25		 8
9
18		 F2
G1

C2		 O Configurable clock output
HFCLK_IN 46 12 10 13 – G3 I Digital high-frequency clock input
HFXIN 45 11 9 12 – F3 I Input for high-frequency crystal oscillator HFXT
HFXOUT 46 12 10 13 – G3 O Output for high-frequency crystal oscillator HFXT
LFCLK_IN 44 10 8 11 7 G4 I Digital low-frequency clock input
LFXIN 43 9 7 10 – F4 I Input for low-frequency crystal oscillator LFXT
LFXOUT 44 10 8 11 7 G4 O Output of low-frequency crystal oscillator LFXT
ROSC 42 8 6 9 5 E4 I External resistor used for improving oscillator accuracy
Comparator COMP0_IN0- 31 47 31 2 – C3 I Comparator 0 inverting input 0
COMP0_IN0+ 30 46 30 1 22 B3 I Comparator 0 noninverting input 0
COMP0_IN1- 10 32 21 20 13 - I Comparator 0 inverting input 1
COMP0_IN1+ 11 33 22 21 14 B1 I Comparator 0 noninverting input 1
COMP0_IN2- 6 28 17 – – - I Comparator 0 inverting input 2
COMP0_IN2+ 7 29 18 17 – - I Comparator 0 noninverting input 2
COMP0_IN3+ 8 30 19 18 11 F1 I Comparator 0 noninverting input 3
COMP0_OUT 22
49
57		 13
19		 11
15		 16 10 G2
B2		 O Comparator 0 output
COMP1_IN0- 29 – – – – - I Comparator 1 inverting input 0
COMP1_IN0+ 28 – – – – - I Comparator 1 noninverting input 0
COMP1_IN1- 24 43 27 26 19 A2 I Comparator 1 inverting input 1
COMP1_IN1+ 23 42 – – – - I Comparator 1 noninverting input 1
COMP1_IN2- 14 36 – – – - I Comparator 1 inverting input 2
COMP1_IN3+ 8 30 19 18 11 F1 I Comparator 1 noninverting input 3
COMP1_OUT 43
60
62		 9
22		 7 10 6 F4 O Comparator 1 output
COMP2_IN0- 21 – – – – - I Comparator 2 inverting input 0
COMP2_IN0+ 20 – – – – - I Comparator 2 noninverting input 0
COMP2_IN1- 17 39 25 24 17 D2 I Comparator 2 inverting input 1
COMP2_IN1+ 16 38 – – – A1 I Comparator 2 noninverting input 1
COMP2_OUT 9
16
29		 31
38		 20 19 12 E1 O Comparator 2 output
DAC DAC_OUT 8 30 19 18 11 F1 O DAC output
Debug SWCLK 13 35 24 23 16 D1 I Serial wire debug input clock
SWDIO 12 34 23 22 15 C1 I/O Serial wire debug data input/output
FCC FCC_IN 5
9
33
45		 1
11
27
31		 1
9
16
20		 4
12
19		 12
24		 D3
F3
E1		 I Frequency clock counter input
General-Purpose Amplifier GPAMP_IN+ 30 46 30 1 22 B3 I GPAMP noninverting terminal input
GPAMP_IN- 11 33 22 21 14 B1 I GPAMP inverting terminal input
GPAMP_OUT 18 40 26 25 18 C2 O GPAMP output
GPIO PA0 33 1 1 4 24 D3 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA1 34 2 2 5 1 E3 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA2 42 8 6 9 5 E4 I/O General-purpose digital I/O
PA3 43 9 7 10 6 F4 I/O General-purpose digital I/O
PA4 44 10 8 11 7 G4 I/O General-purpose digital I/O
PA5 45 11 9 12 – F3 I/O General-purpose digital I/O
PA6 46 12 10 13 – G3 I/O General-purpose digital I/O
PA7 49 13 11 – – – I/O General-purpose digital I/O
PA8 54 16 12 – – – I/O General-purpose digital I/O
PA9 55 17 13 14 8 F2 I/O General-purpose digital I/O
PA10 56 18 14 15 9 G1 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA11 57 19 15 16 10 G2 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA12 5 27 16 – – – I/O General-purpose digital I/O
PA13 6 28 17 – – – I/O General-purpose digital I/O
PA14 7 29 18 17 – – I/O General-purpose digital I/O
PA15 8 30 19 18 11 F1 I/O General-purpose digital I/O
PA16 9 31 20 19 12 E1 I/O General-purpose digital I/O
PA17 10 32 21 20 13 – I/O General-purpose digital I/O with wake up from SHUTDOWN
PA18 11 33 22 21 14 B1 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA19 12 34 23 22 15 C1 I/O General-purpose digital I/O
PA20 13 35 24 23 16 D1 I/O General-purpose digital I/O
PA21 17 39 25 24 17 D2 I/O General-purpose digital I/O
PA22 18 40 26 25 18 C2 I/O General-purpose digital I/O
PA23 24 43 27 26 19 A2 I/O General-purpose digital I/O
PA24 25 44 28 27 20 A3 I/O General-purpose digital I/O
PA25 26 45 29 28 21 E2 I/O General-purpose digital I/O
PA26 30 46 30 1 22 B3 I/O General-purpose digital I/O
PA27 31 47 31 2 – C3 I/O General-purpose digital I/O
PA28 35 3 – – – – I/O General-purpose digital I/O with wake up from SHUTDOWN
PA29 36 – – – – – I/O General-purpose digital I/O
PA30 37 – – – – – I/O General-purpose digital I/O
PA31 39 5 – – – – I/O General-purpose digital I/O with wake up from SHUTDOWN
GPIO PB0 47 – – – – – I/O General-purpose digital I/O
PB1 48 – – – – – I/O General-purpose digital I/O
PB2 50 14 – – – – I/O General-purpose digital I/O
PB3 51 15 – – – – I/O General-purpose digital I/O
PB4 52 – – – – – I/O General-purpose digital I/O
PB5 53 – – – – – I/O General-purpose digital I/O
PB6 58 20 – – – – I/O General-purpose digital I/O
PB7 59 21 – – – – I/O General-purpose digital I/O
PB8 60 22 – – – – I/O General-purpose digital I/O
PB9 61 23 – – – – I/O General-purpose digital I/O
PB10 62 – – – – – I/O General-purpose digital I/O
PB11 63 – – – – – I/O General-purpose digital I/O
PB12 64 – – – – – I/O General-purpose digital I/O
PB13 1 – – – – – I/O General-purpose digital I/O
PB14 2 24 – – – – I/O General-purpose digital I/O
PB15 3 25 – – – – I/O General-purpose digital I/O
PB16 4 26 – – – – I/O General-purpose digital I/O
PB17 14 36 – – – – I/O General-purpose digital I/O
PB18 15 37 – – – – I/O General-purpose digital I/O
PB19 16 38 – – – A1 I/O General-purpose digital I/O
PB20 19 41 – – – – I/O General-purpose digital I/O
PB21 20 – – – – – I/O General-purpose digital I/O
PB22 21 – – – – – I/O General-purpose digital I/O
PB23 22 – – – – B2 I/O General-purpose digital I/O
PB24 23 42 – – – – I/O General-purpose digital I/O
PB25 27 – – – – – I/O General-purpose digital I/O
PB26 28 – – – – – I/O General-purpose digital I/O
PB27 29 – – – – – I/O General-purpose digital I/O
I2C I2C0_SCL 34
39
57		 2
5
19		 2
15		 5
16		 1
10		 E3
G2		 I/O I2C0 serial clock
I2C0_SDA 33
35
56		 1
3
18		 1
14		 4
15		 9
24		 D3
G1		 I/O I2C0 serial data
I2C1_SCL 8
10
36
44
50
57		 10
14
19
30
32		 8
15
19
21		 11
16
18
20		 7
10
11
13		 G4
G2
F1		 I/O I2C1 serial clock
I2C1_SDA 9
11
37
43
51
56		 9
15
18
31
33		 7
14
20
22		 10
15
19
21		 6
9
12
14		 F4
G1
E1
B1		 I/O I2C1 serial data
Operational Amplifier with Chopping (Zero-Drift Op-Amp) OPA0_IN0+ 30 46 30 1 22 B3 I OPA0 noninverting terminal input 0
OPA0_IN1+ 26 45 29 28 21 E2 I OPA0 noninverting terminal input 1
OPA0_IN2+ 8 30 19 18 11 F1 I OPA0 noninverting terminal input 2
OPA0_IN0- 31 47 31 2 – C3 I OPA0 inverting terminal input 0
OPA0_IN1- 25 44 28 27 20 A3 I OPA0 inverting terminal input 1
OPA0_OUT 18 40 26 25 18 C2 O OPA0 output
OPA1_IN0+ 16 38 – – – A1 I OPA1 noninverting terminal input 0
OPA1_IN1+ 11 33 22 21 14 B1 I OPA1 noninverting terminal input 1
OPA1_IN2+ 8 30 19 18 11 F1 I OPA1 noninverting terminal input 2
OPA1_IN0- 19 41 – – – – I OPA1 inverting terminal input 0
OPA1_IN1- 10 32 21 20 13 – I OPA1 inverting terminal input 1
OPA1_OUT 9 31 20 19 12 E1 O OPA1 output
Power VSS 41 7 5 8 4 D4 P Ground supply
VDD 40 6 4 7 3 C4 P Power supply
VCORE 32 48 32 3 23 A4 P Regulated core power supply output
QFN Pad – Pad Pad – Pad – P QFN package exposed thermal pad. TI recommends connection to VSS.
RTC RTC_OUT 31
55		 17
47		 13
31		 2
14		 8 C3
F2		 O RTC clock output
SPI SPI0_CS0 27
42
54		 8
16		 6
12		 9 5 E4 I/O SPI0 chip-select 0
SPI0_CS1 23
28
43
58		 9
20
42		 7 10 6 F4 I/O SPI0 chip-select 1
SPI0_CS2 19
25
59		 21
41
44		 28 27 20 A3 I/O SPI0 chip-select 2
SPI0_CS3 2
23
24		 24
42
43		 27 26 19 A2 I/O SPI0 chip-select 3
SPI0_SCK 5
15
46
57		 12
19
27
37		 10
15
16		 13
16		 10 G3
G2		 I/O SPI0 clock signal input – SPI peripheral mode
Clock signal output – SPI controller mode
SPI0_POCI 6
16
44
56		 10
18
28
38		 8
14
17		 11
15		 7
9		 G4
G1
A1		 I/O SPI0 controller in/peripheral out
SPI0_PICO 7
14
45
55		 11
17
29
36		 9
13
18		 12
14
17		 8 F3
F2		 I/O SPI0 controller out/peripheral in
SPI1_CS0 19
30
42
58		 8
20
41
46		 6
30		 1
9		 5
22		 B3
E4		 I/O SPI1 chip-select 0
SPI1_CS1 14
29
31		 36
47		 31 2 – C3 I/O SPI1 chip-select 1
SPI1_CS2 8
15
47		 30
37		 19 18 11 F1 I/O SPI1 chip-select 2
SPI1_CS3 2
26
48		 24
45		 29 28 21 E2 I/O SPI1 chip-select 3
SPI1_SCK 4
10
22
61		 23
26
32		 21 20 13 B2 I/O SPI1 clock signal input – SPI peripheral mode
Clock signal output – SPI controller mode
SPI1_POCI 2
9
20
59		 21
24
31		 20 19 12 E1 I/O SPI1 controller in/peripheral out
SPI1_PICO 3
11
21
60		 22
25
33		 22 21 14 B1 I/O SPI1 controller out/peripheral in
System NRST 38 4 3 6 2 B4 I Reset input active low
Timer TIMG0_C0 5
24
45
62		 11
27
43		 9
16
27		 12
26		 19 F3
A2		 I/O General purpose timer 0 CCR0 capture input or compare output
TIMG0_C1 6
25
46
63		 12
28
44		 10
17
28		 13
27		 20 G3
A3		 I/O General purpose timer 0 CCR1 capture input or compare output
TIMG6_C0 17
28
36
45
50
58
62		 11
14
20
39		 9
25		 12
24		 17 F3
D2		 I/O General purpose timer 6 CCR0 capture input or compare output
TIMG6_C1 18
29
37
46
51
59
63		 12
15
21
40		 10
26		 13
25		 18 G3
C2		 I/O General purpose timer 6 CCR1 capture input or compare output
TIMG7_C0 3
10
24
30
35
43		 3
9
25
32
43
46		 7
21
27
30		 1
10
20
26		 6
13
19
22		 B3
F4
A2		 I/O General purpose timer 7 CCR1 capture input or compare output
TIMG7_C1 4
11
16
25
31
39
42
44
49		 5
8
10
13
26
33
38
44
47		 6
8
11
22
28
31		 2
9
11
21
27		 5
7
14
20		 C3
E4
G4
B1
A3
A1		 I/O General purpose timer 7 CCR1 capture input or compare output
TIMG8_C0 3
17
20
24
30
34
36
43
45
49
58
62		 2
9
11
13
20
25
39
43
46		 2
7
9
11
25
27
30		 1
5
10
12
24
26		 1
6
17
19
22		 B3
E3
F4
F3
D2
A2		 I/O General purpose timer 8 CCR0 capture input or compare output
Timer (continued) TIMG8_C1 4
16
18
21
31
33
37
42
44
46
59
63		 1
8
10
12
21
26
38
40
47		 1
6
8
10
26
31		 2
4
9
11
13
25		 5
7
18
24		 C3
D3
E4
G4
G3
C2
A1		 I/O General purpose timer 8 CCR1 capture input or compare output
TIMG8_IDX 2
8
34
49		 2
13
24
30		 2
11
19		 5
18		 1
11		 E3
F1		 I General purpose timer 8 quadrature encoder index pulse input
TIMG12_C0 1
7
19
56		 18
29
41		 14
18		 15
17		 9 G1 I/O 32-bit general purpose timer 0 CCR0 capture input or compare output
TIMG12_C1 2
23
26
39		 5
24
42
45		 29 28 21 E2 I/O 32-bit general purpose timer 0 CCR1 capture input or compare output
TIMA0_C0 2
17
33
54
60		 1
16
22
24
39		 1
12
25		 4
24		 17
24		 D3
D2		 I/O Advanced control timer 0 CCR0 capture input/compare output
TIMA0_C0N 18
55
61		 17
23
40		 13
26		 14
25		 8
18		 F2
C2		 I/O Advanced control timer 0 CCR0 compare output (inverting)
TIMA0_C1 18
34
43
49
55
61
64		 2
9
13
17
23
41		 2
7
11
13
26		 5
10
14
25		 1
6
8
18		 E3
F4
F2
C2		 I/O Advanced control timer 0 CCR1 capture input or compare output
TIMA0_C1N 1
19
23
26
44
55		 10
17
42
45		 8
13
29		 11
14
28		 7
21		 G4
E2		 I/O Advanced control timer 0 CCR1 compare output (inverting)
Timer (continued) TIMA0_C2 8
14
19
43
47
49
52
56
64		 9
13
18
30
36
41		 7
11
14
19		 10
15
18		 6
9
11		 F4
G1
F1		 I/O Advanced control timer 0 CCR2 capture input or compare output
TIMA0_C2N 9
15
46
48
53
57		 12
19
31
37		 10
15
20		 13
16
19		 10
12		 G3
G2
E1		 I/O Advanced control timer 0 CCR2 compare output (inverting)
TIMA0_C3 1
5
10
23
24
26
28
35
44
50		 3
10
14
27
32
42
43
45		 8
16
21
27
29		 11
20
26
28		 7
13
19
21		 G4
A2
E2		 I/O Advanced control timer 0 CCR3 capture input or compare output
TIMA0_C3N 6
11
25
29
39
51		 5
15
28
33
44		 17
22
28		 21
27		 14
20		 B1
A3		 I/O Advanced control timer 0 CCR3 compare output (inverting)
TIMA1_C0 8
10
14
28
35
47
50
52
56		 3
14
18
30
32
36		 14
19
21		 15
18
20		 9
11
13		 G1
F1		 I/O Advanced control timer 1 CCR0 capture input or compare output
TIMA1_C0N 8
23
52
54
58		 16
20
30
42		 12
19		 18 11 F1 I/O Advanced control timer 0 CCR3 compare output (inverting)
TIMA1_C1 9
11
15
25
29
39
48
51
53
57		 5
15
19
31
33
37
44		 15
20
22
28		 16
19
21
27		 10
12
14
20		 G2
E1
B1
A3		 I/O Advanced control timer 1 CCR1 capture input or compare output
Timer (continued) TIMA1_C1N 9
19
53
55
59		 17
21
31
41		 13
20		 14
19		 8
12		 F2
E1		 I/O Advanced control timer 1 CCR1 compare output (inverting)
TIMA_FAL0 22
30
35
46		 3
12
46		 10
30		 1
13		 22 B3
G3
B2		 I Advanced control timer 0 fault handling input
TIMA_FAL1 19
33
45
64		 1
11
41		 1
9		 4
12		 24 D3
F3		 I Advanced control timer 1 fault handling input
TIMA_FAL2 27
31
34		 2
47		 2
31		 2
5		 1 C3
E3		 I Advanced control timer 2 fault handling input
UART UART0_TX 33
35
47
56		 1
3
18		 1
14		 4
15		 9
24		 D3
G1		 O UART0 transmit data
UART0_RX 34
39
48
57		 2
5
19		 2
15		 5
16		 1
10		 E3
G2		 I UART0 receive data
UART0_CTS 7
16
27
55		 17
29
38		 13
18		 14
17		 8 F2
A1		 I UART0 "clear to send" flow control input
UART0_RTS 8
28
54		 16
30		 12
19		 18 11 F1 O UART0 "request to send" flow control output
UART1_TX 10
52
54
58		 16
20
32		 12
21		 20 13 - O UART1 transmit data
UART1_RX 11
53
55
59		 17
21
33		 13
22		 14
21		 8
14		 F2
B1		 I UART1 receive data
UART1_CTS 17
50
60		 14
22
39		 25 24 17 D2 I UART1 "clear to send" flow control input
UART1_RTS 18
51
61		 15
23
40		 26 25 18 C2 O UART1 "request to send" flow control output
UART2_TX 3
14
17
24		 25
36
39
43		 25
27		 24
26		 17
19		 D2
A2		 O UART2 transmit data
UART2_RX 4
15
18
25		 26
37
40
44		 26
28		 25
27		 18
20		 C2
A3		 I UART2 receive data
UART2_CTS 37
43
50
58		 9
14
20		 7 10 6 F4 I UART2 "clear to send" flow control input
UART2_RTS 36
44
51
59		 10
15
21		 8 11 7 G4 O UART2 "request to send" flow control output
UART (continued) UART3_TX 7
30
50
64		 14
29
46		 18
30		 1
17		 22 B3 O UART3 transmit data
UART3_RX 1
6
26
51		 15
28
45		 17
29		 28 21 E2 I UART3 receive data
UART3_CTS 3
5
24
52		 25
27
43		 16
27		 26 19 A2 I UART3 "clear to send" flow control input
UART3_RTS 4
6
25
53		 26
28
44		 17
28		 27 20 A3 O UART3 "request to send" flow control output
Voltage Reference (3) VREF+ 24 43 27 26 19 A2 I/O Voltage reference (VREF) power supply; external reference input or internal reference output
VREF- 17 39 25 24 17 D2 I/O Voltage reference (VREF) ground supply; external reference input or internal reference output
(1) – = not available
(2) I = input, O = output, I/O = input or output, P = power
(3) When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source

 
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