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PGA302 Sensor Signal Conditioner With 0V to 5V Ratiometric Output
SLDS216B
December 2017 – February 2025
PGA302
PRODUCTION DATA
CONTENTS
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PGA302 Sensor Signal Conditioner With 0V to 5V Ratiometric Output
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Overvoltage and Reverse Voltage Protection
5.6
Linear Regulators
5.7
Internal Reference
5.8
Internal Oscillator
5.9
Bridge Sensor Supply
5.10
Temperature Sensor Supply
5.11
Bridge Offset Cancel
5.12
P Gain and T Gain Input Amplifiers (Chopper Stabilized)
5.13
Analog-to-Digital Converter
5.14
Internal Temperature Sensor
5.15
Bridge Current Measurement
5.16
One Wire Interface
5.17
DAC Output
5.18
DAC Gain for DAC Output
5.19
Non-Volatile Memory
5.20
Diagnostics - PGA30x
5.21
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Overvoltage and Reverse Voltage Protection
6.3.2
Linear Regulators
6.3.3
Internal Reference
6.3.4
Internal Oscillator
6.3.5
VBRGP and VBRGN Supply for Resistive Bridge
6.3.6
ITEMP Supply for Temperature Sensor
6.3.7
P Gain
6.3.8
T Gain
6.3.9
Bridge Offset Cancel
6.3.10
Analog-to-Digital Converter
6.3.10.1
Sigma Delta Modulator for ADC
6.3.10.2
Decimation Filter for ADC
6.3.10.3
Internal Temperature Sensor ADC Conversion
6.3.10.4
ADC Scan Mode
6.3.10.4.1
P-T Multiplexer Timing in Auto Scan Mode
6.3.11
Internal Temperature Sensor
6.3.12
Bridge Current Measurement
6.3.13
Digital Interface
6.3.14
OWI
6.3.14.1
Overview of OWI Interface
6.3.14.2
Activating and Deactivating the OWI Interface
6.3.14.2.1
Activating OWI Communication
6.3.14.2.2
Deactivating OWI Communication
6.3.14.3
OWI Protocol
6.3.14.3.1
OWI Frame Structure
6.3.14.3.1.1
Standard field structure:
6.3.14.3.1.2
Frame Structure
6.3.14.3.1.3
Sync Field
6.3.14.3.1.4
Command Field
6.3.14.3.1.5
Data Field(s)
6.3.14.3.2
OWI Commands
6.3.14.3.2.1
OWI Write Command
6.3.14.3.2.2
OWI Read Initialization Command
6.3.14.3.2.3
OWI Read Response Command
6.3.14.3.2.4
OWI Burst Write Command (EEPROM Cache Access)
6.3.14.3.2.5
OWI Burst Read Command (EEPROM Cache Access)
6.3.14.3.3
OWI Operations
6.3.14.3.3.1
Write Operation
6.3.14.3.3.2
Read Operation
6.3.14.3.3.3
EEPROM Burst Write
6.3.14.3.3.4
EEPROM Burst Read
6.3.14.4
OWI Communication Error Status
6.3.15
I2C Interface
6.3.15.1
Overview of I2C Interface
6.3.15.2
I2C Interface Protocol
6.3.15.3
Clocking Details of I2C Interface
6.3.16
DAC Output
6.3.17
DAC Gain for DAC Output
6.3.17.1
Connecting DAC Output to DAC GAIN Input
6.3.18
Memory
6.3.18.1
EEPROM Memory
6.3.18.1.1
EEPROM Cache
6.3.18.1.2
EEPROM Programming Procedure
6.3.18.1.3
EEPROM Programming Current
6.3.18.1.4
CRC
6.3.19
Diagnostics
6.3.19.1
Power Supply Diagnostics
6.3.19.2
Sensor Connectivity/Gain Input Faults
6.3.19.3
Gain Output Diagnostics
6.3.19.4
PGA302 Harness Open Wire Diagnostics
6.3.19.5
EEPROM CRC and TRIM Error
6.3.20
Digital Compensation and Filter
6.3.20.1
Digital Gain and Offset
6.3.20.2
TC and NL Correction
6.3.20.3
Clamping
6.3.20.4
Filter
6.3.21
Revision ID
6.4
Device Functional Modes
7
Register Maps
7.1
Programmer's Model
7.1.1
Memory Map
7.1.2
Control and Status Registers
7.1.2.1
MICRO_INTERFACE_CONTROL (DI Page Address = 0x0) (DI Page Offset = 0x0C)
7.1.2.2
PSMON1 (M0 Address= 0x40000558) (DI Page Address = 0x2) (DI Page Offset = 0x58)
7.1.2.3
AFEDIAG (M0 Address= 0x4000055A) (DI Page Address = 0x2) (DI Page Offset = 0x5A)
7.1.2.4
P_GAIN_SELECT (DI Page Address = 0x2) (DI Page Offset = 0x47)
7.1.2.5
T_GAIN_SELECT (DI Page Address = 0x2) (DI Page Offset = 0x48)
7.1.2.6
TEMP_CTRL (DI Page Address = 0x2) (DI Page Offset = 0x4C)
7.1.2.7
OFFSET_CANCEL (DI Page Address = 0x2) (DI Page Offset = 0x4E)
7.1.2.8
PADC_DATA1 (DI Page Address = 0x0) (DI Page Offset = 0x10)
7.1.2.9
PADC_DATA2 (DI Page Address = 0x0) (DI Page Offset = 0x11)
7.1.2.10
TADC_DATA1 (DI Page Address = 0x0) (DI Page Offset = 0x14)
7.1.2.11
TADC_DATA2 (DI Page Address = 0x0) (DI Page Offset = 0x15)
7.1.2.12
DAC_REG0_1 (DI Page Address = 0x2) (DI Page Offset = 0x30)
7.1.2.13
DAC_REG0_2 (DI Page Address = 0x2) (DI Page Offset = 0x31)
7.1.2.14
OP_STAGE_CTRL (DI Page Address = 0x2) (DI Page Offset = 0x3B)
7.1.2.15
EEPROM_ARRAY (DI Page Address = 0x5) (DI Page Offset = 0x00 - 0x7F)
7.1.2.16
EEPROM_CACHE_BYTE0 (DI Page Address = 0x5) (DI Page Offset = 0x80)
7.1.2.17
EEPROM_CACHE_BYTE1 (DI Page Address = 0x5) (DI Page Offset = 0x81)
7.1.2.18
EEPROM_PAGE_ADDRESS (DI Page Address = 0x5) (DI Page Offset = 0x82)
7.1.2.19
EEPROM_CTRL (DI Page Address = 0x5) (DI Page Offset = 0x83)
7.1.2.20
EEPROM_CRC (DI Page Address = 0x5) (DI Page Offset = 0x84)
7.1.2.21
EEPROM_STATUS (DI Page Address = 0x5) (DI Page Offset = 0x85)
7.1.2.22
EEPROM_CRC_STATUS (DI Page Address = 0x5) (DI Page Offset = 0x86)
7.1.2.23
EEPROM_CRC_VALUE (DI Page Address = 0x5) (DI Page Offset = 0x87)
7.1.2.24
H0 (EEPROM Address= 0x40000000)
7.1.2.25
H1 (EEPROM Address= 0x40000002)
7.1.2.26
H2 (EEPROM Address= 0x40000004)
7.1.2.27
H3 (EEPROM Address= 0x40000006)
7.1.2.28
G0 (EEPROM Address= 0x40000008)
7.1.2.29
G1 (EEPROM Address= 0x4000000A)
7.1.2.30
G2 (EEPROM Address= 0x4000000C)
7.1.2.31
G3 (EEPROM Address= 0x4000000E)
7.1.2.32
N0 (EEPROM Address= 0x40000010)
7.1.2.33
N1 (EEPROM Address= 0x40000012)
7.1.2.34
N2 (EEPROM Address= 0x40000014)
7.1.2.35
N3 (EEPROM Address= 0x40000016)
7.1.2.36
M0 (EEPROM Address= 0x40000018)
7.1.2.37
M1 (EEPROM Address= 0x4000001A)
7.1.2.38
M2 (EEPROM Address= 0x4000001C)
7.1.2.39
M3 (EEPROM Address= 0x4000001E)
7.1.2.40
PADC_GAIN (EEPROM Address= 0x40000020)
7.1.2.41
TADC_GAIN (EEPROM Address= 0x40000021)
7.1.2.42
PADC_OFFSET (EEPROM Address= 0x40000022)
7.1.2.43
TADC_OFFSET (EEPROM Address= 0x40000024)
7.1.2.44
TEMP_SW_CTRL (EEPROM Address= 0x40000028)
7.1.2.45
DAC_FAULT_MSB (EEPROM Address= 0x4000002A)
7.1.2.46
LPF_A0_MSB (EEPROM Address= 0x4000002B)
7.1.2.47
LPF_A1 (EEPROM Address= 0x4000002C)
7.1.2.48
LPF_A2 (EEPROM Address= 0x4000002E)
7.1.2.49
.LPF_B1 (EEPROM Address= 0x40000030)
7.1.2.50
NORMAL_LOW (EEPROM Address= 0x40000032)
7.1.2.51
NORMAL_HIGH (EEPROM Address= 0x40000034)
7.1.2.52
LOW_CLAMP (EEPROM Address= 0x40000036)
7.1.2.53
HIGH_CLAMP (EEPROM Address= 0x40000038)
7.1.2.54
DIAG_BIT_EN (EEPROM Address= 0x4000003A)
8
Application and Implementation
8.1
Application Information
8.1.1
0-5V Voltage Output
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Application Data
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Receiving Notification of Documentation Updates
9.2
Support Resources
9.3
Trademarks
9.4
Electrostatic Discharge Caution
9.5
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
PW|16
MPDS361A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slds216b_oa
slds216b_pm
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Data Sheet
PGA302
Sensor Signal Conditioner With 0V to 5V Ratiometric Output