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RF430F5978 MSP430™ System-in-Package With Sub-1-GHz Transceiver and 3D LF Wake-up and Transponder Interface
SLAS740A
January 2013 – October 2015
RF430F5978
PRODUCTION DATA.
CONTENTS
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RF430F5978 MSP430™ System-in-Package With Sub-1-GHz Transceiver and 3D LF Wake-up and Transponder Interface
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Device Characteristics
4
Terminal Configuration and Functions
4.1
Pin Diagram
4.2
Signal Descriptions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Active Mode Supply Current Into VCC Excluding External Current
5.5
Typical Characteristics - Active Mode Supply Currents
5.6
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
5.7
Typical Characteristics - Low-Power Mode Supply Currents
5.8
Thermal Resistance Characteristics
5.9
Digital Inputs
5.10
Digital Outputs
5.11
Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
5.12
Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
5.13
Crystal Oscillator, XT1, Low-Frequency Mode
5.14
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
5.15
Internal Reference, Low-Frequency Oscillator (REFO)
5.16
DCO Frequency
5.17
PMM, Brown-Out Reset (BOR)
5.18
PMM, Core Voltage
5.19
PMM, SVS High Side
5.20
PMM, SVM High Side
5.21
PMM, SVS Low Side
5.22
PMM, SVM Low Side
5.23
Wake-up Times From Low-Power Modes and Reset
5.24
Timer_A
5.25
USCI (UART Mode) Clock Frequency
5.26
USCI (UART Mode)
5.27
USCI (SPI Master Mode) Clock Frequency
5.28
USCI (SPI Master Mode)
5.29
USCI (SPI Slave Mode)
5.30
USCI (I2C Mode)
5.31
12-Bit ADC, Power Supply and Input Range Conditions
5.32
12-Bit ADC, Timing Parameters
5.33
12-Bit ADC, Linearity Parameters
5.34
12-Bit ADC, Temperature Sensor and Built-In VMID
5.35
REF, External Reference
5.36
REF, Built-In Reference
5.37
Comparator B
5.38
Flash Memory
5.39
JTAG and Spy-Bi-Wire Interface
5.40
RF1A CC1101 Radio Parameters
5.40.1
RF Crystal Oscillator, XT2
5.40.2
Current Consumption, Reduced-Power Modes
5.40.3
Current Consumption, Receive Mode
5.40.4
Current Consumption, Transmit Mode
5.40.5
Typical TX Current Consumption, 315 MHz
5.40.6
Typical TX Current Consumption, 433 MHz
5.40.7
Typical TX Current Consumption, 868 MHz
5.40.8
Typical TX Current Consumption, 915 MHz
5.40.9
RF Receive, Overall
5.40.10
RF Receive, 315 MHz
5.40.11
RF Receive, 433 MHz
5.40.12
RF Receive, 868 or 915 MHz
5.40.13
Typical Sensitivity, 315 MHz, Sensitivity-Optimized Setting
5.40.14
Typical Sensitivity, 433 MHz, Sensitivity-Optimized Setting
5.40.15
Typical Sensitivity, 868 MHz, Sensitivity-Optimized Setting
5.40.16
Typical Sensitivity, 915 MHz, Sensitivity-Optimized Setting
5.40.17
RF Transmit
5.40.18
Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
5.40.19
Typical Output Power, 315 MHz
5.40.20
Typical Output Power, 433 MHz
5.40.21
Typical Output Power, 868 MHz
5.40.22
Typical Output Power, 915 MHz
5.40.23
Frequency Synthesizer Characteristics
5.40.24
Typical RSSI_offset Values
5.41
3D LF Front-End Parameters
5.41.1
Recommended Operating Conditions
5.41.2
Resonant Circuits - LF Front End
5.41.3
External Antenna Coil - LF Front End
5.41.4
Resonant Circuit Capacitor - LF Front End
5.41.5
Charge Capacitor - LF Front End
5.41.6
LF Wake Receiver Electrical Characteristics
5.41.7
RSSI - LF Wake Receiver Electrical Characteristics
6
Detailed Description
6.1
3D LF Wake Receiver and 3D Transponder Interface
6.1.1
3D LF Front End
6.1.2
EEPROM
6.1.3
Switch Interface
6.2
Sub-1-GHz Radio
6.3
CPU
6.4
Operating Modes
6.5
Interrupt Vector Addresses
6.6
Memory Organization
6.7
Bootloader (BSL)
6.8
JTAG Operation
6.8.1
JTAG Standard Interface
6.8.2
Spy-Bi-Wire Interface
6.9
Flash Memory
6.10
RAM
6.11
Peripherals
6.11.1
Oscillator and System Clock
6.11.2
Power-Management Module (PMM)
6.11.3
Digital I/O
6.11.4
Port Mapping Controller
6.11.5
System (SYS) Module
6.11.6
DMA Controller
6.11.7
Watchdog Timer (WDT_A)
6.11.8
CRC16
6.11.9
Hardware Multiplier
6.11.10
AES128 Accelerator
6.11.11
Universal Serial Communication Interface (USCI)
6.11.12
TA0
6.11.13
TA1
6.11.14
Real-Time Clock (RTC_A)
6.11.15
REF Voltage Reference
6.11.16
Comparator_B
6.11.17
ADC12_A
6.11.18
Embedded Emulation Module (EEM) (S Version)
6.11.19
Peripheral File Map
6.12
Input/Output Schematics
6.12.1
Port P1, P1.0 to P1.4, Input/Output With Schmitt Trigger
6.12.2
Port P1, P1.5 to P1.7, Input/Output With Schmitt Trigger
6.12.3
Port P2, P2.0 to P2.2, Input/Output With Schmitt Trigger
6.12.4
Port P2, P2.4 and P2.5, Input/Output With Schmitt Trigger
6.12.5
Port P3, P3.1 to P3.3, P3.5, and P3.7, Input/Output With Schmitt Trigger
6.12.6
Port P4, P4.0 to P4.2, Input/Output With Schmitt Trigger
6.12.7
Port P5, P5.0, Input/Output With Schmitt Trigger
6.12.8
Port P5, P5.1, Input/Output With Schmitt Trigger
6.12.9
Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
6.12.10
Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
6.13
Device Descriptor Structures
7
Applications, Implementation, and Layout
7.1
Application Circuit
8
Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
8.1.1.1
Getting Started and Next Steps
8.1.2
Device and Development Tool Nomenclature
8.2
Documentation Support
8.2.1
Related Documentation
8.3
Community Resources
8.4
Trademarks
8.5
Electrostatic Discharge Caution
8.6
Export Control Notice
8.7
Glossary
9
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
RGC|64
MPQF125F
Thermal pad, mechanical data (Package|Pins)
RGC|64
QFND004Q
Orderable Information
slas740a_oa
slas740a_pm
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