SCES595N JULY   2004  – July 2017 SN74AUP1G125

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics, TA = 25°C
    6. 6.6  Electrical Characteristics, TA = -40°C to +85°C
    7. 6.7  Switching Characteristics, CL = 5 pF
    8. 6.8  Switching Characteristics, CL = 10 pF
    9. 6.9  Switching Characteristics, CL = 15 pF
    10. 6.10 Switching Characteristics, CL = 30 pF
    11. 6.11 Operating Characteristics
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diodes
      4. 8.3.4 Partial Power Down (Ioff)
      5. 8.3.5 Over-voltage Tolerant Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4 pF Typical at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    < 10% of VCC
  • Input-Disable Feature Allows Floating Input Conditions
  • Ioff Supports Partial-Power-Down Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.6 ns Maximum at 3.3 V

2 Applications

  • Audio Dock: Portable
  • BluRay™ Players and Home Theaters
  • Personal Digital Assistant (PDA)
  • Power: Telecom/Server AC/DC Supply: Single Controller: Analog and Digital
  • Solid-State Drive (SSD): Client and Enterprise
  • TV: LCD/Digital and High-Definition (HDTV)
  • Tablet: Enterprise
  • Wireless Headsets, Keyboards, and Mice

3 Description

The SN74AUP1G125 bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.

To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74AUP1G125DBV SOT-23 (5) 2.90 mm × 1.60 mm
SN74AUP1G125DCK SC70 (5) 2.00 mm × 1.25 mm
SN74AUP1G125DRL SOT (5) 1.60 mm × 1.20 mm
SN74AUP1G125DRY SON (6) 1.45 mm × 1.00 mm
SN74AUP1G125DSF 1.00 mm × 1.00 mm
SN74AUP1G125YFP DSBGA (6) 0.76 mm × 1.16 mm
SN74AUP1G125YZP DSBGA (5) 0.89 mm × 1.39 mm
SN74AUP1G125YZT DSBGA (5) 0.89 mm × 1.39 mm
SN74AUP1G125DPW X2SON (5) 0.80 mm × 0.80 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

SN74AUP1G125 LOGIC_CES595.gif