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SN74AUP2G08 Low-Power Dual 2-Input Positive-AND Gate
SCES681E
January 2008 – April 2024
SN74AUP2G08
PRODUCTION DATA
CONTENTS
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SN74AUP2G08 Low-Power Dual 2-Input Positive-AND Gate
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Resistance Characteristics
5.5
Electrical Characteristics
5.6
Switching Characteristics - CL = 5 pF
5.7
Switching Characteristics - CL = 10 pF
5.8
Switching Characteristics - CL = 15 pF
5.9
Switching Characteristics - CL = 30 pF
5.10
Operating Characteristics
5.11
Typical Characteristics
6
Parameter Measurement Information
6.1
19
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Balanced CMOS Push-Pull Outputs
7.3.2
CMOS Schmitt-Trigger Inputs
7.3.3
Partial Power Down (Ioff)
7.3.4
Standard CMOS Inputs
7.3.5
Clamp Diode Structure
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Power Considerations
8.2.1.2
Input Considerations
8.2.1.3
Output Considerations
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Receiving Notification of Documentation Updates
9.2
Support Resources
9.3
Trademarks
9.4
Electrostatic Discharge Caution
9.5
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
DQE|8
MPSS008B
YFP|8
MXBG057R
RSE|8
MPQF207E
YZP|8
MXBG020L
DCU|8
MPDS050E
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sces681e_oa
sces681e_pm
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SN74AUP2G08 Low-Power Dual 2-Input Positive-AND Gate