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SN74LV4T125-EP Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter
SCLS985
January 2024
SN74LV4T125-EP
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SN74LV4T125-EP Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter
1
1
Features
2
Applications
3
Description
4
Additional Product Selection
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Noise Characteristics
6.8
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Balanced CMOS 3-State Outputs
8.3.2
Clamp Diode Structure
8.3.3
LVxT Enhanced Input Voltage
8.3.3.1
Down Translation
8.3.3.2
Up Translation
8.4
Device Functional Modes
9
Applications and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Receiving Notification of Documentation Updates
10.2
Support Resources
10.3
Trademarks
10.4
Electrostatic Discharge Caution
10.5
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
PW|14
MPDS360A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
scls985_oa
scls985_pm
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