SN74LV8T373-EP Enhanced Product Octal Transparent D-Type Latches with 3-State Outputs
- SCLSA23A August 2024 – October 2024 SN74LV8T373-EP
  
  PRODUCTION DATA

Full reading width

Data Sheet

SN74LV8T373-EP Enhanced Product Octal Transparent D-Type Latches
with 3-State Outputs

1 Features

Wide operating range of 1.65V to 5.5V
5.5V tolerant input pins
Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
- Up translation:
  - 1.2V to 1.8V
  - 1.5V to 2.5V
  - 1.8V to 3.3V
  - 3.3V to 5.0V
- Down translation:
  - 5.0V, 3.3V, 2.5V to 1.8V
  - 5.0V, 3.3V to 2.5V
  - 5.0V to 3.3V
Up to 150Mbps with 5V or 3.3V V_CC
Supports standard function pinout
Latch-up performance exceeds 250mA
per JESD 17
Supports defense and aerospace applications:
- Controlled baseline
- One assembly and test site
- One fabrication site
- Extended product life cycle
- Product traceability

2 Applications

3 Description

The SN74LV8T373-EP device is an octal transparent D-type latch designed for 2V to 5.5V V_CC operation.

The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (V_CC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

Package Information

PART NUMBER	PACKAGE⁽¹⁾	PACKAGE SIZE⁽²⁾	BODY SIZE (NOM)⁽³⁾
SN74LV8T373-EP	PW (TSSOP, 20)	6.5mm × 6.4mm	6.5mm × 4.4mm

(1) For more information, seeMechanical, Packaging, and Orderable Information.

(2) The package size (length × width) is a nominal value and includes pins, where applicable.

(3) The body size (length × width) is a nominal value and does not include pins.

Simplified Logic Diagram (Positive Logic)

4 Pin Configuration and Functions

SN74LV8T373-EP PW Package, 20-Pin TSSOP (Top View)

Figure 4-1 PW Package, 20-Pin TSSOP (Top View)

Table 4-1 Pin Functions

PIN		TYPE	DESCRIPTION
NO.	Name	TYPE	DESCRIPTION
1	OE	I	Output Enable
2	1Q	O	1Q Output
3	1D	I	1D Input
4	2D	I	2D Input
5	2Q	O	2Q Output
6	3Q	O	3Q Output
7	3D	I	3D Input
8	4D	I	4D Input
9	4Q	O	4Q Output
10	GND	—	Ground Pin
11	LE	I	Latch Enable
12	5Q	O	5Q Output
13	5D	I	5D Input
14	6D	I	6D Input
15	6Q	O	6Q Output
16	7Q	O	7Q Output
17	7D	I	7D Input
18	8D	I	8D Input
19	8Q	O	8Q Output
20	V_CC	—	Power Pin

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CC	Supply voltage range		–0.5	7	V
V_I	Input voltage range⁽²⁾		–0.5	7	V
V_O	Voltage range applied to any output in the high-impedance or power-off state⁽²⁾		–0.5	7	V
V_O	Output voltage range⁽²⁾		–0.5	V_CC + 0.5	V
I_IK	Input clamp current	V_I < -0.5V		-20	mA
I_OK	Output clamp current	V_O < -0.5V or V_O > V_{CC +}0.5V		±20	mA
I_O	Continuous output current	V_O = 0 to V_CC		±25	mA
	Continuous output current through V_CC or GND			±75	mA
T_stg	Storage temperature		-65	150	°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

5.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

Spec	Description	Condition	MIN	MAX	UNIT
V_CC	Supply voltage		1.65	5.5	V
V_I	Input voltage		0	5.5	V
V_O	Output voltage		0	V_CC	V
V_IH	High-level input voltage	V_CC = 1.65V to 2V	1.1		V
		V_CC = 2.25V to 2.75V	1.28
		V_CC = 3V to 3.6V	1.45
		V_CC = 4.5V to 5.5V	2
V_IL	Low-Level input voltage	V_CC = 1.65V to 2V		0.5	V
		V_CC = 2.25V to 2.75V		0.65
		V_CC = 3V to 3.6V		0.75
		V_CC = 4.5V to 5.5V		0.85
I_O	Output current	V_CC = 1.6V to 2V		±3	mA
		V_CC = 2.25V to 2.75V		±7
		V_CC = 3.3V to 5.0V		±15
I_O	Output Current	V_CC = 4.5V to 5.5V		±25	mA
Δt/Δv	Input transition rise or fall rate	V_CC = 1.6V to 5.0V		20	ns/V
T_A	Operating free-air temperature		-55	125	°C

5.4 Thermal Information

THERMAL METRIC⁽¹⁾		SN74LV8T373-EP	UNIT
		PW (TSSOP)
		20 PINS
R_θJA	Junction-to-ambient thermal resistance	122.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	64.8	°C/W
R_θJB	Junction-to-board thermal resistance	73.3	°C/W
Ψ_JT	Junction-to-top characterization parameter	19.0	°C/W
Y_JB	Junction-to-board characterization parameter	73.0	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Electrical Characteristics

over operating free-air temperature range; typical ratings measured at T_A = 25°C (unless otherwise noted).

PARAMETER	TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_OH	I_OH = -50 uA	1.65V to 5.5V	V_CC-0.1			V
	I_OH = -2 mA	1.65V to 2V	1.21	1.7⁽¹⁾
	I_OH = -3 mA	2.25V to 2.75V	1.93	2.4⁽¹⁾
	I_OH = -5.5 mA	3V to 3.6V	2.49	3.08⁽¹⁾
	I_OH = -8 mA	4.5V to 5.5V	3.95	4.65⁽¹⁾
V_OL	I_OL= 50 μA	1.65V to 5.5V			0.1	V
	I_OL = 2 mA	1.65V to 2V		0.1⁽¹⁾	0.25
	I_OL = 3 mA	2.25V to 2.75V		0.1⁽¹⁾	0.2
	I_OL = 5.5 mA	3V to 3.6V		0.2⁽¹⁾	0.25
	I_OL= 8 mA	4.5V to 5.5V		0.3⁽¹⁾	0.35
I_I	V_I = 0 V or V_CC	0V to 5.5V			±1	µA
I_CC	V_I = V_CC or GND, I_O = 0	1.65V to 5.5V			10	µA
ΔI_CC	One input at 0.3 V or 3.4 V, other inputs at 0 or V_CC, I_O = 0	5.5V			1.5	mA
ΔI_CC	One input at 0.3 V or 1.1 V, other inputs at 0 or V_CC, I_O = 0	1.8V			20	µA
C_I	V_I = V_CC or GND	5V		2	10	pF
C_O	V_O = V_CC or GND	5V		5		pF
I_OZ	V_O = V_CC or GND and V_CC = 5.5 V	5.5V			±2.5	µA
C_PD⁽²⁾⁽³⁾	C_L = 50 pF, F = 10 MHz	1.65V to 5.5V		105		pF

(1) Typical value at nearest nominal voltage (1.8V, 2.5V, 3.3V, and 5V)

(2) C_PD is used to determine the dynamic power consumption, per channel.

(3) P_D= V_CC²xF_Ix(C_PD+ C_L) where F_I= input frequency, C_L= output load capacitance, V_CC= supply voltage.