SCES219V April   1999  – August 2015 SN74LVC1G32

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, CL = 15 pF
    7. 6.7  Switching Characteristics, 1.8 V and 2.5V
    8. 6.8  Switching Characteristics, 3.3 V and 5 V
    9. 6.9  Operating Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. 14Package Option Addendum
    1. 14.1 Packaging Information
    2. 14.2 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DPW|5
  • DBV|5
  • DSF|6
  • DCK|5
  • DRL|5
  • DRY|6
  • YZP|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Available in the Ultra-Small 0.64 mm2
    Package (DPW) with 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5-V
  • Supports Down Translation to VCC
  • Max tpd of 3.6 ns at 3.3-V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3-V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

2 Applications

  • AV Receiver
  • Blu-ray Player and Home Theater
  • Digital Picture Frame (DPF)
  • Embedded PC
  • IP Phone: Wireless
  • High-Speed Data Acquisition and Generation
  • Motor Control: High-Voltage
  • Optical Networking: Video Over Fiber and EPON
  • Personal Navigation Device (GPS)
  • Portable Media Player
  • Private Branch Exchange (PBX)
  • Server PSU
  • SSD: Internal and External
  • TV: LCD/Digital and High-Definition (HDTV)
  • Telecom Shelter: Power Distribution Unit (PDU), Power Monitoring Unit (PMU), Wireless Battery Monitoring, Remote Electrical Tilt Unit (RET), Remote Radio Unit (RRU), Tower Mounted Amplifier (TMA)
  • Video Conferencing: IP-Based HD
  • Vector Signal Analyzer and Generator
  • WiMAX and Wireless Infrastructure Equipment
  • Wireless Headset, Keyboard, Mouse, and Repeater

3 Description

This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G32 device performs the Boolean function SN74LVC1G32 ineq_ces219.gif in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G32 device is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 × 0.8 mm.

Device Information(1)

DEVICE NAME PACKAGE (PINS) BODY SIZE
SN74LVC1G32DBV SOT-23 (5) 2.90 mm × 2.80 mm
SN74LVC1G32DCK SC70 (5) 2.00mm × 2.10 mm
SN74LVC1G32DRY SON (6) 1.45 mm × 1.00 mm
SN74LVC1G32DSF SON (6) 1.00 mm × 1.00 mm
SN74LVC1G32DPW X2SON (4) 0.80 mm × 0.80 mm
SN74LVC1G32DRL SOT (5) 1.60 mm × 1.60 mm
SN74LVC1G32YZP DSBGA (5) 1.38 mm × 0.88 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.
SN74LVC1G32 ld_ces219.gif

4 Revision History

Changes from U Revision (April 2014) to V Revision

  • Added TJ junction temp spec to Abs Max RatingsGo

Changes from T Revision (March 2014) to U Revision

  • Updated Features, Description, and Device Information table.Go
  • Added Pin Functions table. Go
  • Added Thermal Information table. Go
  • Added Detailed Description section. Go
  • Added Application and Implementation section. Go
  • Added Layout section. Go

Changes from S Revision (July 2013) to T Revision

  • Updated Features.Go
  • Added Applications.Go
  • Added Device Information table.Go
  • Added DPW Package. Go
  • Moved Tstg to Handling Ratings table.Go

Changes from R Revision (June 2013) to S Revision

  • Added parameter values for –40 to 125°C temperature ratings.Go

Changes from Q Revision (November 2012) to R Revision

  • Deleted Ordering Information table.Go