The TLC59116-Q1 is an I2C-Bus controlled 16-channel LED driver that is optimized for red/green/blue/amber (RGBA) color mixing and backlight application. Each LED output has its own 8-bit resolution (256 steps) fixed-frequency individual PWM controller that operates at 97-kHz, with a duty cycle that is adjustable from 0% to 99.6%.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TLC59116-Q1 | TSSOP (28) | 9.70 mm × 4.40 mm |
Changes from * Revision (March 2016) to A Revision
The individual PWM controller allows each LED to be set to a specific brightness value. An additional 8-bit resolution (256 steps) group PWM controller has both a fixed frequency of 190-Hz and an adjustable frequency between 24-Hz to once every 10.73 seconds, with a duty cycle that is adjustable from 0% to 99.6%. The group PWM controller dims or blinks all LEDs with the same value.
Each LED output can be off, on (no PWM control), or set at its individual PWM controller value at both individual and group PWM controller values.
The TLC59116-Q1 operates with a supply voltage range of 3 V to 5.5 V and the outputs are 17 V tolerant. LEDs can be directly connected to the TLC59116-Q1 device outputs.
Software programmable LED Group and three Sub Call I2C-Bus addresses allow all or defined groups of TLC59116-Q1 devices to respond to a common I2C Bus address, allowing for example, all the same color LEDs to be turned on or off at the same time or marquee chasing effect, thus minimizing I2C Bus commands.
Four hardware address pins allow up to 14 devices on the same Bus.
The Software Reset (SWRST) Call allows the master to perform a reset of the TLC59116-Q1 through the I2C Bus, identical to the Power-On Reset (POR) that initializes the registers to their default state causing the outputs to be set high (LED off). This allows an easy and quick way to reconfigure all device registers to the same condition.
PIN | I/O (1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | REXT | I | Input terminal used to connect an external resistor for setting up all output currents |
2 | A0 | I | Address input 0 |
3 | A1 | I | Address input 1 |
4 | A2 | I | Address input 2 |
5 | A3 | I | Address input 3 |
6 | OUT0 | O | Constant current output 0 |
7 | OUT1 | O | Constant current output 1 |
8 | OUT2 | O | Constant current output 2 |
9 | OUT3 | O | Constant current output 3 |
10 | GND | — | Ground |
11 | OUT4 | O | Constant current output 4 |
12 | OUT5 | O | Constant current output 5 |
13 | OUT6 | O | Constant current output 6 |
14 | OUT7 | O | Constant current output 7 |
15 | OUT8 | O | Constant current output 8 |
16 | OUT9 | O | Constant current output 9 |
17 | OUT10 | O | Constant current output 10 |
18 | OUT11 | O | Constant current output 11 |
19 | GND | — | Ground |
20 | OUT12 | O | Constant current output 12 |
21 | OUT13 | O | Constant current output 13 |
22 | OUT14 | O | Constant current output 14 |
23 | OUT15 | O | Constant current output 15 |
24 | GND | — | Ground |
25 | RESET | I | Active-low reset input |
26 | SCL | I | Serial clock input |
27 | SDA | I/O | Serial data input/output |
28 | VCC | — | Power supply |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage | 0 | 7 | V | |
VI | Input voltage | –0.4 | VCC + 0.4 | V | |
VO | Output voltage | –0.5 | 20 | V | |
IO | Output current per channel | 120 | mA | ||
TJ | Junction temperature | –40 | 150 | °C | |
Tstg | Storage temperature | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V |
Charged-device model (CDM), per AEC Q100-011 | ±1500 |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
VCC | Supply voltage | 3 | 5.5 | V | ||
VIH | High-level input voltage | SCL, SDA, RESET, A0, A1, A2, A3 | 0.7 × VCC | VCC | V | |
VIL | Low-level input voltage | SCL, SDA, RESET, A0, A1, A2, A3 | 0 | 0.3 × VCC | V | |
VO | Supply voltage to output pins | OUT0 to OUT15 | 17 | V | ||
IOL | Low-level output current sink | SDA | VCC = 3 V | 20 | mA | |
VCC = 5 V | 30 | |||||
IO | Output current per channel | OUT0 to OUT15 | 5 | 120 | mA | |
TA | Operating free-air temperature | –40 | 105 | °C |
THERMAL METRIC (1) | TLC59116-Q1 | UNIT | |
---|---|---|---|
PW (TSSOP) | |||
28 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 78 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 18.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 36 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 35.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP (1) | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
II | Input / output leakage current | SCL, SDA, A0, A1, A2, A3, RESET | VI = VCC or GND | ±0.3 | μA | |||
Output leakage current | OUT0 to OUT15 | VO = 17 V, TJ = 25°C | 0.5 | μA | ||||
VPOR | Power-on reset voltage | 2.5 | V | |||||
IOL | Low-level output current | SDA | VCC = 3 V, VOL = 0.4 V | 20 | mA | |||
VCC = 5 V, VOL = 0.4 V | 30 | |||||||
IO(1) | Output current 1 | OUT0 to OUT15 | VO = 0.6 V, Rext = 720 Ω, CG = 0.992 (3) | 26 | mA | |||
Output current error | OUT0 to OUT15 | IO = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C | ±10% | |||||
Output channel to channel current error | OUT0 to OUT15 | IO = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C | ±6% | |||||
IO(2) | Output current 2 | OUT0 to OUT15 | VO = 0.8 V, Rext = 360 Ω, CG = 0.992 (3) | 52 | mA | |||
Output current error | OUT0 to OUT15 | IO = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C | ±8% | |||||
Output channel to channel current error | OUT0 to OUT15 | IO = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C | ±6% | |||||
IOUT vs VOUT | Output current vs output voltage regulation | OUT0 to OUT15 | VO = 1 V to 3 V, IO = 26 mA | ±0.1 | %/V | |||
VO = 3 V to 5.5 V, IO = 26 mA to 120 mA | ±1 | |||||||
IOUT,Th1 | Threshold current 1 for error detection | OUT0 to OUT15 | IOUT,target = 26 mA | 0.5 × ITARGET% | ||||
IOUT,Th2 | Threshold current 2 for error detection | OUT0 to OUT15 | IOUT,target = 52 mA | 0.5 × ITARGET% | ||||
IOUT,Th3 | Threshold current 3 for error detection | OUT0 to OUT15 | IOUT,target = 104 mA | 0.5 × ITARGET% | ||||
TSD | Overtemperature shutdown (2) | 150 | 175 | 200 | °C | |||
THYS | Restart hysteresis | 15 | °C | |||||
Ci | Input capacitance | SCL, A0, A1, A2, A3, RESET | VI = VCC or GND | 5 | pF | |||
Cio | Input / output capacitance | SDA | VI = VCC or GND | 8 | pF | |||
ICC | Supply current | VCC = 5.5 V | OUT0 to OUT15 = OFF, Rext = Open | 25 | mA | |||
OUT0 to OUT15 = OFF, Rext = 720 Ω | 29 | |||||||
OUT0 to OUT15 = OFF, Rext = 360 Ω | 32 | |||||||
OUT0 to OUT15 = OFF, Rext = 180 Ω | 37 | |||||||
OUT0 to OUT15 = ON, Rext = 720 Ω | 29 | |||||||
OUT0 to OUT15 = ON, Rext = 360 Ω | 32 | |||||||
OUT0 to OUT15 = ON, Rext = 180 Ω | 37 |
I2C BUS | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
I2C INTERFACE | |||||
fSCL | SCL clock frequency (1) | STANDARD MODE | 0 | 100 | kHz |
FAST MODE | 0 | 400 | |||
FAST MODE PLUS | 0 | 1000 | |||
tBUF | I2C Bus free time between Stop and Start conditions | STANDARD MODE | 4.7 | μs | |
FAST MODE | 1.3 | ||||
FAST MODE PLUS | 0.5 | ||||
tHD;STA | Hold time (repeated) Start condition | STANDARD MODE | 4 | μs | |
FAST MODE | 0.6 | ||||
FAST MODE PLUS | 0.26 | ||||
tSU;STA | Set-up time for a repeated Start condition | STANDARD MODE | 4.7 | μs | |
FAST MODE | 0.6 | ||||
FAST MODE PLUS | 0.26 | ||||
tSU;STO | Set-up time for Stop condition | STANDARD MODE | 4 | μs | |
FAST MODE | 0.6 | ||||
FAST MODE PLUS | 0.26 | ||||
tHD;DAT | Data hold time | STANDARD MODE | 0 | ns | |
FAST MODE | 0 | ||||
FAST MODE PLUS | 0 | ||||
tVD;ACK | Data valid acknowledge time (2) | STANDARD MODE | 0.3 | 3.45 | μs |
FAST MODE | 0.1 | 0.9 | |||
FAST MODE PLUS | 0.05 | 0.45 | |||
tVD;DAT | Data valid time (3) | STANDARD MODE | 0.3 | 3.45 | μs |
FAST MODE | 0.1 | 0.9 | |||
FAST MODE PLUS | 0.05 | 0.45 | |||
tSU;DAT | Data set-up time | STANDARD MODE | 250 | ns | |
FAST MODE | 100 | ||||
FAST MODE PLUS | 50 | ||||
tLOW | Low period of SCL clock | STANDARD MODE | 4.7 | μs | |
FAST MODE | 1.3 | ||||
FAST MODE PLUS | 0.5 | ||||
tHIGH | High period of SCL clock | STANDARD MODE | 4 | μs | |
FAST MODE | 0.6 | ||||
FAST MODE PLUS | 0.26 | ||||
tf | Fall time of both SDA and SCL signals (5) (6) | STANDARD MODE | 300 | ns | |
FAST MODE | 20+0.1Cb (4) | 300 | |||
FAST MODE PLUS | 120 | ||||
tr | Rise time of both SDA and SCL signals | STANDARD MODE | 1000 | ns | |
FAST MODE | 20+0.1Cb (4) | 300 | |||
FAST MODE PLUS | 120 | ||||
tSP | Pulse width of spikes that must be suppressed by the input filter (7) | STANDARD MODE | 50 | ns | |
FAST MODE | 50 | ||||
FAST MODE PLUS | 50 | ||||
RESET | |||||
tW | Reset pulse width | STANDARD MODE | 10 | ns | |
FAST MODE | 10 | ||||
FAST MODE PLUS | 10 | ||||
tREC | Reset recovery time | STANDARD MODE | 0 | ns | |
FAST MODE | 0 | ||||
FAST MODE PLUS | 0 | ||||
tRESET | Time to reset (8) (9) | STANDARD MODE | 400 | ns | |
FAST MODE | 400 | ||||
FAST MODE PLUS | 400 |
VCC = 5 V | CG = 0.992 | REXT = 720 Ω |
VCC = 5 V | CG = 0.992 | |
REXT = 720 Ω | All Channels ON | |
The TLC59116-Q1 is an I2C Bus controlled 16-channel LED driver that is optimized for red/green/blue/amber (RGBA) color mixing and backlight application. Each LED output has its own 8-bit resolution (256 steps) fixed-frequency individual PWM controller that operates at 97-kHz, with a duty cycle that is adjustable from 0% to 99.6%. The individual PWM controller allows each LED to be set to a specific brightness value. An additional 8-bit resolution (256 steps) group PWM controller has both a fixed frequency of 190-Hz and an adjustable frequency between 24-Hz to once every 10.73 seconds, with a duty cycle that is adjustable from 0% to 99.6%. The group PWM controller dims or blinks all LEDs with the same value.
The TLC59116-Q1 LED open-circuit detection compares the effective current level IOUT with the open load detection threshold current IOUT,Th. If IOUT is below the threshold IOUT,Th the TLC59116-Q1 detects an open load condition. This error status can be read out as an error flag through the registers EFLAG1 and EFLAG2.
For open-circuit error detection, a channel must be on and the PWM must be off. See Table 1.
The TLC59116-Q1 LED is equipped with a global overtemperature sensor and 16 individual channel-selective overtemperature sensors.
For channel-specific overtemperature error detection, a channel must be on.
The error flags of open-circuit and overtemperature are ORed to set the EFLAG1 and EFLAG2 registers.
The error status code because of overtemperature is reset when the host writes 1 to bit 7 of the MODE2 register. The host must write 0 to bit 7 of the MODE2 register to enable the overtemperature error flag. See Table 2.
STATE OF OUTPUT PORT | CONDITION | ERROR STATUS CODE | MEANING |
---|---|---|---|
On On → all channels Off |
Tj < Tj,trip global | 1 | Normal |
Tj > Tj,trip global | All error status bits = 0 | Global overtemperature | |
On On → Off |
Tj < Tj,trip channel n | 1 | Normal |
Tj > Tj,trip channel n | Channel n error status bit = 0 | Channel n overtemperature |
When power is applied to VCC, an internal power-on reset holds the TLC59116-Q1 in a reset condition until VCC reaches VPOR. At this point, the reset condition is released and the TLC59116-Q1 registers, and I2C Bus state machine are initialized to their default states (all zeroes), causing all the channels to be deselected. Thereafter, VCC must be lowered below 0.2 V to reset the device.
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TLC59116-Q1 registers and I2C state machine are held in their default states until the RESET input is again high.
This input requires a pullup resistor to VCC if no active connection is used.
The Software Reset Call (SWRST Call) allows all the devices in the I2C Bus to be reset to the power-up state value through a specific I2C Bus command.
The SWRST Call function is defined as the following:
If more than two bytes of data are sent, the TLC59116-Q1 does not acknowledge any more.
The I2C Bus master may interpret a non-acknowledge from the TLC59116-Q1 (at any time) as a SWRST Call Abort. The TLC59116-Q1 does not initiate a reset of its registers. This happens only when the format of the Start Call sequence is not correct.
A 97-kHz fixed-frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control the individual brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be applied to the four LED outputs):
Active mode occurs when one or more of the output channels is enabled.
Standby mode occurs when all output channels are disabled. Standby mode may be entered via I2C command or by pulling the RESET pin low.
The I2C Bus is for two-way two-line communication between different devices or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 10).
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the Start condition (S). A low-to-high transition of the data line while the clock is high is defined as the Stop condition (P) (see Figure 11).
The number of data bytes transferred between the Start and the Stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. See Figure 12.
A slave receiver that is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during the high period of the acknowledge related clock pulse; set-up time and hold time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line high to enable the master to generate a Stop condition. See Figure 13.
A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the message is the master and the devices that are controlled by the master are the slaves (see Figure 18).
Following a Start condition, the bus master must output the address of the slave it is accessing.
The I2C Bus slave address of the TLC59116-Q1 is shown in Figure 19. To conserve power, no internal pullup resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low. For buffer management purposes, a set of sector information data should be stored.
The last bit of the address byte defines the operation to be performed. When set to logic 1, a read operation is selected. When set to logic 0, a write operation is selected.
See LED All Call I2C Bus Address Register (ALLCALLADR) for more detail.
NOTE
The default LED All Call I2C Bus address (D0h or 1101 000) must not be used as a regular I2C Bus slave address, since this address is enabled at power-up. All the TLC59116-Q1 devices on the I2C Bus will acknowledge the address if it is sent by the I2C Bus master.
See I2C Bus Subaddress Registers 1 to 3 (SUBADR1 to SUBADR3) for more detail.
NOTE
The LED Sub Call I2C Bus addresses may be used as regular I2C Bus slave addresses if their corresponding enable bits are set to 0 in the MODE1 Register.
The address shown in Figure 20 is used when a reset of the TLC59116-Q1 is performed by the master. The software reset address (SWRST Call) must be used with R/W = 0. If R/W = 1, the TLC59116-Q1 does not acknowledge the SWRST. See Software Reset for more detail.
NOTE
The Software Reset I2C Bus address is reserved address and cannot be use as regular I2C Bus slave address or as an LED All Call or LED Sub Call address.
Following the successful acknowledgment of the slave address, LED All Call address or LED Sub Call address, the bus master sends a byte to the TLC59116-Q1, which is stored in the Control register. The lowest five bits are used as a pointer to determine which register is accessed (D[4:0]). The highest three bits are used as auto-increment flag and auto-increment options (AI[2:0]). See Figure 21.
When the auto-increment flag is set (AI2 = logic 1), the five low order bits of the Control register are automatically incremented after a read or write. This allows the user to program the registers sequentially. Four different types of auto-increment are possible, depending on AI1 and AI0 values as shown in Table 3.
AI2 | AI1 | AI0 | DESCRIPTION |
---|---|---|---|
0 | 0 | 0 | No auto-increment |
1 | 0 | 0 | Auto-increment for all registers. D[4:0] roll over to 0 0000 after the last register (1 1011) is accessed. |
1 | 0 | 1 | Auto-increment for individual brightness registers only. D[4:0] roll over to 0 0010 after the last register (1 0001) is accessed. |
1 | 1 | 0 | Auto-increment for global control registers only. D[4:0] roll over to 1 0010 after the last register (1 0011) is accessed. |
1 | 1 | 1 | Auto-increment for individual and global control registers only. D[4:0] roll over to 0 0010 after the last register (1 0011) is accessed. |
NOTE
Other combinations are not shown in Table 3. (AI[2:0] = 001, 010, and 011) are reserved and must not be used for proper device operation.
AI[2:0] = 000 is used when the same register must be accessed several times during a single I2C Bus communication, for example, changing the brightness of a single LED. Data is overwritten each time the register is accessed during a write operation.
AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming.
AI[2:0] = 101 is used when the four LED drivers must be individually programmed with different values during the same I2C Bus communication, for example, changing a color setting to another color setting.
AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same I2C Bus communication, for example, global brightness or blinking change.
AI[2:0] = 111 is used when individually and global changes must be performed during the same I2C Bus communication, for example, changing color and global brightness at the same time.
Only the five least significant bits D[4:0] are affected by the AI[2:0] bits.
When the Control register is written, the register entry point determined by D[4:0] is the first register that will be addressed (read or write operation), and can be anywhere between 0 0000 and 1 1011 (as defined in Table 4). When AI[2] = 1, the Auto-Increment flag is set and the rollover value at which the point where the register increment stops and goes to the next one is determined by AI[2:0]. See Table 3 for rollover values. For example, if the Control register = 1111 0100 (F4h), then the register addressing sequence will be (in hex):
14 → ... → 1B → 00 → ... → 13 → 02 → ... → 13 → 02 → ... as long as the master keeps sending or reading data.
Table 4 describes the registers in the TLC59116-Q1.
REGISTER NUMBER (HEX) |
NAME | ACCESS (1) | DESCRIPTION |
---|---|---|---|
00 | MODE1 | R/W | Mode 1 |
01 | MODE2 | R/W | Mode 2 |
02 | PWM0 | R/W | Brightness control LED0 |
03 | PWM1 | R/W | Brightness control LED1 |
04 | PWM2 | R/W | Brightness control LED2 |
05 | PWM3 | R/W | Brightness control LED3 |
06 | PWM4 | R/W | Brightness control LED4 |
07 | PWM5 | R/W | Brightness control LED5 |
08 | PWM6 | R/W | Brightness control LED6 |
09 | PWM7 | R/W | Brightness control LED7 |
0A | PWM8 | R/W | Brightness control LED8 |
0B | PWM9 | R/W | Brightness control LED9 |
0C | PWM10 | R/W | Brightness control LED10 |
0D | PWM11 | R/W | Brightness control LED11 |
0E | PWM12 | R/W | Brightness control LED12 |
0F | PWM13 | R/W | Brightness control LED13 |
10 | PWM14 | R/W | Brightness control LED14 |
11 | PWM15 | R/W | Brightness control LED15 |
12 | GRPPWM | R/W | Group duty cycle control |
13 | GRPFREQ | R/W | Group frequency |
14 | LEDOUT0 | R/W | LED output state 0 |
15 | LEDOUT1 | R/W | LED output state 1 |
16 | LEDOUT2 | R/W | LED output state 2 |
17 | LEDOUT3 | R/W | LED output state 3 |
18 | SUBADR1 | R/W | I2C Bus subaddress 1 |
19 | SUBADR2 | R/W | I2C Bus subaddress 2 |
1A | SUBADR3 | R/W | I2C Bus subaddress 3 |
1B | ALLCALLADR | R/W | LED All Call I2C Bus address |
1C | IREF | R/W | IREF configuration |
1D | EFLAG1 | R | Error flags 1 |
1E | EFLAG2 | R | Error flags 2 |
Table 5 describes Mode Register 1.
BIT | SYMBOL | ACCESS (1) | VALUE | DESCRIPTION |
---|---|---|---|---|
7 | AI2 | R | 0 (2) | Register auto-increment disabled |
1 | Register auto-increment enabled | |||
6 | AI1 | R | 0 (2) | Auto-increment bit 1 = 0 |
1 | Auto-increment bit 1 = 1 | |||
5 | AI0 | R | 0 (2) | Auto-increment bit 0 = 0 |
1 | Auto-increment bit 0 = 1 | |||
4 | OSC | R/W | 0 | Normal mode (3) |
1 (2) | Oscillator off. | |||
3 | SUB1 | R/W | 0 (2) | Device does not respond to I2C Bus subaddress 1. |
1 | Device responds to I2C Bus subaddress 1. | |||
2 | SUB2 | R/W | 0 (2) | Device does not respond to I2C Bus subaddress 2. |
1 | Device responds to I2C Bus subaddress 2. | |||
1 | SUB3 | R/W | 0 (2) | Device does not respond to I2 CBus subaddress 3. |
1 | Device responds to I2C Bus subaddress 3. | |||
0 | ALLCALL | R/W | 0 | Device does not respond to LED All Call I2C Bus address. |
1 (2) | Device responds to LED All Call I2C Bus address. |
NOTE
The OSC bit (Bit 4) must be set to 0 before any outputs will turn on. Proper operation requires this bit to be 0. Setting the bit to a 1 will turn all channels off.
Table 6 describes Mode Register 2.
BIT | SYMBOL | ACCESS (1) | VALUE | DESCRIPTION |
---|---|---|---|---|
7 | EFCLR | R/W | 0 (2) | Enable error status flag |
1 | Clear error status flag | |||
6 | R | 0 (2) | Reserved | |
5 | DMBLNK | R/W | 0 (2) | Group control = dimming |
1 | Group control = blinking | |||
4 | R | 0 (2) | Reserved | |
3 | OCH | R/W | 0 (2) | Outputs change on Stop command (3) |
1 | Outputs change on ACK | |||
2:0 | R | 000 (2) | Reserved |
Table 7 describes Brightness Control Registers 0 to 15.
ADDRESS | REGISTER | BIT | SYMBOL | ACCESS (1) | VALUE | DESCRIPTION |
---|---|---|---|---|---|---|
02h | PWM0 | 7:0 | IDC0[7:0] | R/W | 0000 0000 (2) | PWM0 individual duty cycle |
03h | PWM1 | 7:0 | IDC1[7:0] | R/W | 0000 0000 (2) | PWM1 individual duty cycle |
04h | PWM2 | 7:0 | IDC2[7:0] | R/W | 0000 0000 (2) | PWM2 individual duty cycle |
05h | PWM3 | 7:0 | IDC3[7:0] | R/W | 0000 0000 (2) | PWM3 individual duty cycle |
06h | PWM4 | 7:0 | IDC4[7:0] | R/W | 0000 0000 (2) | PWM4 individual duty cycle |
07h | PWM5 | 7:0 | IDC5[7:0] | R/W | 0000 0000 (2) | PWM5 individual duty cycle |
08h | PWM6 | 7:0 | IDC6[7:0] | R/W | 0000 0000 (2) | PWM6 individual duty cycle |
09h | PWM7 | 7:0 | IDC7[7:0] | R/W | 0000 0000 (2) | PWM7 individual duty cycle |
0Ah | PWM8 | 7:0 | IDC8[7:0] | R/W | 0000 0000 (2) | PWM8 individual duty cycle |
0Bh | PWM9 | 7:0 | IDC9[7:0] | R/W | 0000 0000 (2) | PWM9 individual duty cycle |
0Ch | PWM10 | 7:0 | IDC10[7:0] | R/W | 0000 0000 (2) | PWM10 individual duty cycle |
0Dh | PWM11 | 7:0 | IDC11[7:0] | R/W | 0000 0000 (2) | PWM11 individual duty cycle |
0Eh | PWM12 | 7:0 | IDC12[7:0] | R/W | 0000 0000 (2) | PWM12 individual duty cycle |
0Fh | PWM13 | 7:0 | IDC13[7:0] | R/W | 0000 0000 (2) | PWM13 individual duty cycle |
10h | PWM14 | 7:0 | IDC14[7:0] | R/W | 0000 0000 (2) | PWM14 individual duty cycle |
11h | PWM15 | 7:0 | IDC15[7:0] | R/W | 0000 0000 (2) | PWM15 individual duty cycle |
A 97-kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = LED output at maximum brightness). Applicable to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0, LEDOUT1, LEDOUT2 and LEDOUT3 registers).
Table 8 describes the Group Duty Cycle Control Register.
ADDRESS | REGISTER | BIT | SYMBOL | ACCESS (1) | VALUE | DESCRIPTION |
---|---|---|---|---|---|---|
12h | GRPPWM | 7:0 | GDC0[7:0] | R/W | 1111 1111 (2) | GRPPWM register |
When the DMBLNK bit (MODE2 register) is programmed with logic 0, a 190-Hz fixed-frequency signal is superimposed with the 97-kHz individual brightness control signal. GRPPWM is then used as a global brightness control, allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a Don't care.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = maximum brightness). This is applicable to LED outputs programmed with LDRx = 11 (LEDOUT0, LEDOUT1, LEDOUT2 and LEDOUT3 registers).
When DMBLNK bit is programmed with logic 1, the GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ defines the blinking period (from 24-Hz to 10.73 s) and GRPPWM defines the duty cycle (ON/OFF ratio in %).
Table 9 describes the Group Frequency Register.
ADDRESS | REGISTER | BIT | SYMBOL | ACCESS (1) | VALUE | DESCRIPTION |
---|---|---|---|---|---|---|
13h | GRPFREQ | 7:0 | GFRQ[7:0] | R/W | 0000 0000 (2) | GRPFREQ register |
GRPFREQ is used to program the global blinking period when the DMBLNK bit (MODE2 register) is equal to 1. Value in this register is a Don't care when DMBLNK = 0. This is applicable to LED output programmed with LDRx = 11 (LEDOUT0, LEDOUT1, LEDOUT2 and LEDOUT3 registers).
The blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 s).
Global blinking period (seconds) = (GFRQ[7:0] + 1) / 24
Table 10 describes LED Driver Output State Registers 0 to 3.
ADDRESS | REGISTER | BIT | SYMBOL | ACCESS (1) | VALUE | DESCRIPTION |
---|---|---|---|---|---|---|
14h | LEDOUT0 | 7:6 | LDR3[1:0] | R/W | 00 (2) | LED3 output state control |
5:4 | LDR2[1:0] | R/W | 00 (2) | LED2 output state control | ||
3:2 | LDR1[1:0] | R/W | 00 (2) | LED1 output state control | ||
1:0 | LDR0[1:0] | R/W | 00 (2) | LED0 output state control | ||
15h | LEDOUT1 | 7:6 | LDR7[1:0] | R/W | 00 (2) | LED7 output state control |
5:4 | LDR6[1:0] | R/W | 00 (2) | LED6 output state control | ||
3:2 | LDR5[1:0] | R/W | 00 (2) | LED5 output state control | ||
1:0 | LDR4[1:0] | R/W | 00 (2) | LED4 output state control | ||
16h | LEDOUT2 | 7:6 | LDR11[1:0] | R/W | 00 (2) | LED11 output state control |
5:4 | LDR10[1:0] | R/W | 00 (2) | LED10 output state control | ||
3:2 | LDR9[1:0] | R/W | 00 (2) | LED9 output state control | ||
1:0 | LDR8[1:0] | R/W | 00 (2) | LED8 output state control | ||
17h | LEDOUT3 | 7:6 | LDR15[1:0] | R/W | 00 (2) | LED15 output state control |
5:4 | LDR14[1:0] | R/W | 00 (2) | LED14 output state control | ||
3:2 | LDR13[1:0] | R/W | 00 (2) | LED13 output state control | ||
1:0 | LDR12[1:0] | R/W | 00 (2) | LED12 output state control |
LDRx = 00: LED driver x is off (default power-up state).
LDRx = 01: LED driver x is fully on (individual brightness and group dimming/blinking not controlled).
LDRx = 10: LED driver x is individual brightness can be controlled through its PWMx register.
LDRx = 11: LED driver x is individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers.
Table 11 describes I2C Bus Subaddress Registers 1 to 3.
ADDRESS | REGISTER | BIT | SYMBOL | ACCESS (1) | VALUE | DESCRIPTION |
---|---|---|---|---|---|---|
18h | SUBADR1 | 7:1 | A1[7:1] | R/W | 1101 001 (2) | I2C Bus subaddress 1 |
0 | A1[0] | R | 0 (2) | Reserved | ||
19h | SUBADR2 | 7:1 | A2[7:1] | R/W | 1101 010 (2) | I2C Bus subaddress 2 |
0 | A2[0] | R | 0 (2) | Reserved | ||
1Ah | SUBADR3 | 7:1 | A3[7:1] | R/W | 1101 100 (2) | I2C Bus subaddress 3 |
0 | A3[0] | R | 0 (2) | Reserved |
Subaddresses are programmable through the I2C Bus. Default power-up values are D2h, D4h, D8h. The TLC59116-Q1 does not acknowledge these addresses immediately after power-up (the corresponding SUBx bit in MODE1 register is equal to 0).
Once subaddresses have been programmed to valid values, the SUBx bits (MODE1 register) must be set to 1 to allows the device to acknowledge these addresses.
Only the 7 MSBs representing the I2C Bus subaddress are valid. The LSB in SUBADRx register is a read-only bit (0).
When SUBx is set to 1, the corresponding I2C Bus subaddress can be used during either an I2C Bus read or write sequence.
Table 12 describes the LED All Call I2C Bus Address Register.
ADDRESS | REGISTER | BIT | SYMBOL | ACCESS (1) | VALUE | DESCRIPTION |
---|---|---|---|---|---|---|
1Bh | ALLCALLADR | 7:1 | AC[7:1] | R/W | 1101 000 (2) | All Call I2C Bus address |
0 | AC[0] | R | 0 (2) | Reserved |
The LED All Call I2C Bus address allows all the TLC59116-Q1 devices in the bus to be programmed at the same time (ALLCALL bit in register MODE1 must be equal to 1, which is the power-up default state). This address is programmable through the I2C Bus and can be used during either an I2C Bus read or write sequence. The register address can also be programmed as a Sub Call.
Only the seven MSBs representing the All Call I2C bus address are valid. The LSB in ALLCALLADR register is a read-only bit (0).
If ALLCALL bit = 0, the device does not acknowledge the address programmed in register ALLCALLADR.
Table 13 describes the Output Gain Control Register.
ADDRESS | REGISTER | BIT | SYMBOL | ACCESS (1) | VALUE | DESCRIPTION |
---|---|---|---|---|---|---|
1Ch | IREF | 7 | CM | R/W | 1 (2) | High/low current multiplier |
6 | HC | R/W | 1 (2) | Subcurrent | ||
5:0 | CC[5:0] | R/W | 11 1111 (2) | Current multiplier |
IREF determines the voltage gain (VG), which affects the voltage at the REXT terminal and indirectly the reference current (Iref) flowing through the external resistor at terminal REXT. Bit 0 is the Current Multiplier (CM) bit, which determines the ratio IOUT,target/Iref. Each combination of VG and CM sets a Current Gain (CG).
VG = (1 + HC) × (1 + D/64) / 4
D = CC0 × 25 + CC1 × 24 + CC2 × 23 + CC3 × 22 + CC4 × 21 + CC5 × 20
Where HC is 1 or 0, and D is the binary value of CC[0:5]. So, the VG could be regarded as a floating-point number with 1-bit exponent HC and 6-bit mantissa CC[0:5]. {HC,CC[0:5]} divides the programmable voltage gain (VG) into 128 steps and two sub-bands:
Low-voltage subband (HC = 0): VG = 1/4 to 127/256, linearly divided into 64 steps
High-voltage subband (HC = 1): VG = 1/2 to 127/128, linearly divided into 64 steps
High Current Multiplier (CM = 1): IOUT,target/Iref = 15, suitable for output current range IOUT = 10 mA to 120 mA.
Low Current Multiplier (CM = 0): IOUT,target/Iref = 5, suitable for output current range IOUT = 5 mA to 40 mA
VREXT = 1.26 V × VG
Iref = VREXT/Rext, if the external resistor (Rext) is connected to ground.
IOUT,target = Iref × 15 × 3CM – 1 = 1.26 V/Rext × VG × 15 × 3CM – 1 = (1.26 V/Rext × 15) × CG
CG = VG × 3CM – 1
Therefore, CG = (1/12) to (127/128), divided into 256 steps.
Examples
VG = 127/128 = 0.992 and CG = VG × 30 = VG = 0.992
VG = (1 + 1) × (1 + 0/64)/4 = 1/2 = 0.5, and CG = 0.5
VG = (1 + 0) × (1 + 0/64)/4 = 1/4, and CG = (1/4) × 3–1 = 1/12
After power-on, the default value of the Configuration Code {CM, HC, CC[0:5]} is {1,1,111111}. Therefore, VG = CG = 0.992. The relationship between the Configuration Code and the Current Gain is shown in Figure 22.
Table 14 describes Error Flags Registers 1 and 2.
ADDRESS | REGISTER | BIT | SYMBOL | ACCESS (1) | VALUE (2) | DESCRIPTION (3) |
---|---|---|---|---|---|---|
1Dh | EFLAG1 | 0 | EFLAG1[0] | R | 0 | Channel 0 |
1 | EFLAG1[1] | 0 | Channel 1 | |||
2 | EFLAG1[2] | 0 | Channel 2 | |||
3 | EFLAG1[3] | 0 | Channel 3 | |||
4 | EFLAG1[4] | 0 | Channel 4 | |||
5 | EFLAG1[5] | 0 | Channel 5 | |||
6 | EFLAG1[6] | 0 | Channel 6 | |||
7 | EFLAG1[7] | 0 | Channel 7 | |||
1Eh | EFLAG2 | 0 | EFLAG1[0] | R | 0 | Channel 8 |
1 | EFLAG1[1] | 0 | Channel 9 | |||
2 | EFLAG1[2] | 0 | Channel 10 | |||
3 | EFLAG1[3] | 0 | Channel 11 | |||
4 | EFLAG1[4] | 0 | Channel 12 | |||
5 | EFLAG1[5] | 0 | Channel 13 | |||
6 | EFLAG1[6] | 0 | Channel 14 | |||
7 | EFLAG1[7] | 0 | Channel 15 |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
In LED display applications, TLC59116-Q1 provides nearly no current variations from channel to channel and from device to device. While IOUT ≤ 52 mA, the maximum current skew between channels is less than ±6% and less than ±10% between devices.
TLC59116-Q1 scales up the reference current (Iref) set by the external resistor (Rext) to sink the output current (Iout) at each output port. Table 13 shows the Configuration Code and discusses bits CM, HC, and CC[5:0]. The following formulas can be used to calculate the target output current IOUT,target in the saturation region:
Where Rext is the resistance of the external resistor connected to the REXT terminal, and VREXT is the voltage of REXT, which is controlled by the programmable voltage gain (VG), which is defined by the Configuration Code.
The Current Multiplier bit (CM) sets the ratio IOUT,target/Iref to 15 or 5 (sets the exponent CM – 1 to either 0 or –1). After power-on, the default value of VG is 127/128 = 0.992, and the default value of CM is 1, so that the ratio IOUT,target/Iref = 15. Based on the default VG and CM:
Therefore, the default current is approximately 20 mA at 931 Ω. The default relationship after power-on between IOUT,target and Rext is shown in Figure 24.
shows the output voltage versus the output current with several different resistor values on REXT. This shows the minimum voltage required at the device to have full VF across the LED. The VLED voltage must be higher than the VF plus the VOL of the driver. If the VLED is too high, more power will be dissipated in the driver. If this is the case, a resistor can be inserted in series with the LED to dissipate the excess power and reduce the thermal conditions on the driver.
If a single driver is used with LEDs that have different VF values, resistors can also be used in series with the LED to remove the excess power from the driver. In cases where not all outputs are being used, the unused outputs can be left floating without issue.
The TLC59116-Q1 outputs can be wired in parallel to increase the current per LED string.
Set the LED current to 50 mA while the IREF register is at the default value (CG = 0.992).
The goal of this design is to set the LED current to 50 mA. Because two outputs are in parallel, the LED current should actually be set to 25 mA. With the IREF register at the default value:
Using this equation, the appropriate REXT is calculated to be 750 Ω.
TLC59116-Q1 is designed to operate from a VCC range of 3 V to 5.5 V.
The I2C signals (SDA / SCL) should be kept away from potential noise sources.
The traces carrying power through the LEDs should be wide enough to the handle necessary current.
All LED current passes through the device and into the ground node. The connection between the device ground and the circuit board ground must be a strong connection.
The maximum IC junction temperature should be restricted to 150°C under normal operating conditions. To calculate the maximum allowable dissipation, PD(max) for a given ambient temperature, use Equation 9 as a guideline:
where
See Thermal Information section. This parameter is highly dependent upon board layout.
Power dissipation in the device is determined by the LED current and the voltage at the OUTx pins. For example, if the LED current is 50 mA continuous through each channel and the output voltage is 1 V on each channel, then the total power dissipation is 50 mA × 1 V × 16 ch = 0.8 W.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
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