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  • TLIN2022A-Q1 Dual Local Interconnect Network (LIN) Transceiver with Dominant State Timeout

    • SLLSFM6 June   2021 TLIN2022A-Q1

      PRODUCTION DATA  

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  • TLIN2022A-Q1 Dual Local Interconnect Network (LIN) Transceiver with Dominant State Timeout
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Description (Continued)
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings - IEC
    4. 7.4 Thermal Information
    5. 7.5 Recommended Operating Conditions
    6. 7.6 Electrical Characteristics
    7. 7.7 Duty Cycle Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  LIN (Local Interconnect Network) Bus
        1. 9.3.1.1 LIN Transmitter Characteristics
        2. 9.3.1.2 LIN Receiver Characteristics
          1. 9.3.1.2.1 Termination
      2. 9.3.2  TXD
      3. 9.3.3  RXD (Receive Output)
      4. 9.3.4  VSUP (Supply Voltage)
      5. 9.3.5  GND (Ground)
      6. 9.3.6  EN (Enable Input)
      7. 9.3.7  Protection Features
      8. 9.3.8  TXD Dominant Time Out (DTO)
      9. 9.3.9  Bus Stuck Dominant System Fault: False Wake-Up Lockout
      10. 9.3.10 Thermal Shutdown
      11. 9.3.11 Undervoltage on VSUP
      12. 9.3.12 Unpowered Device and LIN Bus
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Sleep Mode
      3. 9.4.3 Standby Mode
      4. 9.4.4 Wake-Up Events
        1. 9.4.4.1 Wake-Up Request (RXD)
        2. 9.4.4.2 Mode Transitions
  10. 10Application Information Disclaimer
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 Normal Mode Application Note
        2. 10.2.2.2 Standby Mode Application Note
        3. 10.2.2.3 TXD Dominant State Timeout Application Note
      3. 10.2.3 Application Curves
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DMT|14
    • MPSS087B
  • D|14
    • MPDS177H
Thermal pad, mechanical data (Package|Pins)
  • DMT|14
    • QFND637
Orderable Information
  • sllsfm6_oa
  • sllsfm6_pm
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DATA SHEET

TLIN2022A-Q1 Dual Local Interconnect Network (LIN) Transceiver with Dominant State Timeout

1 Features

  • AEC-Q100 (grade 1) qualified for automotive applications
  • Compliant to LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2 A and ISO/DIS 17987–4 electrical physical layer (EPL) specification
  • Conforms to SAE J2602-1 LIN network for vehicle applications
  • Functional Safety-Capable
    • Documentation available to aid in functional safety system design
  • Supports 12-V and 24-V battery applications
  • LIN transmit data rate up to 20 kbps
  • LIN receive data rate up to 100 kbps
  • Wide operational supply voltage range from 4 V to 48 V
  • Sleep mode: ultra-low current consumption allows wake-up event from:
    • LIN bus
    • Local wake up through EN
  • Power up and power down glitch-free operation on LIN bus and RXD output
  • Protection features:
    • ±60 V LIN bus fault tolerant
    • Undervoltage protection on VSUP
    • TXD Dominant time out protection (DTO)
    • Thermal shutdown protection
    • Unpowered node or ground disconnection failsafe at system level.
  • Available in SOIC (14) package and leadless VSON (14) Package with wettable flanks

2 Applications

  • Body electronics and lighting
  • Hybrid electric vehicles and power train systems
  • Infotainment and cluster
  • Appliances

3 Description

The TLIN2022A-Q1 is a Dual Local Interconnect Network (LIN) physical layer transceiver with integrated wake-up and protection features, compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4 standards. LIN is a single wire bidirectional bus typically used for low speed in-vehicle networks using data rates up to 20 kbps. The TLIN2022A-Q1 is designed to support 12-V and 24-V applications with wider operating voltage and additional bus-fault protection.

The LIN receiver supports data rates up to 100 kbps for faster in-line programming. The TLIN2022A-Q1 converts the LIN protocol data stream on the TXD input into a LIN bus signal using a current-limited wave-shaping driver which reduces electromagnetic emissions (EME). The receiver converts the data stream to logic-level signals that are sent to the microprocessor through the open-drain RXD pin. Ultra-low current consumption is possible using the sleep mode which allows wake-up via LIN bus or EN pin.

Device Information
PART NUMBERPACKAGE(1)BODY SIZE (NOM)
TLIN2022A-Q1SOIC (14) (D)5.00 mm x 8.65 mm
VSON (14) (DMT)3.00 mm x 4.50 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20210513-CA0I-FWG5-RQJS-B3GWVB1FPNXD-low.gifSimplified Schematics, Commander Mode
GUID-20210513-CA0I-6CLM-MC3S-MR7PT3KNRNJF-low.gifSimplified Schematics, Responder Mode

4 Description (Continued)

The TLIN2022A-Q1 integrates a resistor for LIN responder node applications, ESD protection, and fault protection which allow for a reduced amount of external components in the applications. The device prevents back-feed current through LIN to the supply input in case of a ground shift or supply voltage disconnection. The device also includes undervoltage detection, temperature shutdown protection, and loss-of-ground protection.

5 Revision History

DATEREVISIONNOTES
June 2021*Initial release

6 Pin Configuration and Functions

Figure 6-1 D Package, 14-Pin (SOIC), Top View
Figure 6-2 DMT Package, 14-Pin (VSON), Top View
Table 6-1 Pin Functions
PIN Type DESCRIPTION
NO. NAME
1 RXD1 O Channel 1 RXD Output (open-drain) interface reporting state of LIN bus voltage
2 EN1 I Channel 1 Enable Input- High puts the channel 1 in normal operation mode and low puts it in sleep mode
3 TXD1 I Channel 1 TXD input interface to control state of LIN output
4 RXD2 O Channel 2 RXD Output (open-drain) interface reporting state of LIN bus voltage
5 EN2 I Channel 2 Enable Input- High puts the channel 2 in normal operation mode and low puts it in sleep mode
7 TXD2 I Channel 2 TXD input interface to control state of LIN output
8 GND GND Ground
9 LIN2 HV I/O Channel 2 High voltage LIN bus single-wire transmitter and receiver
10 VSUP Supply Device Supply Voltage (connected to battery in series with external reverse blocking diode)
13 LIN1 HV I/O Channel 1 High voltage LIN bus single-wire transmitter and receiver
6, 11, 12,
14		 NC – Not Connected
Thermal Pad – Can be connected to the PCB ground plane to improve thermal coupling (DMT package only)

7 Specifications

7.1 Absolute Maximum Ratings

(1) (2)
Symbol Parameter MIN MAX UNIT
VSUP Supply voltage range (ISO/DIS 17987 Param 10) –0.3 60 V
VLIN LIN bus input voltage (ISO/DIS 17987 Param 82) –60 60 V
VLOGIC Logic pin voltage (RXD, TXD, EN) –0.3 6 V
IO Logic pin output current 8 mA
TJ Junction temperature range –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground terminal.

 
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