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  • TLV936x-Q1 Automotive, 10MHz, 40V, Rail-to-Rail Output, Operational Amplifier for Cost-Sensitive Systems

    • SBOSAD6B April   2023  – August 2024 TLV9361-Q1 , TLV9362-Q1 , TLV9364-Q1

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  • TLV936x-Q1 Automotive, 10MHz, 40V, Rail-to-Rail Output, Operational Amplifier for Cost-Sensitive Systems
  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 EMI Rejection
      2. 6.3.2 Thermal Protection
      3. 6.3.3 Capacitive Load and Stability
      4. 6.3.4 Electrical Overstress
      5. 6.3.5 Overload Recovery
      6. 6.3.6 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
        2. 8.1.1.2 TI Precision Designs
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
  12. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
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    • MSOI002K
  • PW|8
    • MPDS568
  • DGK|8
    • MPDS028E
Thermal pad, mechanical data (Package|Pins)
Orderable Information
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  • sbosad6b_pm
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Data Sheet

TLV936x-Q1 Automotive, 10MHz, 40V, Rail-to-Rail Output, Operational Amplifier for Cost-Sensitive Systems

1 Features

  • AEC-Q100 qualified for automotive applications
    • Temperature grade 1: –40°C to +125°C
    • Human-body model (HBM) Electrostatic discharge (ESD) classification level: 2A
    • Charged-device model (CDM) ESD classification level: C6
  • Low offset voltage: ±400µV
  • Low offset voltage drift: ±1.25µV/°C
  • Low noise: 8.5nV/√Hz at 1kHz, 6nV/√Hz broadband
  • High common-mode rejection: 110dB
  • Low bias current: ±10pA
  • Rail-to-rail output
  • Wide bandwidth: 10.6MHz GBW, unity-gain stable
  • High slew rate: 25V/µs
  • Low quiescent current: 2.6mA per amplifier
  • Wide supply: ±2.25V to ±20V, 4.5V to 40V
  • Robust EMIRR performance

2 Applications

  • Automotive head unit
  • Digital cockpit processing unit
  • Telematics control unit
  • Emergency call (eCall)
  • Automotive active noise cancellation
  • Automotive external amplifier

3 Description

The TLV936x-Q1 family (TLV9361-Q1, TLV9362-Q1, and TLV9364-Q1) is a family of AEC-Q100 automotive qualified, 40V cost-optimized operational amplifiers.

These devices offer strong DC and AC specifications, including rail-to-rail output, low input voltage noise density (6 nV/√Hz), low offset (±400µV, typical), low offset drift (±1.25µV/°C, typical), and 10.6MHz bandwidth.

Features such as EMIRR filtering, high output current (±60mA), and high slew rate (25V/µs) make the TLV936x-Q1 a robust operational amplifier for high-voltage, cost-sensitive applications.

The TLV936x-Q1 family of op amps is available in standard packages and is specified from –40°C to 125°C.

Package Information
PART NUMBER(1) PACKAGE PACKAGE SIZE(2)
TLV9361-Q1 DBV (SOT-23, 5) 2.9mm × 2.8mm
DCK (SC70, 5) 2mm × 2.1mm
TLV9362-Q1 D (SOIC, 8) 4.9mm × 6mm
DGK (VSSOP, 8) 3mm × 4.9mm
PW (TSSOP, 8) 3mm × 6.4mm
TLV9364-Q1 D (SOIC, 14) 8.65mm × 6mm
PW (TSSOP, 14) 5mm × 6.4mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 TLV936x-Q1 in a Single-Pole, Low-Pass Filter TLV936x-Q1 in a Single-Pole, Low-Pass Filter

4 Pin Configuration and Functions

TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 TLV9361-Q1 DBV Package5-Pin SOT-23(Top View)Figure 4-1 TLV9361-Q1 DBV Package
5-Pin SOT-23
(Top View)
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 TLV9361-Q1 DCK Package5-Pin SC70(Top View)Figure 4-2 TLV9361-Q1 DCK Package
5-Pin SC70
(Top View)
Table 4-1 Pin Functions: TLV9361-Q1
PINTYPE(1)DESCRIPTION
NAMESOT-23SC70
IN+31INon-inverting input
IN–43IInverting input
OUT14OOutput
V+55—Positive (highest) power supply
V–22—Negative (lowest) power supply
(1) I = input, O = output
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 TLV9362-Q1 D, DGK, and PW Package8-Pin SOIC, VSSOP, and TSSOP(Top View)Figure 4-3 TLV9362-Q1 D, DGK, and PW Package
8-Pin SOIC, VSSOP, and TSSOP
(Top View)
Table 4-2 Pin Functions: TLV9362-Q1
PINTYPE(1)DESCRIPTION
NAMENO.
IN1+3INon-inverting input, channel 1
IN1–2IInverting input, channel 1
IN2+5INon-inverting input, channel 2
IN2–6IInverting input, channel 2
OUT11OOutput, channel 1
OUT27OOutput, channel 2
V+8—Positive (highest) power supply
V–4—Negative (lowest) power supply
(1) I = input, O = output
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 TLV9364-Q1 D and PW Package,SOIC and TSSOP(Top View)Figure 4-4 TLV9364-Q1 D and PW Package,
SOIC and TSSOP
(Top View)
Table 4-3 Pin Functions: TLV9364-Q1
PINTYPE(1)DESCRIPTION
NAMENO.
IN1+3INon-inverting input, channel 1
IN1–2IInverting input, channel 1
IN2+5INon-inverting input, channel 2
IN2–6IInverting input, channel 2
IN3+10INon-inverting input, channel 3
IN3–9IInverting input, channel 3
IN4+12INon-inverting input, channel 4
IN4–13IInverting input, channel 4
OUT11OOutput, channel 1
OUT27OOutput, channel 2
OUT38OOutput, channel 3
OUT414OOutput, channel 4
V+4—Positive (highest) power supply
V–11—Negative (lowest) power supply
(1) I = input, O = output

5 Specifications

5.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VS = (V+) – (V–) 0 42 V
Signal input pins Common-mode voltage(3) (V–) – 0.5 (V+) + 0.5 V
Differential voltage(3) VS + 0.2 V
Current(3) –10 10 mA
Output short-circuit(2) Continuous
Operating ambient temperature, TA –55 150 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Operating the device beyond the ratings listed under Absolute Maximum Ratings causes permanent damage to the device. These are stress ratings only, based on process and design limitations, and this device has not been designed to function outside the conditions indicated under Recommended Operating Conditions. Exposure to any condition outside Recommended Operating Conditions for extended periods, including absolute-maximum-rated conditions, can affect device reliability and performance.
(2) Short-circuit to ground, one amplifier per package. Extended short-circuit current, especially with higher supply voltage, can cause excessive heating and eventual destruction.
(3) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails must be current limited to 10mA or less.

5.2 ESD Ratings

VALUEUNIT
TLV9361-Q1
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1500
TLV9362-Q1 and TLV9364-Q1
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±2500V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)±1500
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MINMAXUNIT
VSSupply voltage, (V+) – (V–)4.540V
VICommon mode voltage range(V–)(V+) – 2V
TASpecified temperature–40125°C

5.4 Thermal Information for Single Channel

THERMAL METRIC(1) TLV9361-Q1 UNIT
DBV
(SOT-23)		 DCK
(SC70)
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 189.3 202.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 86.8 111.6 °C/W
RθJB Junction-to-board thermal resistance 55.9 51.6 °C/W
ψJT Junction-to-top characterization parameter 23.6 25.8 °C/W
ψJB Junction-to-board characterization parameter 55.5 51.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

5.5 Thermal Information for Dual Channel

THERMAL METRIC(1) TLV9362-Q1 Unit
D
(SOIC)		 DGK
(VSSOP)		 PW
(TSSOP)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 130.8 173.9 159.1   °C/W
RθJC(top) Junction-to-case (top) thermal resistance 74.0 65.7 67.9   °C/W
RθJB Junction-to-board thermal resistance 74.3 95.6 98.1   °C/W
ψJT Junction-to-top characterization parameter 25.8 10.9 9.1   °C/W
ψJB Junction-to-board characterization parameter 73.5 94.1 96.7   °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A   °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

5.6 Thermal Information for Quad Channel

THERMAL METRIC(1) TLV9364-Q1 UNIT
D
(SOIC)		 PW
(TSSOP)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 94.9 120.0         °C/W
RθJC(top) Junction-to-case (top) thermal resistance 51.1 50.4         °C/W
RθJB Junction-to-board thermal resistance 51.4 63.1         °C/W
ψJT Junction-to-top characterization parameter 15.3 8.1         °C/W
ψJB Junction-to-board characterization parameter 51.0 62.5         °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A         °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

5.7 Electrical Characteristics

For VS = (V+) – (V–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = V– ±0.4 ±1.7 mV
TA = –40°C to 125°C ±2
dVOS/dT Input offset voltage drift VCM = V– TA = –40°C to 125°C ±1.25 µV/℃
PSRR Input offset voltage versus power supply VCM = V–, VS = 5 V to 40 V(1) TA = –40°C to 125°C ±1.5 ±7.5 μV/V
DC channel separation 1 µV/V
INPUT BIAS CURRENT
IB Input bias current ±10 pA
IOS Input offset current ±10 pA
NOISE
EN Input voltage noise f = 0.1 Hz to 10 Hz   6 μVPP
  1   µVRMS
eN Input voltage noise density f = 1 kHz 8.5   nV/√Hz
f = 10 kHz   6  
iN Input current noise density f = 1 kHz   100   fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) (V+) – 2 V
CMRR Common-mode rejection ratio VS = 40 V, V– < VCM < (V+) – 2 V TA = –40°C to 125°C 95 110 dB
VS = 5 V, V– < VCM < (V+) – 2 V(1) 75 85
INPUT IMPEDANCE
ZID Differential 100 || 9 MΩ || pF
ZICM Common-mode 6 || 1 TΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 40 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –  0.1 V		 115 130 dB
VS = 40 V, VCM = VS / 2,
(V–) + 0.12 V < VO < (V+) –  0.12 V		 TA = –40°C to 125°C 130
VS = 5 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –  0.1 V(1)		 100 120
TA = –40°C to 125°C 120
FREQUENCY RESPONSE
GBW Gain-bandwidth product 10.6 MHz
SR Slew rate VS = 40 V, G = +1, VSTEP = 10 V, CL = 20 pF(3) 25 V/μs
tS Settling time To 0.1%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF 0.65 μs
To 0.1%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF 0.3
To 0.01%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF 0.86
To 0.01%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF 0.44
Phase margin G = +1, RL = 10 kΩ, CL = 20 pF 64 °
Overload recovery time VIN  × gain > VS 170 ns
THD+N Total harmonic distortion + noise VS = 40 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ 0.0001%
120 dB
VS = 10 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 128 Ω 0.0056%
85 dB
VS = 10 V, VO = 0.4 VRMS, G = 1, f = 1 kHz, RL = 32 Ω 0.00056%
105 dB
OUTPUT
  Voltage output swing from rail Positive and negative
rail headroom		 VS = 40 V, RL = no load   10 mV
VS = 40 V, RL = 10 kΩ   60 100
VS = 40 V, RL = 2 kΩ   250 400
ISC Short-circuit current ±60(2) mA
CLOAD Capacitive Load Drive See Figure 5-28 pF
ZO Open-loop output impedance IO = 0 A See Figure 5-25 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 A 2.6 3 mA
TA = –40°C to 125°C 3.2
(1) Specified by characterization only.
(2) At high supply voltage, placing the TLV936x in a sudden short to mid-supply or ground will lead to rapid thermal shutdown.  Output current greater than ISC can be achieved if rapid thermal shutdown is avoided as per Figure 5-12.
(3) See Figure 5-11 for more information.

5.8 Typical Characteristics

at TA = 25°C, VS = ±20V, VCM = VS / 2, RLOAD = 10kΩ (unless otherwise noted)

TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Offset Voltage Production Distribution
Distribution from 74 amplifiers, TA = 25°C
Figure 5-1 Offset Voltage Production Distribution
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Offset Voltage vs Temperature
VCM = V-
Data from 74 amplifiers
Figure 5-3 Offset Voltage vs Temperature
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Offset Voltage vs Common-Mode Voltage
TA = 125°C
Data from 74 amplifiers
Figure 5-5 Offset Voltage vs Common-Mode Voltage
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Offset Voltage vs Power Supply
VCM = V–
Data from 74 amplifiers
Figure 5-7 Offset Voltage vs Power Supply
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Input Bias Current and Offset Current vs Common-Mode VoltageFigure 5-9 Input Bias Current and Offset Current vs Common-Mode Voltage
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Slew Rate vs Input Step Voltage

G = +1, CL = 20 pF

Figure 5-11 Slew Rate vs Input Step Voltage
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Output Voltage Swing vs Output Current (Sinking)
VS = 40V 
Figure 5-13 Output Voltage Swing vs Output Current (Sinking)
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Output Voltage Swing vs Output Current (Sinking)
VS = 5V
Figure 5-15 Output Voltage Swing vs Output Current (Sinking)
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 CMRR vs Temperature
VS = 40V
Figure 5-17 CMRR vs Temperature
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 PSRR vs Temperature
Figure 5-19 PSRR vs Temperature
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Input Voltage Noise Spectral Density vs FrequencyFigure 5-21 Input Voltage Noise Spectral Density vs Frequency
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Quiescent Current vs Temperature
VCM = V–
Figure 5-23 Quiescent Current vs Temperature
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Open-Loop Output Impedance vs FrequencyFigure 5-25 Open-Loop Output Impedance vs Frequency
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Small-Signal Overshoot vs Capacitive Load
20mVpp Output Step, G = +1
Figure 5-27 Small-Signal Overshoot vs Capacitive Load
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Positive Overload Recovery
G = –10
Figure 5-29 Positive Overload Recovery
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Small-Signal Step Response
CL = 20pF, G = 1, 20mVpp step response
Figure 5-31 Small-Signal Step Response
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Large-Signal Step Response
CL = 20pF, G = 1, 5Vpp step response
Figure 5-33 Large-Signal Step Response
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Maximum Output Voltage vs FrequencyFigure 5-35 Maximum Output Voltage vs Frequency
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 EMIRR (Electromagnetic Interference Rejection Ratio) vs FrequencyFigure 5-37 EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Offset Voltage Drift Distribution
Distribution from 74 amplifiers
Figure 5-2 Offset Voltage Drift Distribution
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Offset Voltage vs Common-Mode Voltage
TA = 25°C
Data from 74 amplifiers
Figure 5-4 Offset Voltage vs Common-Mode Voltage
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Offset Voltage vs Common-Mode Voltage
TA = –40°C
Data from 74 amplifiers
Figure 5-6 Offset Voltage vs Common-Mode Voltage
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Closed-Loop Gain vs FrequencyFigure 5-8 Closed-Loop Gain vs Frequency
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Input Bias Current and Offset Current vs TemperatureFigure 5-10 Input Bias Current and Offset Current vs Temperature
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Output Voltage Swing vs Output Current (Sourcing)
VS = 40 V
Figure 5-12 Output Voltage Swing vs Output Current (Sourcing)
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Output Voltage Swing vs Output Current (Sourcing)
VS = 5V
Figure 5-14 Output Voltage Swing vs Output Current (Sourcing)
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 CMRR and PSRR vs Frequency
 
Figure 5-16 CMRR and PSRR vs Frequency
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 CMRR vs Temperature
VS = 5V
Figure 5-18 CMRR vs Temperature
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 0.1Hz to 10-Hz NoiseFigure 5-20 0.1Hz to 10-Hz Noise
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Quiescent Current vs Supply Voltage
VCM = V–
Figure 5-22 Quiescent Current vs Supply Voltage
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Open-Loop Voltage Gain vs Temperature (dB)Figure 5-24 Open-Loop Voltage Gain vs Temperature (dB)
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Small-Signal Overshoot vs Capacitive Load
20mVpp Output Step, G = -1
Figure 5-26 Small-Signal Overshoot vs Capacitive Load
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Phase Margin vs Capacitive Load
G = +1
Figure 5-28 Phase Margin vs Capacitive Load
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Negative Overload Recovery
G = –10
Figure 5-30 Negative Overload Recovery
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Small-Signal Step Response
CL = 20pF, G = -1, 20mVpp step response
Figure 5-32 Small-Signal Step Response
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Large-Signal Step Response
CL = 20pF, G = -1, 5Vpp step response
Figure 5-34 Large-Signal Step Response
TLV9361-Q1 TLV9362-Q1 TLV9364-Q1 Channel Separation vs FrequencyFigure 5-36 Channel Separation vs Frequency

6 Detailed Description

 
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