TMS320C6743 Fixed- and Floating-Point Digital Signal Processor

1 TMS320C6743 Fixed- and Floating-Point Digital Signal Processor

1.1 Features

• Applications
  • Networking
  • High-Speed Encoding
  • Professional Audio™
• Software Support
  • TI DSP/BIOS™
  • Chip Support Library and DSP Library
• 375-MHz TMS320C674x Fixed- and Floating-Point VLIW DSP Core
  • Load-Store Architecture with Nonaligned Support
  • 64 General-Purpose Registers (32-Bit)
  • Six ALU (32- and 40-Bit) Functional Units
    • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
    • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
    • Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
  • Two Multiply Functional Units
    • Mixed-Precision IEEE Floating Point Multiply Supported up to:
      • 2 SP x SP -> SP Per Clock
      • 2 SP x SP -> DP Every Two Clocks
      • 2 SP x DP -> DP Every Three Clocks
      • 2 DP x DP -> DP Every Four Clocks
    • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
  • Instruction Packing Reduces Code Size
  • All Instructions Conditional
  • Hardware Support for Modulo Loop
    Operation
  • Protected Mode Operation
  • Exceptions Support for Error Detection and Program Redirection
• C674x Instruction Set Features
  • Superset of the C67x+ and C64x+ ISAs
  • 3000 MIPS and 2250 MFLOPS C674x
  • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
  • 8-Bit Overflow Protection
  • Bit-Field Extract, Set, Clear
  • Normalization, Saturation, Bit-Counting
  • Compact 16-Bit Instructions
• C674x Two-Level Cache Memory Architecture
  • 32KB of L1P Program RAM/Cache
  • 32KB of L1D Data RAM/Cache
  • 128KB of L2 Unified Mapped RAM/Cache
  • Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct Memory Access Controller 3 (EDMA3):
  • 2 Transfer Controllers
  • 32 Independent DMA Channels
  • 8 Quick DMA Channels
  • Programmable Transfer Burst Size
• 3.3-V LVCMOS I/Os
• Two External Memory Interfaces:
  • EMIFA
    • NOR (8-Bit-Wide Data)
    • NAND (8-Bit-Wide Data)
  • EMIFB
    • 16-bit SDRAM, up to 128MB
• Two Configurable 16550-Type UART Modules:
  • UART0 with Modem Control Signals
  • 16-Byte FIFO
  • 16x or 13x Oversampling Option
• One Serial Peripheral Interface (SPI) with One Chip Select
• Multimedia Card (MMC)/Secure Digital (SD)
• Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
• Programmable Real-Time Unit Subsystem (PRUSS)
  • Two Independent Programmable Real-Time Unit (PRU) Cores
    • 32-Bit Load-Store RISC Architecture
    • 4KB of Instruction RAM per Core
    • 512 Bytes of Data RAM per Core
    • PRUSS can be Disabled Through Software to Save Power
    • Register 30 of each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores
  • Standard Power-Management Mechanism
    • Clock Gating
    • Entire Subsystem Under a Single PSC Clock Gating Domain
  • Dedicated Interrupt Controller
  • Dedicated Switched Central Resource
• Two Multichannel Audio Serial Ports (McASPs):
  • Supports TDM, I2S, and Similar Formats
  • FIFO Buffers for Transmit and Receive
• 10/100 Mbps RMII Ethernet Media Access Controller (EMAC):
  • IEEE 802.3 Compliant (3.3-V I/O Only)
  • RMII Media-Independent Interface
  • Management Data I/O (MDIO) Module
• One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
• One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit Timers)
• Three Enhanced Pulse Width Modulators (eHRPWMs):
  • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
  • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
  • Dead-Band Generation
  • PWM Chopping by High-Frequency Carrier
  • Trip Zone Input
• Three 32-Bit Event Capture (eCAP) Modules:
  • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
  • Single-Shot Capture of up to Four Event Time-Stamps
• Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
• 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
• 176-Pin Thin Quad Flat Pack (TQFP) [PTP Suffix], 0.5-mm Pin Pitch
• Commercial or Automotive Temperature

1.2 Applications

• A/V Receivers
• Automotive Amplifiers
• Soundbars
• Home Theatre Systems
• Professional Audio
• Network Streaming Audio

1.3 Description

The C6743 device is a low-power digital signal processor based on C674x DSP core. The device consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The C6743 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance.

The C6743 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 128-KB of memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I²C Bus interfaces; two multichannel audio serial ports (McASPs) with 14/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; two UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces (EMIFs): an asynchronous external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6743 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

1.4 Functional Block Diagram

1. Not all peripherals are available at the same time due to multiplexing.

Figure 1-1 TMS320C6743 Functional Block Diagram

2 Revision History

This data manual revision history highlights the changes made to the SPRS565C device-specific data manual to make it an SPRS565D revision.

3 Device Overview

3.1 Device Characteristics

Table 3-1 provides an overview of the C6743 Low power digital signal processor. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin count.

3.2 Device Compatibility

The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both the C64x+ and C67x+ DSP families.

3.3 DSP Subsystem

The DSP Subsystem includes the following features:

• C674x DSP CPU
• 32KB L1 Program (L1P)/Cache (up to 32KB)
• 32KB L1 Data (L1D)/Cache (up to 32KB)
• 128KB Unified Mapped RAM/Cache (L2)
• Boot ROM (cannot be used for application code)
• Little endian

Figure 3-1 C674x Megamodule Block Diagram

3.3.1 C674x DSP CPU Description

The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 3-2. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.

Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes four 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on a variety of signed and unsigned 32-bit data types.

The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.

The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C674x core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support.

Other new features include:

• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
• Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools.
• Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication.
• Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration).
• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions.
• Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.

For more details on the C674x CPU and its enhancements over the C64x architecture, see the following documents:

• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732)
• TMS320C64x Technical Overview (SPRU395)

Figure 3-2 TMS320C674x CPU (DSP Core) Data Paths

3.3.2 DSP Memory Mapping

The DSP memory map is shown in Section 3.4.

3.3.2.1 External Memories

The DSP has access to the following External memories:

• Asynchronous EMIF / NAND / NOR Flash (EMIFA)
• SDRAM (EMIFB)

3.3.2.2 DSP Internal Memories

The DSP has access to the following DSP memories:

• L2 RAM
• L1P RAM
• L1D RAM

3.3.2.3 C674x CPU

The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2 memory/cache (L2) consists of a 128 KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both.

Table 3-2 shows a memory map of the C674x CPU cache registers for the device.

3.4 Memory Map Summary

Note: Read/Write accesses to illegal or reserved addresses in the memory map may cause undefined behavior.

3.4.1 C6743 Top Level Memory Map