TPS65142 LCD Bias Power Integrated with WLED Backlight Drivers

7.3.1 AVDD Boost Regulator

The AVDD boost regulator is designed for output voltages up to 16.5 V with a switch peak current limit of 1.8 A minimum. The device, which operates in a current-mode scheme with quasi-constant frequency, is internally compensated to minimize the pin and component counts. The switching frequency is selectable between 650 kHz and 1.2 MHz and the minimum input voltage is 2.3 V.

During the on-time, the current rises in the inductor. When the current reaches a threshold value set by the internal GM amplifier, the power transistor is turned off. The polarity of the inductor voltage changes and forward biases the Schottky diode, which lets the current flow towards the output of the boost regulator. The off-time is fixed for a certain input voltage V_IN and output voltage V_S, and therefore maintains the same frequency when varying these parameters. However, for different output loads, the frequency changes slightly due to the voltage drop across the r_DS(on) of the power transistor which will have an effect on the voltage across the inductor and thus on t_ON (t_OFF remains fixed).

The fixed off-time maintains a quasi-fixed frequency that provides better stability for the system over a wide range of input and output voltages than conventional boost converters. The TPS65142 topology has also the benefits of providing very good load and line regulations, and excellent line and load transient responses.

Figure 25. Boost Converter Block Diagram

7.3.1.1 Setting the Output Voltage

The output voltage is set by an external resistor divider. Typically, a minimum current of 50 µA flowing through the feedback divider is enough to cover the noise fluctuation. If 70 µA is chosen for higher noise immunity, the resistors shown in Figure 25 are then calculated as:

Equation 1.

where V_FBP = 1.240 V

7.3.2 Regulated Positive Charge Pump

The positive charge pump sets the voltage applied on the VGH input pin, up to 32 V in tripler mode configuration. The charge pump block regulates the VGH voltage by adjusting the drive current I_DRVP. Typically, a minimum current of 50 µA flowing through the feedback divider is usually enough to cover the noise fluctuation. If 70 µA is chosen for higher noise immunity, the resistors of the divider used to set the V_GH voltage are calculated as (refer to Figure 26):

Equation 2.

where V_FBP = 1.240 V

Figure 26. Block Diagram of the Positive Charge Pump Regulator

7.3.3 Negative Charge Pump

Figure 27 shows the block diagram of the negative charge pump. The negative charge pump needs to generate a voltage of –6 V to –7 V with a negative inverter or –12 V to –13 V with a negative doubler. The reference voltage from the REF pin is 3.15 V. The bias to the REF block comes from the SUP pin. The error amplifier is referenced to the ground. The V_GL can be set with the following equation:

Equation 3.

where V_REF = 3.12 V

Figure 27. Block Diagram of the Negative Charge Pump Regulator with a Negative Inverter Configuration

Figure 28. Negative Doubler Configuration for the Negative Charge Pump Regulator

7.3.4 Gate Voltage Shaping

The VGHM output is controlled by the VFLK logic input and the VDPM voltage level.

The VDPM pin allows the user to set a delay before the Gate Voltage Shaping starts. The voltage of the VDPM pin is zero volt at power on. When the output voltage of the AVDD boost converter rises above a power-good threshold, a power-good signal enables a 20-µA current source that charges the capacitor connected between the VDPM pin and the ground. When the VDPM-pin voltage rises to 1.24 V, the Gate Voltage Shaping is enabled.

The VFLK input controls the M1 and the M2 transistors, as shown in Figure 29, after the Gate Voltage Shaping is enabled:

When VFLK = “low”, M1 is turned on so VGHM is connected to the VGH input.

When VFLK = “high”, M2 is turned on so VGHM voltage is discharged through M2 and the resistor connected to the RE pin.

Figure 29. Block Diagram of the Gate Voltage Shaping Function

Figure 30. Gate Voltage Shaping Timing

7.3.5 VCOM Buffer

The VCOM Buffer power supply pin is the SUP pin connected to the AVDD boost converter V_S. To achieve good performance and minimize the output noise, a 1-µF ceramic bypass capacitor is required directly from the SUP pin to ground. The buffer is not designed to drive high capacitive loads; therefore, it is recommended to connect a series resistor at the output to provide stable operation when driving a high capacitive load. With a 3.3-Ω series resistor, a capacitive load of 10 nF can be driven, which is usually sufficient for typical LCD applications.

7.3.6 Reset

The device has an integrated reset function with an open-drain output capable of sinking 1 mA. The reset function monitors the voltage applied to its sense input V_(DET). As soon as the voltage on V_(DET) falls below the threshold voltage, V_(DET), of typically 1.1 V, the reset function asserts its reset signal by pulling XAO low. Typically, a minimum current of 50 µA flowing through the feedback divider is enough to cover the noise fluctuation. Therefore, to select R₁₂ and R₁₃ (see Figure 33), one has to set the input voltage limit (V_IN(LIM)) at which the reset function will pull XAO to low state. V_IN(LIM) must be higher than the UVLO threshold. If 70 µA is chosen,

Equation 4.

where V_DET = 1.1 V.

The XAO output is also controlled by the UVLO function. When the input voltage is below the UVLO threshold, XAO output is forced low until the input voltage is lower than 1.6 V. The XAO output is in an unknown state when the input voltage is below the 1.6 V threshold.

Figure 31. Voltage Detection and XAO Pin

When the input voltage VIN rises, once the voltage on VDET pin exceeds its threshold voltage plus the hysteresis, the XAO signal will go high.

The reset function is operational for V_IN ≥ 1.6 V.

The reset function is configured as a standard open-drain and requires a pull-up resistor. The resistor R_(XAO) (R₁₄ in Figure 33), which must be connected between the XAO pin output and a positive voltage V_X greater than 2 V – 'high' logic level can be chosen as follows:

Equation 5.

7.3.7 Under-voltage Lockout (UVLO)

The TPS65142 monitors both VIN and VBAT inputs for under-voltage lockout. When the VIN input in under its UVLO threshold, the whole IC is disabled to avoid mis-operation. When the VIN input rises above its UVLO threshold, all functions are enabled except the WLED driver. The WLED driver, including the WLED boost converter and the current sinks, will be enabled when the VBAT input is also higher than its UVLO threshold.

7.3.8 Thermal Shutdown

A thermal shutdown is implemented to prevent damages because of excessive heat and power dissipation. Typically the thermal shutdown threshold for the junction temperature is 150°C. When the thermal shutdown is triggered the device stops switching until the junction temperature falls below typically 136°C. Then the device starts switching again.

7.3.9 WLED Boost Regulator

The WLED boost regulator is a current-mode PWM regulator with internal loop compensation. The internal compensation ensures a stable output over the full input and output voltage range. The WLED boost regulator switches at fixed 1 MHz. The output voltage of the boost regulator is automatically set by the TPS65142 to minimize the voltage drop across the current-sink IFBx pins. The lowest IFB-pin voltage to regulated to 400 mV. When the output voltage is too close to the input, the WLED boost regulator may not be able to regulate the output due to the limitation of the minimum duty cycle. In that case, the user needs to increase the number of WLED in series or to include series ballast resistors to provide enough headroom for the boost converter to operate. The WLED boost regulator cannot regulate its output to a voltage below 15 V.

7.3.10 Current Sinks

The six current sink regulators can each provide a maximum of 25 mA. The IFB current must be programmed to the highest WLED current expected using an ISET-pin resistor with the following equation:

Equation 6.

where

K_(ISET) = Current multiple (1000 typical)
V_(ISET) = ISET pin voltage (1.229 V typical)
R_(ISET) = ISET-pin resistor value

The TPS65142 has built-in precise current sink regulators. The current matching error among 6 current sinks is below 2.5%. This means the differential values between the maximum and minimum currents of the six current sinks divided by the average current of the six is less than 2.5%.

7.3.11 Unused IFB Pins

If the application requires less than 6 WLED strings, one can easily disable unused IFBx pins by simply leaving the unused IFB pin open or shorting it to ground. If the IFB pin is open, the boost output voltage ramps up to V_O overvoltage threshold during start up. The IC then detects the zero current string and removes it from the feedback loop. If the IFB pin is shorted to ground, the IC detects the short immediately after WLED driver is enable, and the boost output voltage does not go up to V_O overvoltage threshold. Instead, it ramps to the regulation voltage after the soft start.

7.3.12 PWM Dimming

The WLED brightness is controlled by the PWM signal on the DCTRL pin. The frequency and duty cycle of the DCTRL signal is replicated on the IFB pin current. Keep the dimming frequency in the range of 100 Hz to 1 kHz to avoid screen flickering and to maintain dimming linearity. Screen flickering may occur if the dimming frequency is below the range. The minimum achievable duty cycle increases with the dimming frequency. For example, while a 0.1% dimming duty cycle, giving a 1000:1 dimming range, is achievable at 100 Hz dimming frequency, only 1% duty cycle, giving a 100:1 dimming range, is achievable with a 1-kHz dimming frequency, and 5% dimming duty cycle is achievable with 5 kHz dimming frequency. The device can work at high dimming frequency such as 20 kHz, but then only 15% duty cycle can be achieved. The TPS65142 is designed to minimize the AC ripple on the output capacitor during PWM dimming. Careful passive component selection is also critical to minimize AC ripple on the output capacitor.

7.3.13 Enabling the WLED Driver

The WLED driver (including the WLED boost converter and the six current sinks) is enabled when all following four conditions are satisfied:

1. the VBAT input voltage is higher than its under-voltage-lockout (UVLO) threshold;
2. the REF regulator output is higher than its power-good threshold;
3. the output voltage V_O is within 2 V of the input voltage V_BAT;
4. and the enable input from the EN pin is high.

Pulling the EN pin low shuts down the WLED driver.

7.3.14 Soft-Start of WLED Boost Regulator

Once the above four conditions are satisfied, the WLED boost converter begins the internal soft-start. The soft-start function gradually ramps up the reference voltage of the error amplifier to prevent the output-voltage over shoot and inrush current from the VBAT input.

7.3.15 Protection of WLED Driver

The TPS65142 has multiple protection mechanisms to secure the safe operation of the WLED driver.

7.3.16 Power Up/Down Sequence

The power up and power down sequences are shown in Figure 32.

The operation of the bias converters are gated by the UVLO of the VIN voltage. The start-up of the WLED boost converter is gated by the UVLO of the VBAT input, the power good of the REF output, the (VBAT – 2 V) and VO comparator output, and the EN input. The REF output is powered by the output of the AVDD boost converter through the SUP pin; and hence, the WLED boost converter will not start before the AVDD boost converter.

7.3.16.2 Power Down Sequence and LCD Discharge Function

The power down sequence of the bias section is as following. When the input voltage V_IN falls below a predefined threshold set by V_{(DET_THRESHOLD)}, XAO is driven low and the VGHM output is driven to V_GH. (Note that when V_IN falls below the UVLO threshold, all IC functions are disabled except XAO and VGHM outputs). Since VGHM is connected to VGH, it tracks the output of the positive charge pump as it decays. This feature, together with XAO, can be used to discharge the panel by turning on all the pixel TFTs and discharging them into the gradually decaying VGHM voltage. VHGM is held low during power-up.

The REF regulator will be disabled when V_IN falls below the UVLO threshold, hence, the WLED boost converter as well.

Figure 32. Power Up/Down Sequence