Refer to the PDF data sheet for device specific package drawings
The UCC27311A-Q1 is a robust gate driver designed to drive two N-channel MOSFETs in a half-bridge or synchronous buck configuration with an absolute maximum bootstrap voltage of 120V. Its 3.7A peak source and 4.5A peak sink current capability allows the UCC27311A-Q1 to drive large power MOSFETs with minimized switching losses during the transition through the Miller Plateau. The switching node (HS pin) can handle negative transient voltage, which allows the high-side channel to be protected from inherent negative voltages caused by parasitic inductance and stray capacitance.
The inputs are independent of supply voltage and are able to withstand -10V and +20V absolute maximum ratings. The low-side and high-side gate drivers are matched to 4ns between the turn on and turn off of each other and are controlled throught the LI and HI input pins respectively. An on-chip 120V rated bootstrap diode eliminates the need to add discrete bootstrap diodes. Undervoltage lockout (UVLO) is provided for both the high-side and the low-side drivers which provides symmetric turn on and turn off behavior and forces the outputs low if the drive voltage is below the specified threshold.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
UCC27311AQDRCRQ1 | DRC (VSON, 10) | 3mm × 3mm |
PIN | TYPE(3) | DESCRIPTION | |
---|---|---|---|
NAME | DRC | ||
EN | 6 | I | Enable input. When this pin is pulled high, it will enable the driver. If left floating or pulled low, it will disable the driver. A filter capacitor, typically 1-10nF, is recommended to be placed from EN to VSS to increase noise immunity in sensitive applications. |
HB | 3 | P | High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022µF to 0.1µF. The capacitor value is dependant on the gate charge of the high-side MOSFET and must also be selected based on speed and ripple criteria. |
HI | 7 | I | High-side input.(1) |
HO | 4 | O | High-side output. Connect to the gate of the high-side power MOSFET. |
HS | 5 | P | High-side source connection. Connect to source of high-side power MOSFET. Connect the negative side of bootstrap capacitor to this pin. |
LI | 8 | I | Low-side input.(1) |
LO | 10 | O | Low-side output. Connect to the gate of the low-side power MOSFET. |
VDD | 1 | P | Positive supply to the lower-gate driver. Decouple this pin to VSS (GND). Typical decoupling capacitor range is 0.22µF to 4.7µF (see (2)). |
VSS | 9 | G | Negative supply terminal for the device that is generally grounded. |
Thermal pad | Pad | — | Connect to a large thermal mass trace or GND plane to dramatically improve thermal performance. Pin VSS and the exposed thermal pad are internally connected. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VDD | Supply voltage | –0.3 | 20 | V | |
VHI, VLI | Input voltages on HI and LI | -10 | 20 | V | |
VEN | Input voltages on EN | Input voltages on EN | -10 | 20 | V |
VLO | Output voltage on LO | DC | –0.3 | VDD + 0.3 | V |
Repetitive pulse < 100 ns(2) | –2 | VDD + 0.3 | |||
VHO | Output voltage on HO | DC | VHS – 0.3 | VHB + 0.3 | V |
Repetitive pulse < 100 ns(2) | VHS – 2 | VHB + 0.3 | |||
VHS | Voltage on HS | DC | –1 | 120 | V |
Repetitive pulse < 100 ns(2) | –(28 – VDD) | 120 | |||
VHB | Voltage on HB | –0.3 | 120 | V | |
Voltage on HB-HS | –0.3 | 20 | V | ||
TJ | Operating junction temperature | –40 | 150 | °C | |
Tstg | Storage temperature | –65 | 150 | °C |