UCC2751x Single-Channel, High-Speed, Low-Side Gate Driver (With 4-A Peak Source and 4-A Peak Sink)

Device Information⁽¹⁾

The UCC2751x family of gate-driver products (Table 1) represent TI’s latest generation of single-channel low-side high-speed gate-driver devices featuring high-source/sink current capability, industry best-in-class switching characteristics and a host of other features (Table 2), all of which combine to ensure efficient, robust, and reliable operation in high-frequency switching power circuits.

Pin Functions – UCC27516

Pin Functions – UCC27517

8.1 Absolute Maximum Ratings^(1)(2)(3)

8.2 ESD Ratings

8.3 Recommended Operating Conditions

8.4 Thermal Information

8.5 Electrical Characteristics

8.6 Switching Characteristics

8.7 Typical Characteristics

Figure 5. Startup Current vs Temperature

Figure 7. Supply Current vs Temperature (Output In DC On/Off Condition)

Figure 9. Input Threshold vs Temperature

Figure 11. Output Pulldown Resistance vs Temperature

Figure 13. Fall Time vs Temperature

Figure 15. Operating Supply Current vs Frequency

Figure 17. Rise Time vs Supply Voltage

Figure 6. Operating Supply Current vs Temperature (Output Switching)

Figure 8. UVLO Threshold Voltage vs Temperature

Figure 10. Output Pullup Resistance vs Temperature

Figure 12. Rise Time vs Temperature

Figure 14. Input To Output Propagation Delay vs Temperature

Figure 16. Propagation Delays vs Supply Voltage

Figure 18. Fall Time vs Supply Voltage

9.1 Overview

The UCC2751x single-channel, high-speed, low-side gate-driver device can effectively drive MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, the UCC2751x device can source and sink high peak-current pulses into capacitive loads, offering rail-to-rail drive capability and extremely small propagation delay of 13 ns (typical). The UCC2751x device provides 4-A source, 4-A sink (symmetrical drive) peak-drive current capability. The UCC27511 device is designed to operate over a wide V_DD range of 4.5 to 18 V, and a wide temperature range of –40°C to 140°C.

Internal UVLO circuitry on the V_DD pin holds the output low outside V_DD operating range. The capability to operate at low voltage levels, such as below 5 V, along with best-in-class switching characteristics, is suited for driving emerging wide band-gap power-switching devices such as GaN power-semiconductor devices.

The UCC2751x device features a dual-input design which offers flexibility of implementing both inverting (IN– pin) and noninverting (IN+ pin) configuration with the same device. Either the IN+ or IN– pin can be used to control the state of the driver output. The unused input pin can be used for enable and disable functions. For system robustness, internal pullup and pulldown resistors on the input pins ensure that outputs are held low when the input pins are in floating condition. Therefore the unused input pin is not left floating and must be properly biased to ensure that driver output is in enabled for normal operation. The input pin threshold of the device is based on TTL and CMOS-compatible low-voltage logic which is fixed and independent of the V_DD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

9.2 Functional Block Diagrams

Figure 20. UCC27517 Functional Block Diagram

9.3 Feature Description

9.3.1 VDD and Undervoltage Lockout

The UCC2751x devices have internal UVLO protection feature on the VDD-pin supply-circuit blocks. Whenever the driver is in UVLO condition (for example when V_DD voltage is less than V_ON during power up and when V_DD voltage is less than V_OFF during power down), this circuit holds all outputs LOW, regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis helps prevent chatter when low V_DD-supply voltages have noise from the power supply and also when there are droops in the VDD-bias voltage when the system commences switching and there is a sudden increase in I_DD. The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics, is especially suited for driving emerging GaN wide-bandgap power-semiconductor devices.

For example, at power up, the UCC2751x driver output remains LOW until the V_DD voltage reaches the UVLO threshold. The magnitude of the OUT signal rises with V_DD until steady-state V_DD is reached. In the noninverting operation (PWM signal applied to IN+ pin) shown below, the output remains LOW until the UVLO threshold is reached, and then the output is in-phase with the input. In the inverting operation (PWM signal applied to IN- pin) shown below the output remains LOW until the UVLO threshold is reached, and then the output is out-phase with the input. In both cases, the unused input pin must be properly biased to enable the output. Note that in these devices the output turns to high-state only if IN+ pin is high and IN- pin is low after the UVLO threshold is reached.

Because the driver draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface-mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to the VDD to GND pins of the gate driver. In addition, a larger capacitor (such as 1 μF) with relatively low ESR should be connected in parallel and close proximity, in order to help deliver the high-current peaks required by the load. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels and switching frequencies in the application.

Figure 21. Power Up (Noninverting Drive)

Figure 22. Power Up (Inverting Drive)

9.3.5 Output Stage

The UCC27516 and UCC27517 devices can deliver 4-A source, 4-A sink (symmetrical drive) at VDD = 12 V. The output stage of the UCC27516 and UCC27517 devices are illustrated in Figure 23. The UCC27516 and UCC27517 devices features a unique architecture on the output stage which delivers the highest peak-source current when most needed during the Miller-plateau region of the power-switch turnon transition (when the power-switch drain/collector voltage experiences dV/dt). The device output stage features a hybrid pullup structure using a parallel arrangement of N-Channel and P-Channel MOSFET devices. By turning on the N-Channel MOSFET during a narrow instant when the output changes state from low to high, the gate-driver device delivers a brief boost in the peak-sourcing current enabling fast turnon.

Figure 23. UCC2751x Gate Driver Output Structure

The R_OH parameter (see Electrical Characteristics) is a DC measurement and is representative of the on-resistance of the P-Channel device only, because the N-Channel device is turned on only during output change of state from low to high. Thus the effective resistance of the hybrid pullup stage is much lower than what is represented by R_OH parameter. The pulldown structure is composed of a N-Channel MOSFET only. The R_OL parameter (see Electrical Characteristics), which is also a DC measurement, is representative of true impedance of the pulldown stage in the device. In the UCC27516 and UCC27517, the effective resistance of the hybrid pullup structure is approximately 1.4 × R_OL.

The driver-output voltage swings between VDD and GND providing rail-to-rail operation because of the MOS output stage which delivers very low dropout. The presence of the MOSFET-body diodes also offers low impedance to switching overshoots and undershoots. This means that in many cases, external Schottky-diode clamps may be eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either damage to the device or logic malfunction.

9.4 Device Functional Modes

10.1 Application Information

High-current gate-driver devices are required in switching power applications for a variety of reasons. In order to effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is employed between the PWM output of controllers and the gates of the power-semiconductor devices. Further, gate drivers are indispensable when there are times that the PWM controller cannot directly drive the gates of the switching devices. With advent of digital power, this situation is often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal, which is not capable of effectively turning on a power switch. A level-shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the power device and minimize conduction losses. Because traditional buffer-drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter-follower configurations, lack level-shifting capability, the circuits prove inadequate with digital power. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver physically close to the power switch, driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving gate-charge power losses into itself. Finally, emerging wide-bandgap power-device technologies, such as GaN based switches, which are capable of supporting very high switching frequency operation, are driving very special requirements in terms of gate-drive capability. These requirements include operation at low VDD voltages (5 V or lower), low propagation delays and availability in compact, low-inductance packages with good thermal capability. In summary gate-driver devices are extremely important components in switching power combining benefits of high-performance, low cost, component count and board space reduction with a simplified system design.

10.2 Typical Application

The UCC27516 and UCC27517 devices can be used in non-inverting and inverting driver configurations.

(IN- Is Grounded to the Enable Output)

Figure 24. Using Noninverting Input

(IN+ Is Tied to VDD Enable Output)

Figure 25. Using Inverting Input

10.2.3 Application Curves

VDD = 10 V

C(LOAD) = 1 nF

Figure 26. Typical Turnon Waveform

VDD = 10 V

C(LOAD) = 1 nF

Figure 27. Typical Turnoff Waveform

The bias supply voltage range for which the UCC27516 and UCC27517 device is rated to operate is from 4.5 V to 18 V. The lower end of this range is governed by the internal UVLO protection feature on the V_DD pin supply circuit blocks. Whenever the driver is in UVLO condition when the V_DD pin voltage is below the V(ON) supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is driven by the 20-V absolute maximum voltage rating of the V_DD pin of the device (which is a stress rating). Keeping a 2-V margin to allow for transient voltage spikes, the maximum recommended voltage for the V_DD pin is 18 V.

The UVLO protection feature also involves a hysteresis function. This means that when the V_DD pin bias voltage has exceeded the threshold voltage and the device begins to operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification V_DD(hys). While operating at or near the 4.5 V range, ensure that the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the device, to avoid triggering a device shutdown.

During system shutdown, the device operation continues until the V_DD pin voltage has dropped below the V_(OFF) threshold, which must be accounted for while evaluating system shutdown timing design requirements. Likewise, at system startup the device does not begin operation until the V_DD pin voltage has exceeded above the V_(ON) threshold. The quiescent current consumed by the internal circuit blocks of the device is supplied through the V_DD pin. Keep in mind that the charge for source current pulses delivered by the OUT pin is also supplied through the same V_DD pin. As a result, every time a current is sourced out of the output pin (OUT), a corresponding current pulse is delivered into the device through the V_DD pin. Therefore, ensure that local bypass capacitors are provided between the V_DD and GND pins, and located as close to the device as possible for the purpose of decoupling. A low ESR, ceramic surface mount capacitor is necessary. TI recommends using 2 capacitors; a 100-nF ceramic surface-mount capacitor which can be nudged very close to the pins of the device, and another surface-mount capacitor of few microfarads added in parallel.

12.1 Layout Guidelines

Proper PCB layout is extremely important in a high-current fast-switching circuit to provide appropriate device operation and design robustness. The UCC27516 and UCC27517 gate driver incorporates short-propagation delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of the power switch to facilitate voltage transitions very quickly. At higher VDD voltages, the peak-current capability is even higher (4-A/4-A peak current is at VDD = 12 V). Very high di/dt causes unacceptable ringing if the trace lengths and impedances are not well controlled. The following circuit layout guidelines are strongly recommended when designing with these high-speed drivers.

• Locate the driver device as close as possible to the power device in order to minimize the length of high-current traces between the output pins and the gate of the power device.
• Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal trace length to improve the noise filtering. These capacitors support high-peak current being drawn from VDD during turnon of power MOSFET. The use of low inductance SMD components such as chip resistors and chip capacitors is highly recommended.
• The turnon and turnoff current-loop paths (driver device, power MOSFET and VDD bypass capacitor) should be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is established in these loops at two instances – during turnon and turnoff transients, which will induce significant voltage transients on the output pin of the driver device and gate of the power switch.
• Wherever possible parallel the source and return traces, taking advantage of flux cancellation.
• Separate power traces and signal traces, such as output and input signals.
• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of the driver should be connected to the other circuit nodes such as source of power switch or the ground of PWM controller at one, single point. The connected paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance.
• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals during transition. The ground plane must not be a conduction path for any current loop. Instead the ground plane must be connected to the star-point with one single trace to establish the ground potential. In addition to noise shielding, the ground plane can help in power dissipation as well.
• In noisy environments, tying the unused input pin of UCC27516 and UCC27517 to VDD (in case of IN+) or GND (in case of IN–) using short traces to ensure that the output is enabled and to prevent noise from causing malfunction in the output is necessary.
• The UCC27516 device offers two ground pins, pin 2 and pin 3. Shorting the two pins together using the PCB trace is extremely important. The shortest trace should be located as close as possible to the device.

12.2 Layout Example

Figure 28. UCC27516DRS in Noninverting Configuration

Figure 29. UCC27517DBV in Noninverting Configuration

12.3 Thermal Considerations

The useful range of a driver is greatly affected by the drive-power requirements of the load and the thermal characteristics of the package. For a gate driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The thermal metrics for the driver package is summarized in Thermal Information. For detailed information regarding the thermal information table, refer to the Application Note from Texas Instruments entitled IC Package Thermal Metrics (SPRA953).

The UCC27516 and UCC27517 devices are offered in SOT-23, 5-pin package (DBV) and 3 mm × 3 mm, WSON 6-pin package with exposed thermal pad (DRS), respectively. The Thermal Information table summarizes the thermal performance metrics related to the two packages. R_θJA metric should be used for comparison of power dissipation between different packages. Under identical power dissipation conditions, the DRS package will maintain a lower die temperature than the DBV. The ψ_JT and ψ_JB metrics should be used when estimating the die temperature during actual application measurements.

The DRS is a better thermal package overall because of the exposed thermal pad and ability to sink heat to the PCB better than the DBV. The thermal pad in DRS package provides designers with an ability to create an excellent heat removal subsystem from the vicinity of the device, thus helping to maintain a lower junction temperature. This pad should be soldered to the copper on the printed circuit board directly underneath the device package. Then a printed circuit board designed with thermal lands and thermal vias completes a very efficient heat removal subsystem. In such a design, the heat is extracted from the semiconductor junction through the thermal pad, which is then efficiently conducted away from the location of the device on the PCB through the thermal network. This extraction helps to maintain a lower board temperature near the vicinity of the device leading to an overall lower device-junction temperature.

In comparison, for the DBV package, heat removal occurs primarily through the leads of the device and the PCB traces connected to the leads.

Note that the exposed pad in DRS package is not directly connected to any leads of the package. However, the DRS package is electrically and thermally connected to the substrate of the device which is the ground of the device. TI recommends to externally connect the exposed pads to GND in PCB layout for better EMI immunity.

12.4 Power Dissipation

Power dissipation of the gate driver has two portions as shown in Equation 1.

Equation 1.

The DC portion of the power dissipation is P_DC = I_Q x VDD where I_Q is the quiescent current for the driver. The quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference voltage, logic circuits, protections, and also any current associated with switching of internal devices when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-through etc). The UCC27516 and UCC27517 features very low quiescent currents (less than 1 mA, refer Figure 7) and contains internal logic to eliminate any shoot-through in the output-driver stage. Thus the effect of the P_DC on the total power dissipation within the gate driver can be safely assumed to be negligible.

The power dissipated in the gate-driver package during switching (P_SW) depends on the following factors:

• Gate charge required of the power device (usually a function of the drive voltage V_G, which is very close to input bias supply voltage VDD due to low V_OH drop-out).
• Switching frequency.
• Use of external-gate resistors.

When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias supply is fairly easy. The energy that must be transferred from the bias supply to charge the capacitor is given by Equation 2.

Equation 2.

where

• C_LOAD is load capacitor
• V_DD is bias voltage feeding the driver

There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss given by Equation 3.

Equation 3.

where

• ƒ_SW is the switching frequency

The switching load presented by a power MOSFET/IGBT is converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when charging a capacitor. This is done by using the equation, Q_G = C_LOAD x V_DD, to provide Equation 4 for power:

Equation 4.

This power P_G is dissipated in the resistive elements of the circuit when the MOSFET/IGBT is being turned on or turned off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component). Based on this simplified analysis, the driver power dissipation during switching is calculated in Equation 5.

Equation 5.

where

• R_OFF = R_OL
• R_ON (effective resistance of pullup structure) = 1.4 x R_OL

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13.4 Glossary

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