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  • UCC28C5x-Q1 Automotive Low-Power Current-Mode High-Performance PWM Controller for Si and SiC MOSFETs

    • SLUSEV2C June   2022  – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1

      PRODUCTION DATA  

  • CONTENTS
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  • UCC28C5x-Q1 Automotive Low-Power Current-Mode High-Performance PWM Controller for Si and SiC MOSFETs
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)
        2. 9.2.2.2  Primary Magnetizing Inductance of the Flyback Transformer (LM)
        3. 9.2.2.3  Number of Turns of the Flyback Transformer Windings
        4. 9.2.2.4  Current Sense Resistors (R24, R25) and Current Limiting
        5. 9.2.2.5  Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress
        6. 9.2.2.6  Primary-Side Current Stress and Input Capacitor Selection
        7. 9.2.2.7  Secondary-Side Current Stress and Output Capacitor Selection
        8. 9.2.2.8  VDD Capacitors (C12, C18)
        9. 9.2.2.9  Gate Drive Network (R14, R16, Q6)
        10. 9.2.2.10 VREF Capacitor (C18)
        11. 9.2.2.11 RT/CT Components (R12, C15)
        12. 9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)
        13. 9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
        14. 9.2.2.14 Voltage Feedback Compensation
          1. 9.2.2.14.1 Power Stage Gain, Poles, and Zeroes
          2. 9.2.2.14.2 Compensation Components
          3. 9.2.2.14.3 Bode Plots and Stability Margins
          4. 9.2.2.14.4 Stability Measurements
      3. 9.2.3 Application Curves
    3. 9.3 PCB Layout Recommendations
      1. 9.3.1 PCB Layout Routing Examples
    4. 9.4 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
  12. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • D|8
    • MSOI002K
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • slusev2c_oa
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

UCC28C5x-Q1 Automotive Low-Power Current-Mode High-Performance PWM Controller for Si and SiC MOSFETs

1 Features

  • Undervoltage lockout options to support both Si and SiC MOSFET applications

  • 30-V VDD absolute maximum voltage

  • 1-MHz maximum Fixed frequency oeration
  • 50-μA startup current, 75-μA maximum
  • Low operating current : 1.3 mA at fOSC = 52 kHz
  • High operating TJ : 150℃ maximum
  • Fast 35-ns cycle-by-cycle over-current limiting
  • ±1-A peak driving current
  • Rail-to-rail output:
    • 25-ns rise time
    • 20-ns fall time
  • ±1% accurate 2.5-V error amplifier reference

  • Pin-to-pin compatible and drop-in replacement for UCC28C4x-Q1

  • Functional Safety-Capable
    • Documentation available to aid functional safety system design
  • AEC-Q100 qualified with the following results
    • Device temperature grade 1: -40°C to 125°C
    • Device HBM classification level 2: ±2 kV
    • Device CDM classification level C4B: 750 V

2 Applications

  • Traction inverter HV to LV backup supply
  • OBC and DC/DC converter isolated bias power supply
  • HVAC compressor HV isolated power supply
  • Single-ended DC converters in AC and DC EV charging equipment

3 Description

The UCC28C5x-Q1 family of devices are high performance current-mode PWM controllers which can be used to drive both Si and SiC MOSFETs in various applications. The UCC28C5x-Q1 family is a more efficient and robust version of the UCC28C4x-Q1.

The UCC28C5x-Q1 family has new UVLO thresholds that allow for reliable SiC MOSFET operation (UCC28C56-59-Q1), in addition to existing UVLO thresholds for continued Si MOSFET support (UCC28C50-55-Q1).

VDD absolute maximum voltage rating is extended from 20 V to 30 V for optimally driving the gate of 20-Vgs, 18-Vgs, or 15-Vgs SiC MOSFETs, while also allowing for the exclusion of an external LDO.

Device Performance Improvements
PARAMETERUCC28C4x-Q1UCC28C5x-Q1
Supply current at 52 kHz2.3 mA1.3 mA
Startup current (max)100 µA75 µA
VDD abs max20 V30 V
Reference Voltage Accuracy ±2% ±1%
UVLO and DMAX for Si FET6 options6 options
UVLO and DMAX for SiC FETnone6 options
  1. For all available packages, see the orderable addendum at the end of the data sheet.
Figure 3-1 Typical Automotive Application

4 Revision History

Changes from Revision B (February 2023) to Revision C (March 2023)

  • Initial release of the UCC28C58-Q1 deviceGo
  • Updated Available Options TableGo
  • Added Link to Technical Support Go

Changes from Revision A (October 2022) to Revision B (February 2023)

  • Initial release of the UCC28C55-Q1, UCC28C56L-Q1, UCC28C57L-Q1 and UCC28C57H-Q1 deviceGo

Changes from Revision * (June 2022) to Revision A (October 2022)

  • Initial release of the UCC28C59-Q1 deviceGo
  • Updated Available Options TableGo
  • Updated Electrical Characteristics section Go
  • Updated Typical Characteristics section Go
  • Updated Application Information section Go

5 Device Comparison Table

UVLOMAXIMUM DUTY CYCLETEMPERATURE (TA)
TURN ON AT 14.5 V
TURN OFF AT 9 V
SUITABLE FOR OFF-LINE APPLICATIONS		TURN ON AT 8.4 V
TURN OFF AT 7.6 V
SUITABLE FOR DC/DC APPLICATIONS		TURN ON AT 7 V
TURN OFF AT 6.6 V
SUITABLE FOR BATTERY APPLICATIONS
UCC28C52QDRQ1UCC28C53QDRQ1UCC28C50QDRQ1100%–40°C to 125°C
UCC28C54QDRQ1UCC28C55QDRQ1UCC28C51QDRQ150%
UVLOMAXIMUM DUTY CYCLETEMPERATURE (TA)
TURN ON AT 18.8 V
TURN OFF AT 15.5V
Suitable for HV applications using GEN-I SiC MOSFET

TURN ON AT 18.8 V TURN OFF AT 14.5V
Suitable for HV applications using GEN-II SiC MOSFET

TURN ON AT 16 V TURN OFF AT 12.5V
Suitable for HV applications using GEN-III SiC MOSFET

UCC28C56HQDRQ1UCC28C56LQDRQ1UCC28C58QDRQ1100%–40°C to 125°C
UCC28C57HQDRQ1UCC28C57LQDRQ1UCC28C59QDRQ150%
Device Information1
PART NUMBERPACKAGEBODY SIZE (NOM)
UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1SOIC (8)4.90 mm × 3.91 mm
UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1
UCC28C56H-Q1, UCC28C56L-Q1
UCC28C57H-Q1, UCC28C57L-Q1
UCC28C58-Q1, UCC28C59-Q1

6 Pin Configuration and Functions

Figure 6-1 D Package8-Pin SOICTop View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
COMP 1 O This pin provides the output of the error amplifier for compensation. In addition, the COMP pin is frequently used as a control port, by utilizing a secondary-side error amplifier to send an error signal across the secondary-primary isolation boundary through an opto-isolator. The error amplifier is internally current limited so the user can command zero duty cycle by externally forcing COMP to GND.
CS 3 I Primary-side current sense pin. The current sense pin is the noninverting input to the PWM comparator. Connect to current sensing resistor. This signal is compared to a signal proportional to the error amplifier output voltage. The PWM uses this to terminate the OUT switch conduction. A voltage ramp can be applied to this pin to run the device with a voltage mode control configuration.
FB 2 I This pin is the inverting input to the error amplifier. FB is used to control the power converter voltage-feedback loop for stability. The noninverting input to the error amplifier is internally trimmed to 2.5 V ±1%.
GND 5 — Ground return pin for the output driver stage and the logic level controller section.
OUT 6 O The output of the on-chip drive stage. OUT is intended to directly drive a MOSFET. The OUT pin in the UCC28C50-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C56H/L-Q1, and UCC28C58-Q1 is the same frequency as the oscillator, and can operate near 100% duty cycle. In the UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1, UCC28C57H/L-Q1, and UCC28C59-Q1, the frequency of OUT is one-half that of the oscillator due to an internal T flipflop. This limits the maximum duty cycle to < 50%. Peak currents of up to 1 A are sourced and sunk by this pin. OUT is actively held low when VDD is below the turn-on threshold.
RT/CT 4 I/O

Fixed frequency oscillator set point. Connect timing resistor (RRT) to VREF and timing capacitor (CCT) to GND from this pin to set the switching frequency. For best performance, keep the timing capacitor lead to the device GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions. The switching frequency (fSW) of the UCC28C50-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C56H/L and UCC28C58 gate drive is equal to fOSC; the switching frequency of the UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1, UCC28C57H/L-Q1, and UCC28C59-Q1 is equal to half of the fOSC.
VDD 7 I Analog controller bias input that provides power to the device. Total VDD current is the sum of the quiescent VDD current and the average OUT current. A bypass capacitor, typically 0.1 µF, connected directly to GND with minimal trace length, is required on this pin. Additional capacitance at least 10 times greater than the gate capacitance of the main switching FET used in the design and 10 times greater than the capacitance on the VREF pin are also required on VDD.
VREF 8 O 5-V reference voltage. VREF is used to provide charging current to the oscillator timing capacitor through the timing resistor. It is important for reference stability that VREF is bypassed to GND with a ceramic capacitor connected as close to the pin as possible. A minimum value of 0.1 µF ceramic is required. Additional VREF bypassing is required for external loads on VREF. No external voltage higher than specified VREF is allowed to superimposed to VREF pin Since VREF is an ouput.

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2)
MINMAXUNIT
Input voltageVDD30V
Input currentIVDD30mA
Output drive current (peak)±1A
Output energy (capacitive load), EOUT5µJ
Analog input voltageCOMP, CS, FB, RT/CT–0.36.3V
Output driver voltageOUT–0.330
Reference voltageVREF7
Error amplifier output sink currentCOMP10mA
Total power dissipation at TA = 25°CD package72.3°C/W
Lead temperature (soldering, 10 s), TLEAD300°C
Operating junction temperature, TJ–40150°C
Storage temperature, Tstg–65150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 7.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND pin. Currents are positive into and negative out of the specified terminals.

7.2 ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per AEC Q100-002(1)±2000V
Charged-device model (CDM), per AEC Q100-011 Section 7.2±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINMAXUNIT
VVDDInput voltage28V
VOUTOutput driver voltage28V
IOUTAverage output driver current(1)200mA
IOUT(VREF)Reference output current(1)–20mA
TJOperating junction temperature(1)UCC28C5x-Q1–40

150

°C

TA

Operating ambient temperature(1)UCC28C5x-Q1–40

125

°C
(1) TI recommends against operating the device under conditions beyond those specified in this table for extended periods of time.

7.4 Thermal Information

THERMAL METRIC(1) UCC28C5x-Q1 UNIT
D (SOIC) 8 PINS
RθJA Junction-to-ambient thermal resistance 128.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 71.7 °C/W
RθJB Junction-to-board thermal resistance 72.3 °C/W
ψJT Junction-to-top characterization parameter 23.4 °C/W
ψJB Junction-to-board characterization parameter 71.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor anddevicePackage Thermal Metrics application report.

7.5 Electrical Characteristics

VVDD = 20 V (1)(for UCC28C56H/L-Q1, UCC28C57H/L-Q1 and UCC28C58/9-Q1), VVDD = 15 V(1) (for the rest), RRT = 10 kΩ, CCT = 3.3 nF, CVDD = 0.1 µF and no load on the outputs, TJ = –40°C to 150°C (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
REFERENCE
VVREFVREF voltage, initial accuracyIOUT = 1 mA4.9555.05V
Line regulationVVDD = 12 V to 25 V0.220mV
Load regulation1 mA to 20 mA325mV
Temperature stabilitySee (2)0.20.4mV/°C
Total output variationSee (2)4.825.18V
VREF noise voltage10 Hz to 10 kHz, TJ = 25°C, see (2)50µV
Long term stability1000 hours, TJ = 150°C, see (2)525mV
IVREFOutput short circuit (source current)304555mA
OSCILLATOR
fOSCInitial accuracyTJ = 25°C, see (3)50.55355kHz
TJ = Full Range, see (3)50.557kHz
Voltage stability12 V ≤ VVDD ≤ 25 V0.2%1%
Temperature stabilityTJ(MIN) to TJ(MAX), see (2)1%2.5%
AmplitudeRT/CT pin peak-to-peak voltage1.9V
Discharge currentTJ = 25°C, VRT/CT = 2 V, see (4)7.78.49mA
TJ = Full Range, VRT/CT = 2 V, see (4)7.28.49.5
ERROR AMPLIFIER
VFBFeedback input voltage, initial accuracyTJ = 25°C, VCOMP = 2.5 V2.4752.52.525V
Feedback input voltage, total variationTJ = Full Range, VCOMP = 2.5 V2.452.52.55V
IFBInput bias currentVFB = 5 V, (sourcing current)0.12µA
AVOLOpen-loop voltage gain2 V ≤ VOUT ≤ 4 V6590dB
Unity gain bandwidthSee (2)11.5MHz
PSRRPower supply rejection ratio12 V ≤ VVDD ≤ 25 V60dB
Output sink currentVFB = 2.7 V, VCOMP = 1.1 V214mA
Output source currentVFB = 2.3 V, VCOMP = 5 V, (sourcing current)0.51mA
VOHHigh-level COMP voltageVFB = 2.7 V, RCOMP = 15 kΩ COMP to GNDVREF–0.2V
VOLLow-level COMP voltageVFB = 2.7 V, RCOMP = 15 kΩ COMP to VREF0.11.1V
CURRENT SENSE
ACSGainTJ = 25°C, See (5)2.8533.15V/V
TJ = Full Range, See (5)2.7533.15V/V
VCSMaximum input signalVFB < 2.4 V0.911.1V
PSRRPower supply rejection ratioVVDD = 12 V to 25 V(2)(5)70dB
ICSInput bias current (source current)0.12µA
tDCS to output delay3570ns
COMP to CS offsetVCS = 0 V1.15V
OUTPUT
VOUT(low)RDS(on) pulldownISINK = 200 mA5.515Ω
VOUT(high)RDS(on) pullupISOURCE = 200 mA1025Ω
tRISERise tImeTJ = 25°C, COUT = 1 nF2550ns
tFALLFall tImeTJ = 25°C, COUT = 1 nF2040ns
UNDERVOLTAGE LOCKOUT
VDDONStart threshold(6)UCC28C52-Q1, UCC28C54-Q113.514.515.5V
UCC28C53-Q1, UCC28C55-Q17.88.49
UCC28C50-Q1, UCC28C51-Q16.577.5

UCC28C56H-Q1, UCC28C57H-Q1

17.6

18.8

20

UCC28C56L-Q1, UCC28C57L-Q1

17.6

18.8

20

UCC28C58-Q1, UCC28C59-Q1

14.8

16

17.2

VDDOFFMinimum operating voltage (6)UCC28C52-Q1, UCC28C54-Q18910V
UCC28C53-Q1, UCC28C55-Q177.68.2
UCC28C50-Q1, UCC28C51-Q16.16.67.1
UCC28C56H-Q1, UCC28C57H-Q1

15

15.5

16

UCC28C56L-Q1, UCC28C57L-Q1

13.95

14.5

15

UCC28C58-Q1, UCC28C59-Q1

12

12.5

13

VDDHystVDDON - VDDOFF(6)

UCC28C52-Q1, UCC28C54-Q1

5.4

5.5

V

UCC28C53-Q1, UCC28C55-Q1

0.8

0.9

UCC28C51-Q1, UCC28C50-Q1

0.4

0.5

UCC28C56H-Q1, UCC28C57H-Q1

2.6

3.3

UCC28C56L-Q1, UCC28C57L-Q1

3.65

4.3

UCC28C58-Q1, UCC28C59-Q1

2.8

3.5

PWM
DMAXMaximum duty cycleUCC28C52-Q1, UCC28C53-Q1, UCC28C50-Q1, VFB < 2.4 V94%96%
UCC28C56H-Q1, UCC28C56L-Q1, UCC28C58-Q1, VFB < 2.4 V
UCC28C54-Q1, UCC28C55-Q1, UCC28C51-Q1, VFB < 2.4 V47%48%
UCC28C57H-Q1, UCC28C57L-Q1, UCC28C59-Q1, VFB < 2.4 V
DMINMinimum duty cycleVFB > 2.6 V0%
CURRENT SUPPLY
ISTART-UPStart-up currentVVDD = VDDON – 0.5 V50

75

µA
IVDDOperating supply currentVFB = VCS = 0 V1.3

2

mA
(1) Adjust VVDD above the start threshold before setting at 20 V for UCC28C56H/L-Q1, UCC28C57H/L-Q1 and UCC28C58/9-Q1, and 15.5 V for the rest family.
(2) Ensured by design. Not production tested.
(3) Output frequencies of the UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1, UCC28C57H/L-Q1, and the UCC28C59-Q1 are half the oscillator frequency.
(4) Oscillator discharge current is measured with RRT = 10 kΩ to VREF.
(5) Parameter measured at trip point of latch with VFB = 0 V. Gain is defined as ACS = ΔVCOMP / ΔVCS , 0 V ≤ VCS ≤ 900 mV.
(6) VDDON, VDDOFF, and VREF are tracking each other in the same direction, e.g., min VDDOFF is due to min VDDON.

7.6 Typical Characteristics

GUID-7F66B2E8-321D-4EE3-A511-1FA2CACF9119-low.gifFigure 7-1 Oscillator Frequency vs Timing Resistance and Capacitance
GUID-085CBE7B-C7AF-4D49-98CF-54EDF3C5563A-low.gif
Figure 7-3 Error Amplifier Frequency Response
Group 1: UCC28C50-Q1 to UCC28C55-Q1Group 2: UCC28C56H-Q1 to UCC28C59-Q1
Figure 7-5 Reference Voltage vs Temperature
Group 1: UCC28C50-Q1 to UCC28C55-Q1Group 2: UCC28C56H-Q1 to UCC28C59-Q1
Figure 7-7 Reference Short-Circuit Current vs Temperature
GUID-4B6E3F22-D4F9-4015-A3FA-1C4321E47796-low.gif
UCC28C52-Q1 and UCC28C54-Q1
Figure 7-9 Undervoltage Lockout vs Temperature
GUID-4314F1CB-FDC7-4C58-AC0F-EB95ABEF45CE-low.gif
UCC28C50-Q1 and UCC28C51-Q1
Figure 7-11 Undervoltage Lockout vs Temperature
UCC28C56L-Q1 and UCC28C57L-Q1
Figure 7-13 Undervoltage Lockout vs Temperature
Figure 7-15 Supply Current vs Oscillator Frequency
GUID-9DE6F354-07A5-434A-9D30-61A6ACAD8EF8-low.gifFigure 7-17 Output Rise Time and Fall Time vs Temperature
GUID-C6FF4B06-3FA6-427C-873F-43C057A572DB-low.gif
UCC28C50-Q1, UCC28C52-Q1, UCC28C53-Q1,

UCC28C56H/L-Q1, and UCC28C58-Q1

Figure 7-19 Maximum Duty Cycle vs Temperature
Group 1: UCC28C50-Q1 to UCC28C55-Q1Group 2: UCC28C56H-Q1 to UCC28C59-Q1
Figure 7-21 Current Sense Threshold Voltage vs Temperature
Group 1: UCC28C50-Q1 to UCC28C55-Q1Group 2: UCC28C56H-Q1 to UCC28C59-Q1
Figure 7-2 Oscillator Discharge Current vs Temperature
VCS = 0Group 1: UCC28C50-Q1 to UCC28C55-Q1Group 2: UCC28C56H-Q1 to UCC28C59-Q1
Figure 7-4 COMP to CS Offset Voltage vs Temperature
Group 1: UCC28C50-Q1 to UCC28C55-Q1Group 2: UCC28C56H-Q1 to UCC28C59-Q1
Figure 7-6 Error Amplifier Reference Voltage vs Temperature
GUID-6E1AE9A9-3E2F-4B73-89B4-E7010867675C-low.gifFigure 7-8 Error Amplifier Input Bias Current vs Temperature
GUID-5B652379-CBA4-47B1-93FD-E7484A35BF9A-low.gif
UCC28C53-Q1 and UCC28C55-Q1
Figure 7-10 Undervoltage Lockout vs Temperature
UCC28C56H-Q1 and UCC28C57H-Q1
Figure 7-12 Undervoltage Lockout vs Temperature
UCC28C58-Q1 and UCC28C59-Q1
Figure 7-14 Undervoltage Lockout vs Temperature
Group 1: UCC28C50-Q1 to UCC28C55-Q1Group 2: UCC28C56H-Q1 to UCC28C59-Q1
Figure 7-16 Supply Current vs Temperature
GUID-CF39C555-9DF9-4071-B99A-1F964D876E54-low.gifFigure 7-18 Maximum Duty Cycle vs Oscillator Frequency
GUID-3B9401BD-2480-477D-B19C-D1EA0F5A2447-low.gif
UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C57H/L-Q1, and UCC28C59-Q1

Figure 7-20 Maximum Duty Cycle vs Temperature
GUID-74156948-0C9C-480E-A662-F2EC9153DF3D-low.gifFigure 7-22 Current Sense to Output Delay Time vs Temperature

8 Detailed Description

8.1 Overview

The UCC28C5x-Q1 series of control integrated circuits provide the features necessary to implement AC-DC or DC‑to-DC fixed-frequency current-mode control schemes with a minimum number of external components. Protection circuitry includes undervoltage lockout (UVLO) and current limiting. Internally implemented circuits include a start-up current of less than 75 µA, a precision reference trimmed for accuracy at the error amplifier input, logic to ensure latched operation, a pulse-width modulation (PWM) comparator that also provides current-limit control, and an output stage designed to source or sink high-peak current. The output stage, suitable for driving N-channel MOSFETs, is low when it is in the OFF state. The oscillator contains a trimmed discharge current that enables accurate programming of the maximum duty cycle and dead time limit, making this device suitable for high-speed applications.

Major differences between members of this series are the UVLO thresholds, acceptable ambient temperature range, and maximum duty cycle and frequency. Typical UVLO thresholds of 14.5 V (ON) and 9 V (OFF) on the UCC28C52-Q1 and UCC28C54-Q1 devices make them ideally suited to off-line AC-DC applications. The corresponding typical thresholds for the UCC28C53-Q1 and UCC28C55-Q1 devices are 8.4-V (ON) and 7.6-V (OFF), making them ideal for use with regulated input voltages used in DC-DC applications. The UCC28C50-Q1 and UCC28C51-Q1 feature a start-up threshold of 7 V and a turnoff threshold of 6.6 V (OFF), which makes them suitable for battery- powered applications. The UCC28C56H/L-Q1, UCC28C57H/L-Q1, UCC28C58-Q1 and UCC28C59-Q1 operate with higher start-up thresholds for them suitably to work with SiC MOSFETs which often being used in high-voltage and high-power traction inverter applications. The UCC28C56H-Q1 and UCC28C57H-Q1 are with a start-up threshold 18.8-V (ON) and 15.5-V (OFF). The UCC28C56L-Q1 and UCC28C57L-Q1 are with a start-up threshold 18.8-V (ON) and 14.5-V (OFF). The UCC28C58-Q1 and UCC28C59-Q1 are with a start-up threshold 16-V (ON) and 12.5-V (OFF). The UCC28C50-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C56H/L-Q1 and UCC28C58-Q1 devices operate to duty cycles approaching 100%. The UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1, UCC28C57H/L-Q1 and UCC28C59-Q1 obtain a duty cycle from 0% to 50% by the addition of an internal toggle flip-flop, which blanks the output off every other clock cycle. The UCC28C5x series is specified for operation from –40°C to 125°C. The switching frequency (fSW) of the UCC28C50-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C56H/L-Q1 and UCC28C58-Q1 gate drive is equal to fOSC; the switching frequency of the UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1, UCC28C57H/L-Q1 and UCC28C59-Q1 is equal to half of the fOSC.

The UCC28C5x-Q1 series are an enhanced replacement with pin-to-pin compatibility to the BiCMOS UCC28C4x- Q1 families. The new series offers improved performance when compared to older bipolar devices and other competitive BiCMOS devices with similar functionality. These improvements generally consist of tighter specification limits that are a subset of the older product ratings, maintaining drop-in capability. In new designs, these improvements can reduce the component count or enhance circuit performance when compared to the previously available devices.

 
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