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  • UCCx8C5x Low-Power Current-Mode High-Performance PWM Controller for Si and SiC MOSFETs

    • SLUSER8C June   2022  – March 2023 UCC28C50 , UCC28C51 , UCC28C52 , UCC28C53 , UCC28C54 , UCC28C55 , UCC28C56H , UCC28C56L , UCC28C57H , UCC28C57L , UCC28C58 , UCC28C59 , UCC38C50 , UCC38C51 , UCC38C52 , UCC38C53 , UCC38C54 , UCC38C55

      PRODUCTION DATA  

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  • UCCx8C5x Low-Power Current-Mode High-Performance PWM Controller for Si and SiC MOSFETs
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft-Start Timing
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Input Bulk Capacitor and Minimum Bulk Voltage
        2. 9.2.2.2  Transformer Turns Ratio and Maximum Duty Cycle
        3. 9.2.2.3  Transformer Inductance and Peak Currents
        4. 9.2.2.4  Output Capacitor
        5. 9.2.2.5  Current Sensing Network
        6. 9.2.2.6  Gate Drive Resistor
        7. 9.2.2.7  VREF Capacitor
        8. 9.2.2.8  RT/CT
        9. 9.2.2.9  Start-Up Circuit
        10. 9.2.2.10 Voltage Feedback Compensation
          1. 9.2.2.10.1 Power Stage Poles and Zeroes
          2. 9.2.2.10.2 Slope Compensation
          3. 9.2.2.10.3 Open-Loop Gain
          4. 9.2.2.10.4 Compensation Loop
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Precautions
        2. 9.4.1.2 Feedback Traces
        3. 9.4.1.3 Bypass Capacitors
        4. 9.4.1.4 Compensation Components
        5. 9.4.1.5 Traces and Ground Planes
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
  12. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • D|8
    • MSOI002K
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sluser8c_oa
  • sluser8c_pm
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DATA SHEET

UCCx8C5x Low-Power Current-Mode High-Performance PWM Controller for Si and SiC MOSFETs

1 Features

  • Undervoltage lockout options to support both Si and SiC MOSFET applications
  • 30-V VDD absolute maximum voltage
  • 1-MHz maximum fixed frequency operation
  • 50-μA startup current, 75-μA maximum
  • Low operating current: 1.3 mA (at fOSC = 52 kHz)
  • Fast 35-ns, cycle-by-cycle overcurrent limiting
  • ±1-A peak driving current
  • Rail-to-rail output
    • 25-ns rise time
    • 20-ns fall time
  • ±1% accurate 2.5-V error amplifier reference
  • Pin-to-pin compatible and drop-in replacement for UCCx8C4x
  • Functional Safety-Capable
    • Documentation available to aid functional safety system design

2 Applications

  • General purpose single-ended DC-DC or off-line isolated power converters
  • Auxiliary power supply for solar power inverters, motor drives, energy storage systems
  • Isolated power supply for EV charging stations

3 Description

The UCCx8C5x family of devices are high-performance current-mode PWM controllers that can drive both Si and SiC MOSFETs in various applications. The UCCx8C5x family is a more efficient and robust version of the UCCx8C4x.

The UCCx8C5x family has new UVLO thresholds that allow for reliable SiC MOSFET operation (UCC28C56-59), in addition to existing UVLO thresholds for continued Si MOSFET support (UCCx8C50-55).

VDD absolute maximum voltage rating is extended from 20 V to 30 V for optimally driving the gate of 20-Vgs, 18-Vgs, or 15-Vgs SiC MOSFETs, while also allowing for the exclusion of an external LDO.

Device Performance Improvements
PARAMETERUCCx8C4xUCCx8C5x
Supply current at 52 kHz2.3 mA1.3 mA
Startup current (max)100 µA75 µA
VDD abs max20 V30 V
Reference Voltage Accuracy±2%±1%
UVLO and DMAX for Si FET6 options6 options
UVLO and DMAX for SiC FETnone6 options
Smallest package optionVSSOP (8)VSSOP (8)

The UCCx8C5x family is offered in 8-pin VSSOP (DGK), and 8-pin SOIC (D) packages.

Device Information
PART NUMBERPACKAGE(1)BODY SIZE (NOM)
UCC28C50, UCC28C51
UCC28C52, UCC28C53,
UCC28C54, UCC28C55,
UCC38C50, UCC38C51
UCC38C52, UCC38C53
UCC38C54, UCC38C55		SOIC (8)3.91 mm × 4.90 mm
VSSOP (8)3.00 mm × 3.00 mm
UCC28C56H, UCC28C56L
UCC28C57H, UCC28C57L,
UCC28C58, UCC28C59		SOIC (8)3.91 mm × 4.90 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20221102-SS0I-708N-CNP5-HV7QXLTZPQC1-low.svgSimplified Application

4 Revision History

Changes from Revision B (February 2023) to Revision C (March 2023)

  • Initial release of the UCC28C56L, UCC38C53, and UCC38C55 devicesGo

Changes from Revision A (October 2022) to Revision B (February 2023)

  • Initial release of the UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C57H, UCC28C57L, UCC38C50, UCC38C51, UCC38C52, and UCC38C54 deviceGo
  • Corrected Figure 8-5 Oscillator Synchronization Circuit Go

5 Device Comparison Table

UVLOJunction Temperature (TJ) (°C)Maximum duty cycle
Turn on at 14.5 V
Turn off at 9 V
for off-line applications		Turn on at 8.4 V
Turn off at 7.6 V
for dc/dc applications		Turn on at 7 V
Turn off at 6.6 V
for battery applications
UCC28C52UCC28C53UCC28C50–40 to 125100%
UCC38C52UCC38C53UCC38C500 to 85
UCC28C54UCC28C55UCC28C51–40 to 12550%
UCC38C54UCC38C55UCC38C510 to 85
UVLOJunction
Temperature (TJ) (°C)		Maximum duty cycle
Turn on at 18.8 V
Turn off at 15.5 V
Suitable for HV applications using GEN-I SiC MOSFET		Turn on at 18.8 V
Turn off at 14.5 V
Suitable for HV applications using GEN-II SiC MOSFET		Turn on at 16 V
Turn off at 12.5 V
Suitable for HV applications using GEN-III SiC MOSFET
UCC28C56HUCC28C56LUCC28C58–40 to 125100%
UCC28C57HUCC28C57LUCC28C59–40 to 12550%

6 Pin Configuration and Functions

GUID-A0F28CFE-F7AF-4839-A226-C4597D6FB385-low.svgFigure 6-1 D Package 8-Pin SOIC (Top View)
GUID-4B1EB7C8-C869-4B62-8002-F21D86B41510-low.svgFigure 6-2 DGK Package, 8-Pin VSSOP (Top View)
Table 6-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
COMP1OThis pin provides the output of the error amplifier for compensation. In addition, the COMP pin is frequently used as a control port, by utilizing a secondary-side error amplifier to send an error signal across the secondary-primary isolation boundary through an opto-isolator. The error amplifier is internally current limited so the user can command zero duty cycle by externally forcing COMP to GND.
CS3IPrimary-side current sense pin. The current sense pin is the noninverting input to the PWM comparator. Connect to current sensing resistor. This signal is compared to a signal proportional to the error amplifier output voltage. The PWM uses this to terminate the OUT switch conduction. A voltage ramp can be applied to this pin to run the device with a voltage mode control configuration.
FB2IThis pin is the inverting input to the error amplifier. FB is used to control the power converter voltage-feedback loop for stability. The noninverting input to the error amplifier is internally trimmed to 2.5 V ± 1%.
GND5—Ground return pin for the output driver stage and the logic level controller section.
OUT6OThe output of the on-chip drive stage. OUT is intended to directly drive a MOSFET. The OUT pin in the UCCx8C50, UCCx8C52, UCCx8C53, UCC28C56H/L and UCC28C58 is the same frequency as the oscillator, and can operate near 100% duty cycle. In the UCCx8C51, UCCx8C54, and UCCx8C55, UCC28C57H/L and UCC28C59, the frequency of OUT is one-half that of the oscillator due to an internal T flipflop. This limits the maximum duty cycle to < 50%. Peak currents of up to 1 A are sourced and sunk by this pin. OUT is actively held low when VDD is below the turn-on threshold.
RT/CT4I/OFixed frequency oscillator set point. Connect timing resistor (RRT) to VREF and timing capacitor (CCT) to GND from this pin to set the switching frequency. For best performance, keep the timing capacitor lead to the device GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions. The switching frequency (fSW) of the UCCx8C50, UCCx8C52, UCCx8C53, UCC28C56H/L and UCC28C58 gate drive is equal to fOSC; the switching frequency of the UCCx8C51, UCCx8C54, and UCCx8C55, UCC28C57H/L and UCC28C59 is equal to half of the fOSC.
VDD7IAnalog controller bias input that provides power to the device. Total VDD current is the sum of the quiescent VDD current and the average OUT current. A bypass capacitor, typically 0.1 µF, connected directly to GND with minimal trace length, is required on this pin. Additional capacitance at least 10 times greater than the gate capacitance of the main switching FET used in the design and at least 10 times greater than the capacitance on the VREF pin used in the design are also required on VDD.
VREF8O5-V reference voltage. VREF is used to provide charging current to the oscillator timing capacitor through the timing resistor. It is important for reference stability that VREF is bypassed to GND with a ceramic capacitor connected as close to the pin as possible. A minimum value of 0.1 µF ceramic is required. Additional VREF bypassing is required for external loads on VREF. No external voltage higher than specified VREF is allowed to superimposed to VREF pin since VREF is an ouput.
(1) I = input, O = output, G = ground

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2)
MINMAXUNIT
Input voltageVDD30V
Input currentIVDD30mA
Output drive current (peak)±1A
Output energy (capacitive load), EOUT5µJ
Analog input voltageCOMP, CS, FB, RT/CT–0.36.3V
Output driver voltageOUT–0.330
Reference voltageVREF7
Error amplifier output sink currentCOMP10mA
Total power dissipation at TA = 25°CD package72.3°C/W
DGK package98.1
Lead temperature (soldering, 10 s), TLEAD300°C
Operating junction temperature, TJ–40150°C
Storage temperature, Tstg–65150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND pin. Currents are positive into and negative out of the specified terminals.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

 
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