SLUSC99A July   2016  – January 2017 UCD3138128A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 PMBus/SMBus/I2C Timing
    8. 7.8 Typical Characteristics
    9. 7.9 Timing Diagrams
  8. 8 Parametric Measurement Information
    1. 8.1 Typical Clock Gating Power Savings
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 ARM Processor
      2. 9.1.2 Memory
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  System Module
        1. 9.3.1.1 Address Decoder (DEC)
        2. 9.3.1.2 Memory Management Controller (MMC)
        3. 9.3.1.3 System Management (SYS)
        4. 9.3.1.4 Central Interrupt Module (CIM)
      2. 9.3.2  Peripherals
        1. 9.3.2.1 Digital Power Peripherals (DPPs)
          1. 9.3.2.1.1 Front End
          2. 9.3.2.1.2 DPWM Module
          3. 9.3.2.1.3 DPWM Events
          4. 9.3.2.1.4 High Resolution DPWM
          5. 9.3.2.1.5 Oversampling
          6. 9.3.2.1.6 DPWM Interrupt Generation
          7. 9.3.2.1.7 DPWM Interrupt Scaling/Range
          8. 9.3.2.1.8 Synchronous Rectifier Dead Time Optimization Peripheral
      3. 9.3.3  Automatic Mode Switching
        1. 9.3.3.1 Phase Shifted Full Bridge Example
        2. 9.3.3.2 LLC Example
        3. 9.3.3.3 Mechanism For Automatic Mode Switching
      4. 9.3.4  DPWMC, Edge Generation, Intramux
      5. 9.3.5  Synchronous Rectifier MOSFET Ramp And IDE Calculation
      6. 9.3.6  Filter
        1. 9.3.6.1 Loop Multiplexer
        2. 9.3.6.2 Fault Multiplexer
      7. 9.3.7  Communication Ports
        1. 9.3.7.1 SCI (UART) Serial Communication Interface
        2. 9.3.7.2 PMBUS/I2C
          1. 9.3.7.2.1 Example: PMBus Address Decode via ADC12 Reading
        3. 9.3.7.3 SPI
        4. 9.3.7.4 JTAG Standard Interface
      8. 9.3.8  Real Time Clock
      9. 9.3.9  External Crystal Interface
      10. 9.3.10 Timers
        1. 9.3.10.1 24-Bit Timer
        2. 9.3.10.2 16-Bit PWM Timers
        3. 9.3.10.3 Watchdog Timer
      11. 9.3.11 General Purpose ADC12
      12. 9.3.12 Miscellaneous Analog
      13. 9.3.13 Brownout
      14. 9.3.14 Global I/O
      15. 9.3.15 Temperature Sensor Control
      16. 9.3.16 I/O Mux Control
      17. 9.3.17 Current Sharing Control
      18. 9.3.18 Temperature Reference
    4. 9.4 Device Functional Modes
      1. 9.4.1 DPWM Modes of Operation
        1. 9.4.1.1 Normal Mode
        2. 9.4.1.2 DPWM Multiple Output Mode
        3. 9.4.1.3 DPWM Resonant Mode
        4. 9.4.1.4 Triangular Mode
        5. 9.4.1.5 Leading Edge Mode
        6. 9.4.1.6 Phase Shifting
    5. 9.5 Register Maps
      1. 9.5.1 CPU Memory Map And Interrupts
        1. 9.5.1.1 Memory Map (After Reset Operation)
        2. 9.5.1.2 Memory Map (Normal Operation)
        3. 9.5.1.3 Memory Map (System And Peripherals Blocks)
      2. 9.5.2 Boot ROM
        1. 9.5.2.1 Pseudo Code for ROM
      3. 9.5.3 Customer Boot Program
      4. 9.5.4 Flash Management
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. 10.2.2.2 DPWM Initialization for PSFB
        3. 10.2.2.3 DPWM Synchronization
        4. 10.2.2.4 Fixed Signals to Bridge
        5. 10.2.2.5 Dynamic Signals to Bridge
      3. 10.2.3 System Initialization for PCM
        1. 10.2.3.1 Use of Front Ends and Filters in PSFB
        2. 10.2.3.2 Peak Current Detection
        3. 10.2.3.3 Peak Current Mode (PCM)
      4. 10.2.4 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Device Grounding and Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
        1. 13.2.1.1 References
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 128 kB Program Flash Derivative of UCD3138xA Family
    • 4-32 kB Program Flash Memory Banks
    • Supports Execution From 1 Bank, While Programming Another
    • Capability to Update Firmware Without Shutting Down the Power Supply
    • Additional Communication Ports Compared to the UCD3138xA (+1 SPI, +1 I2C)
    • Boot Flash Based Dual Memory Image Support for ‘On the Fly’ Firmware Updates
  • Synchronous Rectifier Dead Time Optimization Peripheral to Use with UCD7138 Synchronous Rectifier Driver
  • Digital Control of up to 3 Independent Feedback Loops
    • Dedicated PID Based Hardware
    • 2-pole/2-zero Configurable, Non-Linear Control
  • Up to 16 MSPS Error A/D Converter (EADC)
    • Configurable Resolution (min: 1 mV/LSB)
    • Up to 8x Oversampling and Adaptive Sample Positioning
    • Hardware Based Averaging (up to 8x)
    • 14 bit Effective Reference DAC
  • Up to 8 High Resolution Digital Pulse Width Modulated (DPWM) Outputs
    • 250 ps Pulse Width Resolution
    • 4 ns Frequency and Phase Resolution
    • Adjustable Phase Shift and Dead-bands
    • Cycle-by-Cycle Duty Cycle Matching
    • Up to 2 MHz Switching Frequency
  • Configurable Trailing/Leading/Triangular Modulation
  • RTC Support
  • External Crystal Interface
  • Configurable Feedback Control
    • Voltage, Average Current and Peak Current Mode Control
    • Constant Current, Constant Power
  • Configurable FM, Phase Shift Modulation and PWM
  • Fast, Automatic and Smooth Mode Switching
    • Frequency Modulation and PWM
    • Phase Shift Modulation and PWM
  • High Efficiency and Light Load Management
    • Burst Mode and Ideal Diode Emulation
    • Synchronous Rectifier Soft On/Off
    • Low IC Standby Power
  • Primary Side Voltage Sensing
  • Current Share (Average and Master/Slave)
  • Feature Rich Fault Protection Options
    • 7 Analog / 4 Digital Comparators,
    • Cycle-by-Cycle Current Limiting
    • Programmable Blanking Time and Fault Counting
    • External Fault Inputs
  • Synchronization of DPWM Waveforms Between Multiple UCD3138x Devices
  • 15 channel, 12 bit, 539 ksps General Purpose ADC
  • Internal Temperature Sensor
  • Fully Programmable High-Performance 31.25 MHz, 32-bit ARM7TDMI-S Processor
    • 128 kB Program Flash (4-32 kB Banks)
    • 2 kB Data Flash with ECC
    • 8 kB Data RAM
    • 8 kB Boot ROM Enables Firmware Boot-Load\
  • Communication Peripherals,
    • 2 - I2C/PMBus interfaces
    • 2 - UARTs, 1 - SPI
  • UART Auto Baud Rate Adjustment
  • Timer Capture with Selectable Input Pins
  • 80-pin QFP Package
  • Operating Temperature: –40°C to 125°C
  • Debug Interface
    • Code Composer Studio with JTAG Interface
    • Fusion Digital Power Designer GUI Support

2 Applications

  • Power Supplies and Telecom Rectifiers
  • Power Factor Correction
  • Isolated DC-DC Modules
  • Phase Shifted Full Bridge with Peak Current Mode Control, LLC, HSFB, Forward

Typical Applications and Tools

UCD3138128A fp_image_slusc99.gif

3 Description

The UCD3138xA is a digital power supply controller from Texas Instruments offering superior levels of integration and performance in a single chip solution. The UCD3138128A offers 128 kB of program flash memory in comparison to 32 kB in UCD3138A. and it also provides additional options for communication such as SPI and a second I2C/PMBus port. The availability of of program Flash memory in multiple 32 kB banks enables designers to implement dual images of firmware (that is, one main image + one back-up image) in the device and provides the option to execute from either of the banks using appropriate algorithms. It also creates the unique opportunity for the processor to load a new program and subsequently execute that program without interrupting power delivery. This feature allows the end user to add new features to the power supply in the field while eliminating any down-time required to load the new program.

The flexible nature of the UCD3138xA family makes it suitable for a wide variety of power conversion applications. In addition, multiple peripherals inside the device have been specifically optimized to enhance the performance of AC/DC and isolated DC/DC applications and reduce the solution component count in the IT and network infrastructure space. The UCD3138xA family is a fully programmable solution offering customers complete control of their application, along with ample flexibility for many solutions. At the same time, TI is committed to simplifying our customer’s development effort through offering best in class development tools, including application firmware, Code Composer StudioTM software development environment, and TI’s Fusion Power Development GUI which enables customers to configure and monitor key system parameters.

At the core of the controller are the Digital Power Peripherals (DPP). Each DPP implements a high speed digital control loop consisting of a dedicated Error Analog to Digital Converter (EADC), a PID based 2 pole - 2 zero digital compensator and DPWM outputs with 250 ps pulse width resolution. The device also contains a 12-bit, 539 ksps general purpose ADC with up to 15 channels, timers, interrupt control, PMBus, I2C, SPI and UART communications ports. The device is based on a 32-bit ARM7TDMI-S RISC microcontroller that performs real-time monitoring, configures peripherals and manages communications. The ARM microcontroller executes its program out of programmable flash memory as well as on chip RAM and ROM.

In addition to the DPP, specific power management peripherals have been added to enable high efficiency across the entire operating range, high integration for increased power density, reliability, and lowest overall system cost and high flexibility with support for the widest number of control schemes and topologies. Such peripherals include: light load burst mode, synchronous rectification, LLC and phase shifted full bridge mode switching, input voltage feed forward, copper trace current sense, ideal diode emulation, constant current constant power control, synchronous rectification soft on and off, peak current mode control, flux balancing, secondary side input voltage sensing, high resolution current sharing, hardware configurable soft start with pre bias, as well as several other features. Topology support has been optimized for voltage mode and peak current mode controlled phase shifted full bridge, single and dual phase PFC, bridgeless PFC, hard switched full bridge and half bridge, active clamp forward converter, two switch forward converter and LLC half bridge and full bridge.

The UCD3138128A is a functional variant of the UCD3138 Digital Power Controller that includes significant improvements over the UCD3138. For a description of the complete changes made in the UCD3138128A, refer to UCD3138128A Migration Guide. The major improvements are:

  • The General Purpose ADC has been improved for better accuracy and performance at extreme cold temperatures (–40°C).
  • The UART peripheral has been modified to include a hardware based auto-baud rate adjustment feature.
  • A new Synchronous Rectifier Dead Time Optimization hardware peripheral has been added. Benefits include:
    • Improved efficiency
    • Reduced synchronous rectifier voltage stresses
    • Shorter development cycle
  • A Duty Cycle Read Function has been added to improve use in peak current mode.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
UCD3138128A TQFP (80) 12.00 mm × 12.00 mm
(1) For detailed ordering information please check the Mechanical, Packaging, and Orderable Information section at the end of this datasheet.

4 Revision History

Changes from * Revision (June 2016) to A Revision

  • Added two temperature ranges to the Internal oscillator frequency section.Go
  • Changed Figure 15 Go
  • Changed Figure 35 to include DTC Adjustment Go
  • Changed capacitor from RESET to ground value from 0.22 µF to 2.2 µF. Go
  • Added updated V33 slew rate values in the Device Grounding and Layout Guidelines section.Go
  • Added bullet on unused GPIO pins Go
  • Changed "A" to part number Go