ADC34J2x Quad-Channel, 12-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with JESD204B Interface

1 Features

• Quad Channel
• 12-Bit Resolution
• Single 1.8-V Supply
• Flexible Input Clock Buffer with Divide-by-1, -2, -4
• SNR = 69.6 dBFS, SFDR = 86 dBc at
  f_IN = 70 MHz
• Ultra-Low Power Consumption:
  • 203 mW/Ch at 160 MSPS
• Channel Isolation: 105 dB
• Internal Dither
• JESD204B Serial Interface:
  • Subclass 0, 1, 2 Compliant up to 3.2 Gbps
  • Supports One Lane per ADC up to 160 MSPS
• Support for Multi-Chip Synchronization
• Pin-to-Pin Compatible with 14-Bit Version
• Package: VQFN-48 (7 mm × 7 mm)

2 Applications

• Multi-Carrier, Multi-Mode Cellular Base Stations
• Radar and Smart Antenna Arrays
• Munitions Guidance
• Motor Control Feedback
• Network and Vector Analyzers
• Communications Test Equipment
• Nondestructive Testing
• Microwave Receivers
• Software Defined Radios (SDRs)
• Quadrature and Diversity Radio Receivers

3 Description

The ADC34J2x are a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.

1. For all available packages, see the orderable addendum at the end of the datasheet.

FFT with Dither On
(f_S = 160 MSPS, f_IN = 10 MHz, SNR = 70.3 dBFS, SFDR = 84 dBc)

4 Revision History

Changes from * Revision (May 2014) to A Revision

• Changed document status from product preview to production dataGo

5 Device Comparison Table

6 Pin Configuration and Functions

RGZ Package

VQFN-48

(Top View)