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ADS54J69 Dual-Channel, 16-Bit, 500-MSPS, Analog-to-Digital Converter
SBAS713C
May 2015 – January 2017
ADS54J69
PRODUCTION DATA.
CONTENTS
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ADS54J69 Dual-Channel, 16-Bit, 500-MSPS, Analog-to-Digital Converter
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
AC Characteristics
7.7
Digital Characteristics
7.8
Timing Characteristics
7.9
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Analog Inputs
8.3.2
DDC Block
8.3.2.1
Decimate-by-2 Filter
8.3.3
SYSREF Signal
8.3.3.1
SYSREF Not Present (Subclass 0, 2)
8.3.4
Overrange Indication
8.3.4.1
Fast OVR
8.3.5
Power-Down Mode
8.4
Device Functional Modes
8.4.1
Device Configuration
8.4.1.1
Serial Interface
8.4.1.2
Serial Register Write: Analog Bank
8.4.1.3
Serial Register Readout: Analog Bank
8.4.1.4
JESD Bank SPI Page Selection
8.4.1.5
Serial Register Write: JESD Bank
8.4.1.5.1
Individual Channel Programming
8.4.1.6
Serial Register Readout: JESD Bank
8.4.2
JESD204B Interface
8.4.2.1
JESD204B Initial Lane Alignment (ILA)
8.4.2.2
JESD204B Test Patterns
8.4.2.3
JESD204B Frame
8.4.2.4
JESD204B Frame Assembly with Decimation
8.4.2.4.1
JESD Transmitter Interface
8.4.2.4.2
Eye Diagrams
8.5
Register Maps
8.5.1
Detailed Register Info
8.5.2
Example Register Writes
8.5.3
Register Descriptions
8.5.3.1
General Registers
8.5.3.1.1
Register 0h (address = 0h)
8.5.3.1.2
Register 3h (address = 3h)
8.5.3.1.3
Register 4h (address = 4h)
8.5.3.1.4
Register 5h (address = 5h)
8.5.3.1.5
Register 11h (address = 11h)
8.5.3.2
Master Page (080h) Registers
8.5.3.2.1
Register 20h (address = 20h), Master Page (080h)
8.5.3.2.2
Register 21h (address = 21h), Master Page (080h)
8.5.3.2.3
Register 23h (address = 23h), Master Page (080h)
8.5.3.2.4
Register 24h (address = 24h), Master Page (080h)
8.5.3.2.5
Register 26h (address = 26h), Master Page (080h)
8.5.3.2.6
Register 39h (address = 39h), Master Page (080h)
8.5.3.2.7
Register 3Ah (address = 3Ah), Master Page (080h)
8.5.3.2.8
Register 4Fh (address = 4Fh), Master Page (080h)
8.5.3.2.9
Register 53h (address = 53h), Master Page (080h)
8.5.3.2.10
Register 54h (address = 54h), Master Page (080h)
8.5.3.2.11
Register 55h (address = 55h), Master Page (080h)
8.5.3.2.12
Register 56h (address = 56h), Master Page (080h)
8.5.3.2.13
Register 59h (address = 59h), Master Page (080h)
8.5.3.3
ADC Page (0Fh) Registers
8.5.3.3.1
Registers 5F (addresses = 5F), ADC Page (0Fh)
8.5.3.4
Main Digital Page (6800h) Registers
8.5.3.4.1
Register 0h (address = 0h), Main Digital Page (6800h)
8.5.3.4.2
Register 41h (address = 41h), Main Digital Page (6800h)
8.5.3.4.3
Register 42h (address = 42h), Main Digital Page (6800h)
8.5.3.4.4
Register 43h (address = 43h), Main Digital Page (6800h)
8.5.3.4.5
Register 44h (address = 44h), Main Digital Page (6800h)
8.5.3.4.6
Register 4Bh (address = 4Bh), Main Digital Page (6800h)
8.5.3.4.7
Register 4Dh (address = 4Dh), Main Digital Page (6800h)
8.5.3.4.8
Register 4Eh (address = 4Eh), Main Digital Page (6800h)
8.5.3.4.9
Register 52h (address = 52h), Main Digital Page (6800h)
8.5.3.4.10
Register 72h (address = 72h), Main Digital Page (6800h)
8.5.3.4.11
Register ABh (address = ABh), Main Digital Page (6800h)
8.5.3.4.12
Register ADh (address = ADh), Main Digital Page (6800h)
8.5.3.4.13
Register F7h (address = F7h), Main Digital Page (6800h)
8.5.3.5
JESD Digital Page (6900h) Registers
8.5.3.5.1
Register 0h (address = 0h), JESD Digital Page (6900h)
8.5.3.5.2
Register 1h (address = 1h), JESD Digital Page (6900h)
8.5.3.5.3
Register 2h (address = 2h), JESD Digital Page (6900h)
8.5.3.5.4
Register 3h (address = 3h), JESD Digital Page (6900h)
8.5.3.5.5
Register 5h (address = 5h), JESD Digital Page (6900h)
8.5.3.5.6
Register 6h (address = 6h), JESD Digital Page (6900h)
8.5.3.5.7
Register 7h (address = 7h), JESD Digital Page (6900h)
8.5.3.5.8
Register 31h (address = 31h), JESD Digital Page (6900h)
8.5.3.5.9
Register 32h (address = 32h), JESD Digital Page (6900h)
8.5.3.6
JESD Analog Page (6A00h) Register
8.5.3.6.1
Registers 12h-5h (address = 12h-5h), JESD Analog Page (6A00h)
8.5.3.6.2
Register 16h (address = 16h), JESD Analog Page (6A00h)
8.5.3.6.3
Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
8.5.3.6.4
Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
9
Application and Implementation
9.1
Application Information
9.1.1
Start-Up Sequence
9.1.2
Hardware Reset
9.1.3
SNR and Clock Jitter
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Transformer-Coupled Circuits
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
10.1
Power Sequencing and Initialization
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
RMP|72
MPQF396A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sbas713c_oa
sbas713c_pm
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