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  • ADS8339 16-Bit, 250-kSPS, Serial Interface, Micro-Power, Miniature, SAR Analog-to-Digital Converter

    • SBAS677A June   2014  – October 2014 ADS8339

      PRODUCTION DATA.  

  • CONTENTS
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  • ADS8339 16-Bit, 250-kSPS, Serial Interface, Micro-Power, Miniature, SAR Analog-to-Digital Converter
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Family
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parametric Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input
      2. 9.3.2 Power Saving
      3. 9.3.3 Digital Output
      4. 9.3.4 SCLK Input
    4. 9.4 Device Functional Modes
      1. 9.4.1 CS Mode for a 3-Wire Interface
        1. 9.4.1.1 3-Wire CS Mode Without a Busy Indicator
        2. 9.4.1.2 3-Wire CS Mode With a Busy Indicator
      2. 9.4.2 CS Mode for a 4-Wire Interface
        1. 9.4.2.1 4-Wire CS Mode Without a Busy Indicator
        2. 9.4.2.2 4-Wire CS Mode With a Busy Indicator
      3. 9.4.3 Daisy-Chain Mode
        1. 9.4.3.1 Daisy-Chain Mode Without a Busy Indicator
        2. 9.4.3.2 Daisy-Chain Mode With a Busy Indicator
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 ADC Reference Driver
        1. 10.1.1.1 Reference Driver Circuit
      2. 10.1.2 ADC Input Driver
        1. 10.1.2.1 Input Amplifier Selection
        2. 10.1.2.2 Antialiasing Filter
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 Do's and Don'ts
  11. 11Power-Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
  15. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DGS|10
    • MPDS035C
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sbas677a_oa
  • sbas677a_pm
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DATA SHEET

ADS8339 16-Bit, 250-kSPS, Serial Interface, Micro-Power, Miniature, SAR Analog-to-Digital Converter

1 Features

  • Sample Rate: 250 kHz
  • 16-Bit Resolution
  • Zero Latency at Full Speed
  • Unipolar Single-Ended Input Range:
    • 0 V to Vref
  • SPI™-Compatible Serial Interface with Daisy-Chain Option
  • Uses Internal Clock for Conversion
  • Excellent Performance:
    • 93.6 dB SNR (typ) at 10-kHz Input
    • –106 dB THD (typ) at 10-kHz Input
    • ±2.0 LSB INL (max)
    • ±1.0 LSB DNL (max)
  • Low-Power Dissipation:
    • 17.5 mW (typ) at 250 kSPS
  • Power Scales Linearly with Speed:
    • 1.75 mW at 25 kSPS
  • Power Dissipation During Power-Down State:
    • 0.25 μW (typ)
  • Package: VSSOP-10

2 Applications

  • Battery-Powered Equipment
  • Data Acquisition Systems
  • Instrumentation and Process Controls
  • Medical Electronics
  • Optical Networking

3 Description

The ADS8339 is a 16-bit, 250-kSPS, analog-to-digital converter (ADC). The device operates with a 2.25-V to 5.5-V external reference. The device includes a capacitor-based, successive-approximation register (SAR) ADC with an inherent sample-and-hold circuit.

The device includes a 25-MHz, SPI-compatible serial interface. The interface is designed to support daisy-chaining or cascading of multiple devices. Furthermore, a busy indicator makes synchronizing with the digital host easy. The unipolar, single-ended input range for the device supports an input swing of 0 V to Vref.

The device is optimized for low-power operation and power consumption scales directly with speed. This feature makes the device attractive for lower speed applications. The ADS8339 is available in a VSSOP-10 package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
ADS8339 VSSOP (10) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

alt_sbas677.gif

4 Revision History

Changes from * Revision (June 2014) to A Revision

  • Made changes to product preview data sheetGo

5 Device Family(1)

SAMPLING RATE 16-BIT, SINGLE-ENDED 16-BIT, DIFFERENTIAL 18-BIT, DIFFERENTIAL
100 kSPS ADS8866 ADS8867 ADS8887
250 kSPS ADS8339 — —
400 kSPS ADS8864 ADS8865 ADS8885
500 kSPS ADS8319 ADS8318 —
680 kSPS ADS8862 ADS8863 ADS8883
1 MSPS ADS8860 ADS8861 ADS8881
(1) All devices are pin-to-pin compatible. The ADS8339, ADS8319, and ADS8318 require a 4.5-V to 5.5-V analog supply. The remaining devices use a 2.7-V to 3.6-V analog supply.

6 Pin Configuration and Functions

DGS Package
VSSOP-10
(Top View)
po_bas677.gif

Pin Functions

PIN FUNCTION DESCRIPTION
NO. NAME
1 REFIN Input Reference (positive) input. Decouple to GND with a 0.1-μF bypass capacitor and a 10-μF storage capacitor.
2 +VA Supply Analog power supply. Decouple with the GND pin.
3 +IN Input Noninverting analog signal input
4 –IN Input Inverting analog signal input. Note that this input has a limited range of ±0.1 V and is typically grounded at the input decoupling capacitor.
5 GND Supply Device ground. Note that this pin is a common ground pin for both the analog power supply (+VA) and digital I/O supply (+VBD).
6 CONVST Input Convert input. CONVST also functions as the CS input in 3-wire interface mode. Refer to the Description and Timing Diagrams sections for more details.
7 SDO Output Serial data output
8 SCLK Input Serial I/O clock input. Data (on the SDO output) are synchronized with this clock.
9 SDI Input Serial data input. The SDI level at the start of a conversion selects the mode of operation (such as CS or daisy-chain mode). SDI also serves as the CS input in 4-wire interface mode. Refer to the Description and Timing Diagrams sections for more details.
10 +VBD Supply Digital I/O power supply. Decouple with the GND pin.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
+IN, –IN input Voltage –0.3 +VA + 0.3 V
Momentary current(2) 130 mA
Continuous current ±10 mA
+VA to GND –0.3 7 V
+VBD to GND –0.3 7 V
Digital input voltage to GND –0.3 +VBD + 0.3 V
Digital output voltage to GND –0.3 +VBD + 0.3 V
Temperature Operating free-air range, TA –40 85 °C
Junction, TJ max 150 °C
VSSOP package Power dissipation (TJmax – TA) / θJA °C
θJA thermal impedance 121.1 °C/W
Maximum VSSOP reflow temperature(3) 260 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Limit the duration for this current to less than 10 ms.
(3) The device is rated at MSL2, 260°C, as per the JSTD-020 specification.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –1000 1000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –250 250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V+VA Analog power-supply voltage 4.5 5.0 5.5 V
V+VBD Digital I/O-supply voltage 2.375 3.3 5.5 V
Vref Reference voltage 2.25 4.096 V+VA + 0.1 V
f(SCLK) SCLK frequency 25 MHz
TA Operating temperature range –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1) ADS8339 UNIT
DGS (VSSOP)
10 PINS
RθJA Junction-to-ambient thermal resistance 121.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 29.4
RθJB Junction-to-board thermal resistance 32.0
ψJT Junction-to-top characterization parameter 0.7
ψJB Junction-to-board characterization parameter 31.5
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

All minimum and maximum specifications are at TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, Vref = 4 V, and fsample = 250 kHz, unless otherwise noted. Typical specifications are at TA = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input span(1) +IN – (–IN) 0 Vref V
Operating input range +IN –0.1 Vref + 0.1 V
–IN –0.1 0.1 V
Ci Input capacitance 59 pF
Input leakage current During acquisition 1000 pA
SYSTEM PERFORMANCE
Resolution 16 Bits
NMC No missing codes 16 Bits
INL Integral linearity(7) –2.0 ±1.2 2.0 LSB(2)
DNL Differential linearity At 16-bit level –0.99 ±0.65 1.0 LSB
EO Offset error(3) –1.5 ±0.3 1.5 mV
EG Gain error –0.03 ±0.0045 0.03 %FSR
CMRR Common-mode rejection ratio With common-mode input signal = 200 mVPP
at 250 kHz		 78 dB
PSRR Power-supply rejection ratio At FFF0h output code 80 dB
Transition noise 0.5 LSB
SAMPLING DYNAMICS
tcnv Conversion time 500(4) 3300 ns
tacq Acquisition time 700 ns
Maximum throughput rate
with or without latency		 0.25 MHz
Aperture delay 2.5 ns
Aperture jitter, RMS 6 ps
Step response Settling to 16-bit accuracy 600 ns
Overvoltage recovery Settling to 16-bit accuracy 600 ns
DYNAMIC CHARACTERISTICS
THD Total harmonic distortion(5) VIN = 0.4 dB below fS at 1 kHz, Vref = 5 V –111 dB
VIN = 0.4 dB below fS at 10 kHz, Vref = 5 V –106 dB
SNR Signal-to-noise ratio VIN = 0.4 dB below fS at 1 kHz, Vref = 5 V 93.9 dB
VIN = 0.4 dB below fS at 10 kHz, Vref = 5 V 93.6 dB
SINAD Signal-to-noise + distortion VIN = 0.4 dB below fS at 1 kHz, Vref = 5 V 93.8 dB
VIN = 0.4 dB below fS at 10 kHz, Vref = 5 V 93.4 dB
SFDR Spurious-free dynamic range VIN = 0.4 dB below fS at 1 kHz, Vref = 5 V 113 dB
VIN = 0.4 dB below fS at 10 kHz, Vref = 5 V 107 dB
–3-dB small-signal bandwidth 15 MHz
EXTERNAL REFERENCE INPUT
Vref Input range 2.25 4.096 VA + 0.1 V
Reference input current(6) During conversion 75 μA
POWER-SUPPLY REQUIREMENTS
Power-supply voltage +VBD 2.375 3.3 5.5 V
+VA 4.5 5 5.5 V
ICC Supply current +VA 250-kHz sample rate 3.5 4.0 mA
PVA Power dissipation +VA = 5 V, 250-kHz sample rate 17.5 20.0 mW
IVApd Device power-down current(8) +VA = 5 V 50 300 nA
LOGIC FAMILY CMOS
VIH High-level input voltage IIH = 5 μA 0.7 × VBD VBD + 0.3 V
VIL Low-level input voltage IIL = 5 μA –0.3 0.3 × VBD V
VOH High-level output voltage IOH = 2 TTL loads VBD – 0.3 VBD V
VOL Low-level output voltage IOL = 2 TTL loads 0 0.4 V
TEMPERATURE RANGE
TA Operating free-air temperature –40 85 °C
(1) Ideal input span, does not include gain or offset error.
(2) LSB = least significant bit.
(3) Measured relative to actual measured reference.
(4) Refer to the CS Mode for a 3-Wire Interface section in the Device Functional Modes.
(5) Calculated on the first nine harmonics of the input frequency.
(6) Can vary by ±20%.
(7) This parameter is the endpoint INL, not best-fit INL.
(8) The device automatically enters a power-down state at the end of every conversion and remains in a power-down state as long as the device is in an acquisition phase.

7.6 Timing Requirements

All specifications are at TA = –40°C to 85°C, +VA = 5 V, and 5.5 V > +VBD ≥ 2.375 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SAMPLING AND CONVERSION
tacq Acquisition time
(see Figure 47, Figure 49, Figure 50, Figure 53)		 700 ns
tcnv Conversion time
(see Figure 47, Figure 49, Figure 50, Figure 53)		 500(1) 3300 ns
tcyc Time between conversions
(see Figure 47, Figure 49, Figure 50, Figure 53)		 4000 ns
t1 Pulse duration, CONVST high (see Figure 47, Figure 49) 10 ns
t6 Pulse duration, CONVST low
(see Figure 50, Figure 53, Figure 55)		 20 ns
INPUTS AND OUTPUTS (I/O)
tclk SCLK period (see Figure 47, Figure 49, Figure 50, Figure 53, Figure 55, Figure 57) 40.0 ns
tclkl SCLK low time (see Figure 47, Figure 49, Figure 50, Figure 53, Figure 55, Figure 57) 0.45 0.55 tclk
tclkh SCLK high time (see Figure 47, Figure 49, Figure 50, Figure 53, Figure 55, Figure 57) 0.45 0.55 tclk
t2 SCLK falling edge to data remains valid (see Figure 47, Figure 49, Figure 50, Figure 53, Figure 55, Figure 57) 5 ns
t3 SCLK falling edge to next data valid delay (see Figure 47, Figure 49, Figure 50, Figure 53, Figure 55, Figure 57) 5.5 V ≥ +VBD ≥ 4.5 V 16 ns
4.5 V > +VBD ≥ 2.375 V 24 ns
ten CONVST or SDI low to MSB valid
(see Figure 47, Figure 50)		 5.5 V ≥ +VBD ≥ 4.5 V 15 ns
4.5 V > +VBD ≥ 2.375 V 22 ns
tdis CONVST or SDI high or last SCLK falling edge to SDO
3-state (CS mode)
(see Figure 47, Figure 49, Figure 50, Figure 53)		 5.5 V ≥ +VBD ≥ 4.5 V 12 ns
4.5 V > +VBD ≥ 2.375 V 15 ns
t4 SDI valid setup time to CONVST rising edge
(see Figure 50, Figure 53)		 5 ns
t5 SDI valid hold time from CONVST rising edge
(see Figure 50, Figure 53)		 5 ns
t7 SCLK valid setup time to CONVST rising edge
(see Figure 55)		 5 ns
t8 SCLK valid hold time from CONVST rising edge
(see Figure 55)		 5 ns
(1) Refer to the CS Mode for a 3-Wire Interface subsection in the Device Functional Modes section.

7.7 Typical Characteristics

At TA = 30°C, +VA = 5 V, +VBD = 2.7 V, Vref = 4.096 V, and fsample = 250 kHz, unless otherwise noted.
C001_SBAS677.png
+VBD = 2.7 V, Vref = 4.096 V, fS = 250 kSPS, TA = 30°C
Figure 1. Offset Error vs Supply Voltage
C003_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, fS = 250 kSPS, TA = 30°C
Figure 3. Offset Error vs Reference Voltage
C005_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS
Figure 5. Offset Error vs Free-Air Temperature
C007_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, fS = 250 kSPS
Figure 7. Gain Error Drift Histogram
C009_SBAS677.png
+VBD = 2.7 V, Vref = 4.096 V, fS = 250 kSPS, TA = 30°C
Figure 9. DNL vs Supply Voltage
C011_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, fS = 250 kSPS, TA = 30°C
Figure 11. DNL vs Reference Voltage
C013_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS
Figure 13. DNL vs Free-Air Temperature
C015_SBAS677.png
+VBD = 2.7 V, Vref = 5 V, fIN = 1.9 kHz, fS = 250 kSPS,
TA = 30°C
Figure 15. ENOB vs Supply Voltage
C017_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fIN = 1.9 kHz,
fS = 250 kSPS
Figure 17. ENOB vs Free-Air Temperature
C019_SBAS677.png
+VBD = 2.7 V, Vref = 4.096 V, fIN = 1.9 kHz, fS = 250 kSPS,
TA = 30°C
Figure 19. SINAD vs Supply Voltage
C021_SBAS677.png
+VBD = 2.7 V, Vref = 4.096 V, fIN = 1.9 kHz, fS = 250 kSPS,
TA = 30°C
Figure 21. THD vs Supply Voltage
C023_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, fIN = 1.9 kHz, fS = 250 kSPS, TA = 30°C
Figure 23. SINAD vs Reference Voltage
C025_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, fIN = 1.9 kHz, fS = 250 kSPS, TA = 30°C
Figure 25. THD vs Reference Voltage
C027_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fIN = 1.9 kHz,
fS = 250 kSPS
Figure 27. SINAD vs Free-Air Temperature
C029_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fIN = 1.9 kHz,
fS = 250 kSPS
Figure 29. THD vs Free-Air Temperature
C031_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS, TA = 30°C
Figure 31. THD vs Signal Input Frequency
C033_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fIN = 1.9 kHz,
fS = 250 kSPS, TA = 30°C
Figure 33. THD vs Source Resistance
C035_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, fS = 250 kSPS
Figure 35. Supply Current vs Free-Air Temperature
C037_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, TA = 30°C
Figure 37. Power Dissipation vs Sampling Frequency
C039_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 4.096 V, fS = 250 kSPS
Figure 39. Power-Down Current vs Free-Air Temperature
C041_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS, TA = 30°C
Figure 41. INL Error vs Output Code
C002_SBAS677.png
+VBD = 2.7 V, Vref = 4.096 V, fS = 250 kSPS, TA = 30°C
Figure 2. Gain Error vs Supply Voltage
C004_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, fS = 250 kSPS, TA = 30°C
Figure 4. Gain Error vs Reference Voltage
C006_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS
Figure 6. Gain Error vs Free-Air Temperature
C008_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS
Figure 8. Offset Error Drift Histogram
C010_SBAS677.png
+VBD = 2.7 V, Vref = 4.096 V, fS = 250 kSPS, TA = 30°C
Figure 10. INL vs Supply Voltage
C012_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, fS = 250 kSPS, TA = 30°C
Figure 12. INL vs Reference Voltage
C014_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS
Figure 14. INL vs Free-Air Temperature
C016_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, fIN = 1.9 kHz, fS = 250 kSPS, TA = 30°C
Figure 16. ENOB vs Reference Voltage
C018_SBAS677.png
+VBD = 2.7 V, Vref = 4.096 V, fIN = 1.9 kHz, fS = 250 kSPS,
TA = 30°C
Figure 18. SFDR vs Supply Voltage
C020_SBAS677.png
+VBD = 2.7 V, Vref = 4.096 V, fIN = 1.9 kHz, fS = 250 kSPS,
TA = 30°C
Figure 20. SNR vs Supply Voltage
C022_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, fIN = 1.9 kHz, fS = 250 kSPS, TA = 30°C
Figure 22. SFDR vs Reference Voltage
C024_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, fIN = 1.9 kHz, fS = 250 kSPS, TA = 30°C
Figure 24. SNR vs Reference Voltage
C026_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fIN = 1.9 kHz,
fS = 250 kSPS
Figure 26. SFDR vs Free-Air Temperature
C028_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fIN = 1.9 kHz,
fS = 250 kSPS
Figure 28. SNR vs Free-Air Temperature
C030_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS, TA = 30°C
Figure 30. SINAD vs Signal Input Frequency
C032_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS, TA = 30°C
Figure 32. DC Histogram of ADC Close-to-Center Code
C034_SBAS677.png
+VBD = 2.7 V, Vref = 4.096 V, fS = 250 kSPS, TA = 30°C
Figure 34. Supply Current vs Supply Voltage
C036_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, TA = 30°C
Figure 36. Supply Current vs Sampling Frequency
C038_SBAS677.png
+VBD = 2.7 V, Vref = 4.096 V, fS = 250 kSPS, TA = 30°C
Figure 38. Power-Down Current vs Supply Voltage
C040_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fS = 250 kSPS, TA = 30°C
Figure 40. DNL Error vs Output Code
C042_SBAS677.png
+VBD = 2.7 V, +VA = 5 V, Vref = 5 V, fIN = 1.9 kHz,
fS = 250 kSPS, TA = 30°C
Figure 42. Signal Strength vs Frequency

8 Parametric Measurement Information

8.1 Timing Diagrams

load_cir_digital_iface_bas616.gifFigure 43. Digital Interface Timing Load Circuit
tim_voltage_levels_bas616.gifFigure 44. Timing Voltage Levels

9 Detailed Description

9.1 Overview

The ADS8339 is a 250-kSPS, low-power, successive-approximation register (SAR), analog-to-digital converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently includes a sample-and-hold function.

The ADS8339 is a single-channel device. The analog input is provided to two input pins: +IN and –IN, where –IN is a pseudo-differential input and has a limited range of ±0.1 V. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both the +IN and –IN inputs are disconnected from any internal functions.

The device has an internal clock that is used to run the conversion. Therefore, the conversion requires a fixed amount of time. After a conversion is completed, the device reconnects the sampling capacitors to the +IN and –IN pins and the device is in the acquisition phase. During this phase, the device is powered down and conversion data can be read.

The device digital output is available in SPI-compatible format. The device easily interfaces with microprocessors, digital signal processors (DSPs), or field-programmable gate arrays (FPGAs).

9.2 Functional Block Diagram

alt_sbas616.gif

9.3 Feature Description

9.3.1 Analog Input

When the converter samples the input, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. The differential signal range is [(+IN) – (–IN)]. The voltage on +IN is limited between GND – 0.1 V and Vref + 0.1 V and the voltage on –IN is limited between GND – 0.1 V to GND + 0.1 V. The input rejects any small signal that is common to both the +IN and –IN input.

The (peak) input current through the analog input depends upon a number of factors: sample rate, input voltage, and source impedance. The current into the device charges the internal capacitor array (as shown in Figure 45) during the sample period. When this capacitance is fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (59 pF) to a 18-bit settling level within the minimum acquisition time. When the converter goes into hold mode, the input impedance is greater than 1 GΩ.

Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN input, –IN input, and span [+IN – (–IN)] must be within the limits specified. Outside of these ranges, the converter linearity may not meet specifications.

Care must also be taken to ensure that the output impedance of the sources driving the +IN input and the –IN input is matched. If this output impedance is not well matched, the two inputs can have different settling times. This mismatch may result in an offset error, gain error, and linearity error that changes with temperature and input voltage. Typically, the –IN input is grounded at the input decoupling capacitor.

ai_input_equiv_cir_bas616.gifFigure 45. Input Equivalent Circuit

9.3.2 Power Saving

The device has an auto power-down feature. The device powers down at the end of every conversion. The input signal is acquired on sampling capacitors when the device is in power-down state. At the same time, the conversion results are available for reading. The device powers up automatically at the start of the conversion. The conversion runs on an internal clock and requires a fixed time. As a result, device power consumption is directly proportional to the speed of operation.

9.3.3 Digital Output

As discussed in the Description and Timing Diagrams sections, the device digital output is SPI-compatible. Table 1 lists the output codes corresponding to various analog input voltages.

Table 1. Output Codes

DESCRIPTION ANALOG VALUE (V) DIGITAL OUTPUT STRAIGHT BINARY
BINARY CODE HEX CODE
Full-scale range Vref — —
Least significant bit (LSB) Vref / 65536 — —
Positive full-scale +Vref – 1 LSB 1111 1111 1111 1111 FFFF
Mid-scale Vref / 2 1000 0000 0000 0000 8000
Mid-scale – 1 LSB Vref / 2 – 1 LSB 0111 1111 1111 1111 7FFF
Zero 0 0000 0000 0000 0000 0000

9.3.4 SCLK Input

The device uses SCLK for the serial data output. Data are read after the conversion is complete and the device is in acquisition phase. A free-running SCLK can be used, but TI recommends stopping the clock during conversion time because the clock edges can couple with the internal analog circuit that, in turn, can affect the conversion results.

9.4 Device Functional Modes

The ADS8339 supports three interface options. Under each option, the device can be used with or without a busy indicator.

  1. CS mode for a 3-wire interface (with or without a busy indicator): This mode is useful for applications where a single ADS8339 device is connected to the digital host.
  2. CS mode for a 4-wire interface (with or without a busy indicator): This mode can be used when more than one ADS8339 device is connected to the digital host on a common data bus.
  3. Daisy-chain mode (with or without a busy indicator): This mode is provided to connect multiple ADS8339 devices in a chain (such as a shift register) and is useful when reducing the number of signal traces on the board or the component count.

The busy indicator is generated as the bit preceding the 16-bit serial data.

9.4.1 CS Mode for a 3-Wire Interface

CS mode is selected if SDI is high at the CONVST rising edge. As previously indicated, the device can be used without or with a busy indicator. This section discusses this interface and the two options in detail.

9.4.1.1 3-Wire CS Mode Without a Busy Indicator

In a 3-wire CS mode, SDI is permanently tied to +VBD, as shown in Figure 46. CONVST functions like CS. As shown in Figure 47, the device samples the input signal and enters the conversion phase on the CONVST rising edge. SDO goes to 3-state at the same time. Conversion is done with the internal clock and continues regardless of the state of CONVST. As a result, CONVST (functioning as CS) can be brought low after the start of the conversion to select other devices on the board.

CONVST must return to high before the minimum conversion time (tcnv_min in the Timing Requirements table) elapses. A high level on CONVST at the end of the conversion ensures the device does not generate a busy indicator.

ai_conex_3wire_nobusy_bas616.gifFigure 46. Connection Diagram: 3-Wire CS Mode without a Busy Indicator (SDI = 1)
ai_iface_tim_3wire_nobusy_bas677.gifFigure 47. Interface Timing Diagram: 3-Wire CS Mode Without a Busy Indicator (SDI = 1)

When the conversion is complete, the device enters acquisition phase and powers down. On the CONVST falling edge, SDO comes out of 3-state and the device outputs the MSB of the data. Afterwards, the device outputs the next lower data bits on every subsequent SCLK falling edge. A minimum of 15 SCLK falling edges must occur during the low period of CONVST. SDO goes to 3-state after the 16th SCLK falling edge or when CONVST is high, whichever occurs first.

9.4.1.2 3-Wire CS Mode With a Busy Indicator

As stated in the 3-Wire CS Mode Without a Busy Indicator section, SDI is permanently tied to +VBD, as shown in Figure 48. CONVST functions like CS. As shown in Figure 49, the device samples the input signal and enters the conversion phase on the CONVST rising edge. SDO goes to 3-state at the same time. Conversion is done with the internal clock and continues regardless of the state of CONVST. As a result, CONVST (functioning as CS) can be toggled after the start of the conversion to select other devices on the board.

CONVST must return to low before the minimum conversion time (tcnv_min in the Timing Requirements table) elapses and remains low until the end of the maximum conversion time. A low level on the CONVST input at the end of a conversion ensures the device generates a busy indicator (low level on SDO). For fast settling, a 10-kΩ pull-up resistor tied to +VBD is recommended to provide the necessary current to drive SDO low.

ai_conex_3wire_busy_bas677.gifFigure 48. Connection Diagram: 3-Wire CS Mode With a Busy Indicator
ai_iface_tim_3wire_busy_bas677.gifFigure 49. Interface Timing Diagram: 3-Wire CS Mode With a Busy Indicator (SDI = 1)

When the conversion is complete, the device enters acquisition phase, powers down, forces SDO out of 3-state, and outputs a busy indicator bit (low level). The device outputs the MSB of data on the first SCLK falling edge after the conversion is complete and continues to output the next lower data bits on every subsequent SCLK falling edge. A minimum of 16 SCLK falling edges must occur during the low period of CONVST. SDO goes to 3-state after the 17th SCLK falling edge or when CONVST is high, whichever occurs first.

9.4.2 CS Mode for a 4-Wire Interface

This interface is similar to the CS mode for 3-wire interface except that SDI is controlled by the digital host. This section discusses in detail the interface option with and without a busy indicator.

9.4.2.1 4-Wire CS Mode Without a Busy Indicator

As mentioned previously, in order to select CS mode, SDI must be high at the time of the CONVST rising edge. Unlike in the 3-wire interface option, SDI is controlled by the digital host and functions like CS. As shown in Figure 50, SDI goes to a high level before the CONVST rising edge. When SDI is high, the CONVST rising edge selects CS mode, forces SDO to 3-state, samples the input signal, and the device enters the conversion phase.

In the 4-wire interface option, CONVST must be at a high level from the start of the conversion until all data bits are read. Conversion is done with the internal clock and continues regardless of the state of SDI. As a result, SDI (functioning as CS) can be brought low to select other devices on the board.

SDI must return to high before the minimum conversion time (tcnv_min in the Timing Requirements table) elapses.

ai_iface_tim_4wire_nobusy_bas677.gifFigure 50. Interface Timing Diagram: 4-Wire CS Mode Without a Busy Indicator

When the conversion is complete, the device enters the acquisition phase and powers down. An SDI falling edge can occur after the maximum conversion time (tcnv in the Timing Requirements table). Note that SDI must be high at the end of the conversion so that the device does not generate a busy indicator. The SDI falling edge brings SDO out of 3-state and the device outputs the MSB of the data. Subsequently, the device outputs the next lower data bits on every subsequent SCLK falling edge. SDO goes to 3-state after the 16th SCLK falling edge or when SDI (CS) is high, whichever occurs first. As shown in Figure 51, multiple devices can be chained on the same data bus. In this case, the second device SDI (functioning as CS) can go low after the first device data are read and the device 1 SDO is in 3-state.

Care must be taken so that CONVST and SDI are not both low at any time during the cycle.

ai_conex_4wire_nobusy_bas616.gifFigure 51. Connection Diagram: 4-Wire CS Mode Without a Busy Indicator

9.4.2.2 4-Wire CS Mode With a Busy Indicator

As mentioned previously, in order to select CS mode, SDI must be high at the time of the CONVST rising edge. In this mode of operation, the connection is made as shown in Figure 52.

ai_conex_4wire_busy_bas616.gifFigure 52. Connection Diagram: 4-Wire CS Mode With a Busy Indicator

Unlike in the 3-wire interface option, SDI is controlled by the digital host and functions like CS. As shown in Figure 53, SDI goes to a high level before the CONVST rising edge. When SDI is high, the CONVST rising edge selects the CS mode, forces SDO to 3-state, samples the input signal, and the device enters the conversion phase.

In the 4-wire interface option, CONVST must be at a high level from the start of the conversion until all data bits are read. Conversion is done with the internal clock and continues regardless of the state of SDI. As a result, SDI (functioning as CS) can be toggled to select other devices on the board.

SDI must return low before the minimum conversion time (tcnv_min in the Timing Requirements table) elapses and must remain low until the end of the maximum conversion time. A low level on the SDI input at the end of a conversion ensures the device generates a busy indicator (low on SDO). For fast settling, a 10-kΩ pull-up resistor tied to +VBD is recommended to provide the necessary current to drive SDO low.

ai_iface_tim_4wire_busy_bas677.gifFigure 53. Interface Timing Diagram: 4-Wire CS Mode With a Busy Indicator

When the conversion is complete, the device enters acquisition phase, powers down, forces SDO out of 3-state, and outputs a busy indicator bit (low level). The device outputs the MSB of the data on the first SCLK falling edge after the conversion is complete and continues to output the next lower data bits on every subsequent SCLK falling edge. SDO goes to 3-state after the 17th SCLK falling edge or when SDI (CS) is high, whichever occurs first.

Care must be taken so that CONVST and SDI are not both low at any time during the cycle.

9.4.3 Daisy-Chain Mode

Daisy-chain mode is selected if SDI is low at the time of the CONVST rising edge. This mode is useful to reduce wiring and hardware requirements (such as digital isolators in applications where multiple ADC devices are used). In this mode, all devices are connected in a chain (the SDO of one device is connected to the SDI of the next device) and data transfer is analogous to a shift register.

As in CS mode, this mode offers operation with or without a busy indicator. This section discusses these interface options in detail.

9.4.3.1 Daisy-Chain Mode Without a Busy Indicator

A connection diagram for this mode is shown in Figure 54. The SDI for device 1 is tied to ground and the SDO of device 1 goes to the SDI of device 2, and so on. The SDO of the last device in the chain goes to the digital host. CONVST for all devices in the chain are tied together. There is no CS signal in this mode.

ai_conex_daisy_nobusy_bas616.gifFigure 54. Connection Diagram: Daisy-Chain Mode Without a Busy Indicator (SDI = 0)

The device SDO is driven low when SDI low selects daisy-chain mode and the device samples the analog input and enters the conversion phase. SCLK must be low at the CONVST rising edge (as shown in Figure 55) so that the device does not generate a busy indicator at the end of the conversion. In this mode, CONVST remains high from the start of the conversion until all data bits are read. When started, the conversion continues regardless of the state of SCLK.

ai_iface_tim_daisy_nobusy_bas616.gifFigure 55. Interface Timing Diagram: Daisy-Chain Mode Without a Busy Indicator

At the end of the conversion, every device in the chain initiates an output of its conversion data starting with the MSB bit. Furthermore, the next lower data bit is output on every subsequent SCLK falling edge. While every device outputs its data on the SDO pin, each device also receives the previous device data on the SDI pin (other than device 1) and stores the data in the shift register. The device latches incoming data on every SCLK falling edge. The SDO of the first device in the chain goes low after the 16th SCLK falling edge. All subsequent devices in the chain output the stored data from the previous device in MSB-first format immediately following their own data word. 16 × N clocks must read data for N devices in the chain.

9.4.3.2 Daisy-Chain Mode With a Busy Indicator

A connection diagram for this mode is shown in Figure 56. The SDI for device 1 is wired to its CONVST and the CONVST for all devices in the chain are wired together. The SDO of device 1 goes to the SDI of device 2, and so on. The SDO of the last device in the chain goes to the digital host. There is no CS signal in this mode.

ai_conex_daisy_busy_bas677.gifFigure 56. Connection Diagram: Daisy Chain Mode With a Busy Indicator (SDI = 0)

On the CONVST rising edge, all devices in the chain sample the analog input and enter the conversion phase. For the first device, SDI and CONVST are wired together and the setup time of SDI to the CONVST rising edge is adjusted so that the device still enters daisy-chain mode even though SDI and CONVST rise together. SCLK must be high at the CONVST rising edge (as shown in Figure 57) so that the device generates a busy indicator at the end of the conversion. In this mode, CONVST remains high from the start of the conversion until all data bits are read. When started, the conversion continues regardless of the state of SCLK.

ai_iface_tim_daisy_busy_bas616.gifFigure 57. Interface Timing Diagram: Daisy Chain Mode With a Busy Indicator

At the end of the conversion, all devices in the chain generate busy indicators. On the first SCLK falling edge following the busy indicator bit, all devices in the chain output their conversion data starting with the MSB bit. Afterwards, the next lower data bit is output on every SCLK falling edge. While every device outputs its data on the SDO pin, each device also receives the previous device data on the SDI pin (except for device 1) and stores the data in the shift register. Each device latches incoming data on every SCLK falling edge. The SDO of the first device in the chain goes high after the 17th SCLK falling edge. All subsequent devices in the chain output the stored data from the pervious device in MSB-first format immediately following their own data word. 16 × N + 1 clock pulses are required to read data for N devices in the chain.

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

To obtain the best performance from a high-precision successive approximation register (SAR) analog-to-digital converter (ADC), the reference driver and the input driver circuit must be optimized. This section details general principles for designing such drivers, followed by typical application circuits designed using the ADS8339.

10.1.1 ADC Reference Driver

A simplified circuit diagram for such a reference driver is shown in Figure 58.The external voltage reference must provide a low-noise, low-drift, highly-accurate voltage for the ADC reference input pin. The output broadband noise of most voltage references can be in the order of a few hundred μVRMS, which degrades the conversion result. To prevent any noticeable degradation in the noise performance of the ADC, the noise from the voltage reference must be filtered. This filtering can be done by using a low-pass filter with a cutoff frequency of a few hundred hertz.

ai_ref_driver_sch_sbas677.gifFigure 58. Reference Driver Schematic

During the conversion process, the ADS8339 switches binary-weighted capacitors onto the reference pin (REFIN). The switching frequency is proportional to the internal conversion clock frequency. The dynamic charge required by the capacitors is a function of the ADC input voltage and the reference voltage. Design the reference driver circuit such that the dynamic loading of the capacitors can be handled without degrading the noise and linearity performance of the ADC.

When the noise of the voltage reference is band-limited the next step is to design a reference buffer that can drive the dynamic load posed during the conversion cycle. The buffer must regulate the voltage at the REFIN pin of the device such that the reference voltage to the ADC stays within 1 LSB of an error at the start of each conversion. This condition necessitates the use of a large capacitor, CBUF_FLT (as shown in Figure 58). The amplifier selected as the buffer must have very low offset, temperature drift, and output impedance to drive the internal binary-weighted capacitors at the REFIN pin of the ADC without any stability issues.

10.1.1.1 Reference Driver Circuit

A more detailed circuit shows the schematic (as shown in Figure 59) of a complete reference driver circuit that generates 4.5 V dc using a single 5-V supply. This circuit can drive the reference pin of the ADS8339 at sampling rates of up to 250 kSPS. The 4.5-V reference voltage is generated using a high-precision, low-noise REF5045. The output broadband noise of the reference is further filtered using a low-pass filter with a 3-dB cutoff frequency of 16 Hz.

apps_ref_driver_4V_se_8864_sbas677.gifFigure 59. Reference Driver Circuit Schematic

The driver also includes a THS4281 and an OPA333. This composite architecture provides superior ac and dc performance at reduced power levels compared to a single high-performance amplifier.

The THS4281 is a high-bandwidth amplifier with very low output impedance of 1 Ω at a frequency of 1 MHz. The low output impedance makes the THS4281 a good choice for driving large capacitive loads. The high offset and drift specifications of the THS4281 are corrected using a dc-correcting amplifier (OPA333) inside the feedback loop. Thus, the composite scheme also inherits the extremely low offset and temperature drift specifications of the OPA333.

10.1.2 ADC Input Driver

The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and an RC filter. An amplifier is used for signal conditioning the input voltage. The low output impedance of the amplifier functions as a buffer between the signal source and the sampling capacitor input of the ADC. The RC filter functions as an antialiasing filter that band-limits the wideband noise contributed by the front-end circuit. The RC filter also helps attenuate the sampling capacitor charge injection from the switched-capacitor input stage of the ADC. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a high-precision, 16-bit ADC such as the ADS8339.

10.1.2.1 Input Amplifier Selection

Selection criteria for the input amplifier is dependent on the input signal type as well as performance goals of the data acquisition system. Some key specifications to consider when selecting an amplifier to drive the inputs of the ADS8339 are:

  • Small-signal bandwidth. The small-signal bandwidth of the input amplifier must be as high as possible for a given power budget. Higher bandwidth reduces the closed-loop output impedance of the amplifier, thus allowing the amplifier to more easily drive the RC filter (with low cutoff frequency) at the inputs of the ADC. Higher bandwidth also minimizes harmonic distortion at higher input frequencies. In order to maintain overall stability, the amplifier bandwidth must satisfy Equation 1:
    • Equation 1. apps_eqn_ugb_bas547.gif
  • Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in the overall SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data acquisition system is not limited by the front-end circuit, keep the total noise contribution from the front-end circuit below 20% of the input-referred noise of the ADC. Noise from the input driver circuit gets band-limited by the RC filter, as given in Equation 2.
    • Equation 2. apps_eqn_noise_bas547.gif

    where

    • V1 / f_AMP_PP is the peak-to-peak flicker noise in µV,
    • en_RMS is the amplifier broadband noise density in nV/√Hz,
    • f–3dB is the 3-dB bandwidth of the RC filter, and
    • NG is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration.
  • Distortion. The ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end circuit, the distortion of the input driver must be at least 10 dB lower than the distortion of the ADC, as given in Equation 3.
    • Equation 3. apps_eqn_thd_bas547.gif
  • Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal must settle to a 16-bit accuracy level at the device inputs during the acquisition time. This condition is critical in maintaining the overall linearity of the ADC. Typically, the amplifier data sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired 16-bit accuracy. Therefore, the settling behavior of the input driver must always be verified by TINA™-SPICE simulations before selecting the amplifier.

10.1.2.2 Antialiasing Filter

Converting analog-to-digital signals requires sampling the input signal at a constant rate. Any frequency content in the input signal that is beyond half the sampling frequency is folded back into the low-frequency spectrum, which is undesirable. This process is called aliasing. An analog antialiasing filter must be used to remove the high-frequency component (beyond half the sampling frequency) from the input signal before being sampled by the ADC.

An antialiasing filter is designed as a low-pass, RC filter for which the 3-dB bandwidth is optimized based on specific application requirements. For dc signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow for accurate settling of the signal at the input of the ADC. For ac signals, keep the filter bandwidth as low as possible to band-limit the noise fed into the ADC, which improves the signal-to-noise ratio (SNR) performance of the system.

The RC filter also helps absorb the sampling charge injection from the switched-capacitor input of the ADC. A filter capacitor, CFLT, is connected across the inputs of the ADC (as shown in Figure 60). This capacitor helps absorb the sampling capacitor charge injection in addition to functioning as a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition phase.

When selecting this capacitor, as a rule of thumb, the capacitor value must be at least 10 times the ADC sampling capacitor specified on the data sheet. The input sampling capacitance is approximately 59 pF for the ADS8339. The value of CFLT must be greater than 590 pF. The capacitor must be a COG- or NPO-type because these capacitor types have a high-Q, low-temperature coefficient and stable electrical characteristics under varying voltages, frequency, and time.

apps_aaf_sbas677.gifFigure 60. Antialiasing Filter

NOTE

Driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid stability issues, series isolation resistors (RFLT) are used at the output of the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective. Distortion increases with source impedance, input signal frequency, and input signal amplitude. The selection of RFLT thus requires a balance between stability and distortion of the design.

TI recommends limiting the value of RFLT to a maximum of 44 Ω in order to avoid any significant degradation in linearity performance for the ADS8339. The tolerance of resistors can be 1% because the differential capacitor at the input balances the effects resulting from resistor mismatch.

The input amplifier bandwidth must be much higher than the cutoff frequency of the antialiasing filter. TI strongly recommends running a SPICE simulation to confirm that the amplifier has more than 40° phase margin with the filter that is designed. Simulation is critical because some amplifiers may require more bandwidth than others to drive similar filters. If an amplifier has less than 40° phase margin with 44-Ω resistors, using a different amplifier with higher bandwidth or reducing the filter cutoff frequency with a larger differential capacitor is advisable.

10.2 Typical Application

This section describes a typical application circuit using the ADS8339. The circuit is optimized to derive the best ac performance. For simplicity, power-supply decoupling capacitors are not shown in these circuit diagrams.

apps_daq_low_distortion_sch_8339.gifFigure 61. Single-Ended Input DAQ Circuit for Lowest Distortion and Noise at 250 kSPS

10.2.1 Design Requirements

The application circuit for the ADS8339 (as shown in Figure 61) is optimized for lowest distortion and noise for a 10-kHz input signal to achieve:

  • –106-dB THD and 93-dB SNR at a maximum specified throughput of 250 kSPS.

10.2.2 Detailed Design Procedure

In the application circuit, the input signal is processed through a high-bandwidth, low-distortion, inverting amplifier and a low-pass RC filter before being fed to the ADC.

The reference driver circuit illustrated in Figure 59 generates 4.5 V dc using a single 5-V supply. This circuit is suitable to drive the reference at sampling rates of up to 250 kSPS. To keep the noise low, a high-precision REF5045 is used. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 16 Hz.

The reference buffer is designed in a composite architecture to achieve superior dc and ac performance at reduced power consumption. The low output impedance makes the THS4281 a good choice for driving large capacitive loads that regulate the voltage at the reference input pin of the ADC. The high offset and drift specifications of the THS4281 are corrected by using a dc-correcting amplifier (such as the OPA333) inside the feedback loop.

For the input driver, as a rule of thumb, the distortion of the amplifier must be at least 10 dB less than the ADC distortion. The distortion resulting from variation in the common-mode signal is eliminated by using the driver in an inverting gain configuration. This configuration also eliminates the need for an amplifier that supports rail-to-rail input. The OPA836 is a good choice for an input driver because of its low-power consumption and exceptional ac performance (such as low distortion and high bandwidth).

Finally, the components of the antialiasing filter are chosen such that the noise from the front-end circuit is kept low without adding distortion to the input signal.

10.2.3 Application Curve

To ensure that the circuit meets the design requirements, the dc noise performance and the frequency content of the digitized output is verified. The input is set to a fixed dc value at half the reference. The histogram of the output code shows a peak-to-peak noise distribution of four codes which translates to 14 bits of noise-free bits.

An ac signal at 10 kHz is then fed to the input. The FFT of the output shows a THD of –106 dB and an SNR of 92 dB, which is close to the design requirements.

C043_SBAS677.png
VDIFF = Vref / 2, 2048 data points, standard deviation = 0.41 bits
Figure 62. DC Input Histogram at Mid-Code
C044_SBAS677.png
SNR = 92 dB, THD = – 106 dB, number of samples = 1024
Figure 63. 0.4-dBFS, 10-kHz Sine Input FFT

10.3 Do's and Don'ts

  • Use multiple capacitors to decouple the dynamic current transients at various input pins including the reference, supply, and input signal.
  • Parasitic inductance can induce ringing on the clock signal. Include a resistor on the SCLK pin to clean up the clock edges.

 
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