SBAS619A March   2014  – June 2017 AFE5401-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Digital Characteristics
    7. 6.7  Timing Requirements: Output Interface
    8. 6.8  Timing Requirements: RESET
    9. 6.9  Timing Requirements: Serial Interface Operation
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Timing Requirements: Across Output Serialization Modes
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Low-Noise Amplifier (LNA)
      2. 9.3.2 Programmable Gain Amplifier (PGA)
      3. 9.3.3 Antialiasing Filter
      4. 9.3.4 Analog-to-Digital Converter (ADC)
      5. 9.3.5 Digital Gain
      6. 9.3.6 Input Clock Divider
      7. 9.3.7 Data Output Serialization
      8. 9.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
        1. 9.3.8.1 Main Channels
        2. 9.3.8.2 Auxiliary Channel
    4. 9.4 Device Functional Modes
      1. 9.4.1 Equalizer Mode
      2. 9.4.2 Data Output Mode
        1. 9.4.2.1 Header
        2. 9.4.2.2 Test Pattern Mode
      3. 9.4.3 Parity
      4. 9.4.4 Standby, Power-Down Mode
      5. 9.4.5 Digital Filtering to Improve Stop-Band Attenuation
        1. 9.4.5.1 Decimate-by-2 Mode
        2. 9.4.5.2 Decimate-by-4 Mode
      6. 9.4.6 Diagnostic Mode
      7. 9.4.7 Signal Chain Probe
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
      2. 9.5.2 Register Initialization
        1. 9.5.2.1 Register Write Mode
        2. 9.5.2.2 Register Read Mode
      3. 9.5.3 CMOS Output Interface
        1. 9.5.3.1 Synchronization and Triggering
    6. 9.6 Register Maps
      1. 9.6.1 Functional Register Map
      2. 9.6.2 Register Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Power Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Integrated Analog Front-End Includes:
    • Quad LNA, Equalizer, PGA, Antialiasing Filter, and ADC
  • Input-Referred Noise with 30-dB PGA Gain:
    • 2.9-nV/√Hz for 15-dB LNA Gain
    • 2.0-nV/√Hz for 18-dB LNA Gain with HIGH_POW_LNA Mode
  • Simultaneous Sampling Across Channels
  • Programmable LNA Gain:
    12 dB, 15 dB, 16.5 dB, and 18 dB
  • Programmable Equalizer Modes
  • Built-In Diagnostic Modes
  • Temperature Sensor
  • Programmable-Gain Amplifiers (PGAs):
    • 0 dB to 30 dB in 3-dB Steps
  • Programmable, Third-Order, Antialiasing Filter:
    • 7 MHz, 8 MHz, 10.5 MHz, and 12 MHz
  • Analog-to-Digital Converter (ADC):
    • Quad Channel, 12 Bits, 25 MSPS per Channel
    • No External Decoupling Required for References
  • Parallel CMOS Outputs
  • 64-mW Total Core Power per Channel at
    25 MSPS per Channel
  • Supplies: 1.8 V and 3.3 V
  • Package: 9-mm × 9-mm VQFN-64

2 Applications

  • Automotive Radar
  • Data Acquisition
  • SONAR™

3 Description

The AFE5401-Q1 is an analog front-end (AFE), targeting applications where the level of integration is critical. The device includes four channels, with each channel comprising a low-noise amplifier (LNA), a programmable equalizer (EQ), a programmable gain amplifier (PGA), and an antialias filter followed by a high-speed, 12-bit, analog-to-digital converter (ADC) at 25 MSPS per channel.

Each of the four differential input pairs are amplified by an LNA and are followed by a PGA with a programmable gain range from 0 dB to 30 dB. An antialias, low-pass filter (LPF) is also integrated between the PGA and ADC for each channel.

Each LNA, PGA, and antialiasing filter output is differential (limited to 2 VPP). The antialiasing filter drives the on-chip, 12-bit, 25-MSPS ADC. The four ADC outputs are multiplexed on a 12-bit, parallel, CMOS output bus.

The device is available in a 9-mm × 9-mm, VQFN-64 package and is specified over a temperature range of –40°C to +105°C. For more information, contact AFE5401_info@list.ti.com.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
AFE5401-Q1 VQFN (64) 9.00 mm × 9.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

AFE5401-Q1 alt_sbas619.gif