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  • AM335x Sitara™ Processors

    • SPRS717L October   2011  – March 2020 AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359

      PRODUCTION DATA.  

  • CONTENTS
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  • AM335x Sitara™ Processors
  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
      1. 4.1.1 ZCE Package Pin Maps (Top View)
        1. Table 4-1 ZCE Pin Map [Section Left - Top View]
        2.       ZCE Pin Map [Section Middle - Top View]
        3.       ZCE Pin Map [Section Right - Top View]
      2. 4.1.2 ZCZ Package Pin Maps (Top View)
        1.       ZCZ Pin Map [Section Left - Top View]
        2.       ZCZ Pin Map [Section Middle - Top View]
        3.       ZCZ Pin Map [Section Right - Top View]
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 External Memory Interfaces
      2. 4.3.2 General-Purpose IOs
      3. 4.3.3 Miscellaneous
        1. 4.3.3.1 eCAP
        2. 4.3.3.2 eHRPWM
        3. 4.3.3.3 eQEP
        4. 4.3.3.4 Timer
      4. 4.3.4 PRU-ICSS
        1. 4.3.4.1 PRU0
        2. 4.3.4.2 PRU1
      5. 4.3.5 Removable Media Interfaces
      6. 4.3.6 Serial Communication Interfaces
        1. 4.3.6.1 CAN
        2. 4.3.6.2 GEMAC_CPSW
        3. 4.3.6.3 I2C
        4. 4.3.6.4 McASP
        5. 4.3.6.5 SPI
        6. 4.3.6.6 UART
        7. 4.3.6.7 USB
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Operating Performance Points (OPPs)
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Power Consumption Summary
    7. 5.7  DC Electrical Characteristics
    8. 5.8  Thermal Resistance Characteristics for ZCE and ZCZ Packages
    9. 5.9  External Capacitors
      1. 5.9.1 Voltage Decoupling Capacitors
        1. 5.9.1.1 Core Voltage Decoupling Capacitors
        2. 5.9.1.2 I/O and Analog Voltage Decoupling Capacitors
      2. 5.9.2 Output Capacitors
    10. 5.10 Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters
  6. 6Power and Clocking
    1. 6.1 Power Supplies
      1. 6.1.1 Power Supply Slew Rate Requirement
      2. 6.1.2 Power-Down Sequencing
      3. 6.1.3 VDD_MPU_MON Connections
      4. 6.1.4 Digital Phase-Locked Loop Power Supply Requirements
    2. 6.2 Clock Specifications
      1. 6.2.1 Input Clock Specifications
      2. 6.2.2 Input Clock Requirements
        1. 6.2.2.1 OSC0 Internal Oscillator Clock Source
          1. Table 6-2 OSC0 Crystal Circuit Requirements
          2. Table 6-3 OSC0 Crystal Circuit Characteristics
        2. 6.2.2.2 OSC0 LVCMOS Digital Clock Source
        3. 6.2.2.3 OSC1 Internal Oscillator Clock Source
          1. Table 6-5 OSC1 Crystal Circuit Requirements
          2. Table 6-6 OSC1 Crystal Circuit Characteristics
        4. 6.2.2.4 OSC1 LVCMOS Digital Clock Source
        5. 6.2.2.5 OSC1 Not Used
      3. 6.2.3 Output Clock Specifications
      4. 6.2.4 Output Clock Characteristics
        1. 6.2.4.1 CLKOUT1
        2. 6.2.4.2 CLKOUT2
  7. 7Peripheral Information and Timings
    1. 7.1  Parameter Information
      1. 7.1.1 Timing Parameters and Board Routing Analysis
    2. 7.2  Recommended Clock and Control Signal Transition Behavior
    3. 7.3  OPP50 Support
    4. 7.4  Controller Area Network (CAN)
      1. 7.4.1 DCAN Electrical Data and Timing
        1. Table 7-1 DCAN Timing Conditions
        2. Table 7-2 Timing Requirements for DCANx Receive
        3. Table 7-3 Switching Characteristics for DCANx Transmit
    5. 7.5  DMTimer
      1. 7.5.1 DMTimer Electrical Data and Timing
        1. Table 7-4 DMTimer Timing Conditions
        2. Table 7-5 Timing Requirements for DMTimer [1-7]
        3. Table 7-6 Switching Characteristics for DMTimer [4-7]
    6. 7.6  Ethernet Media Access Controller (EMAC) and Switch
      1. 7.6.1 EMAC and Switch Electrical Data and Timing
        1. Table 7-7 EMAC and Switch Timing Conditions
        2. 7.6.1.1   EMAC/Switch MDIO Electrical Data and Timing
          1. Table 7-8  Timing Requirements for MDIO_DATA
          2. Table 7-9  Switching Characteristics for MDIO_CLK
          3. Table 7-10 Switching Characteristics for MDIO_DATA
        3. 7.6.1.2   EMAC and Switch MII Electrical Data and Timing
          1. Table 7-11 Timing Requirements for GMII[x]_RXCLK - MII Mode
          2. Table 7-12 Timing Requirements for GMII[x]_TXCLK - MII Mode
          3. Table 7-13 Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
          4. Table 7-14 Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
        4. 7.6.1.3   EMAC and Switch RMII Electrical Data and Timing
          1. Table 7-15 Timing Requirements for RMII[x]_REFCLK - RMII Mode
          2. Table 7-16 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
          3. Table 7-17 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
        5. 7.6.1.4   EMAC and Switch RGMII Electrical Data and Timing
          1. Table 7-18 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
          2. Table 7-19 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
          3. Table 7-20 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
          4. Table 7-21 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
    7. 7.7  External Memory Interfaces
      1. 7.7.1 General-Purpose Memory Controller (GPMC)
        1. 7.7.1.1 GPMC and NOR Flash—Synchronous Mode
          1. Table 7-22 GPMC and NOR Flash Timing Conditions—Synchronous Mode
          2. Table 7-23 GPMC and NOR Flash Timing Requirements—Synchronous Mode
          3. Table 7-24 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
        2. 7.7.1.2 GPMC and NOR Flash—Asynchronous Mode
          1. Table 7-25 GPMC and NOR Flash Timing Conditions—Asynchronous Mode
          2. Table 7-26 GPMC and NOR Flash Internal Timing Requirements—Asynchronous Mode
          3. Table 7-27 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
          4. Table 7-28 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
        3. 7.7.1.3 GPMC and NAND Flash—Asynchronous Mode
          1. Table 7-29 GPMC and NAND Flash Timing Conditions—Asynchronous Mode
          2. Table 7-30 GPMC and NAND Flash Internal Timing Requirements—Asynchronous Mode
          3. Table 7-31 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
          4. Table 7-32 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
      2. 7.7.2 mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface
        1. 7.7.2.1 mDDR (LPDDR) Routing Guidelines
          1. 7.7.2.1.1 Board Designs
          2. 7.7.2.1.2 LPDDR Interface
            1. 7.7.2.1.2.1 LPDDR Interface Schematic
            2. 7.7.2.1.2.2 Compatible JEDEC LPDDR Devices
              1. Table 7-34 Compatible JEDEC LPDDR Devices (Per Interface)
            3. 7.7.2.1.2.3 PCB Stackup
            4. 7.7.2.1.2.4 Placement
            5. 7.7.2.1.2.5 LPDDR Keepout Region
            6. 7.7.2.1.2.6 Bulk Bypass Capacitors
            7. 7.7.2.1.2.7 High-Speed Bypass Capacitors
            8. 7.7.2.1.2.8 Net Classes
            9. 7.7.2.1.2.9 LPDDR Signal Termination
          3. 7.7.2.1.3 LPDDR CK and ADDR_CTRL Routing
        2. 7.7.2.2 DDR2 Routing Guidelines
          1. 7.7.2.2.1 Board Designs
          2. 7.7.2.2.2 DDR2 Interface
            1. 7.7.2.2.2.1  DDR2 Interface Schematic
            2. 7.7.2.2.2.2  Compatible JEDEC DDR2 Devices
              1. Table 7-46 Compatible JEDEC DDR2 Devices (Per Interface)
            3. 7.7.2.2.2.3  PCB Stackup
            4. 7.7.2.2.2.4  Placement
            5. 7.7.2.2.2.5  DDR2 Keepout Region
            6. 7.7.2.2.2.6  Bulk Bypass Capacitors
            7. 7.7.2.2.2.7  High-Speed (HS) Bypass Capacitors
            8. 7.7.2.2.2.8  Net Classes
            9. 7.7.2.2.2.9  DDR2 Signal Termination
            10. 7.7.2.2.2.10 DDR_VREF Routing
          3. 7.7.2.2.3 DDR2 CK and ADDR_CTRL Routing
        3. 7.7.2.3 DDR3 and DDR3L Routing Guidelines
          1. 7.7.2.3.1 Board Designs
            1. 7.7.2.3.1.1 DDR3 versus DDR2
          2. 7.7.2.3.2 DDR3 Device Combinations
          3. 7.7.2.3.3 DDR3 Interface
            1. 7.7.2.3.3.1  DDR3 Interface Schematic
            2. 7.7.2.3.3.2  Compatible JEDEC DDR3 Devices
            3. 7.7.2.3.3.3  PCB Stackup
            4. 7.7.2.3.3.4  Placement
            5. 7.7.2.3.3.5  DDR3 Keepout Region
            6. 7.7.2.3.3.6  Bulk Bypass Capacitors
            7. 7.7.2.3.3.7  High-Speed Bypass Capacitors
              1. 7.7.2.3.3.7.1 Return Current Bypass Capacitors
            8. 7.7.2.3.3.8  Net Classes
            9. 7.7.2.3.3.9  DDR3 Signal Termination
            10. 7.7.2.3.3.10 DDR_VREF Routing
            11. 7.7.2.3.3.11 VTT
          4. 7.7.2.3.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
            1. 7.7.2.3.4.1 Two DDR3 Devices
              1. 7.7.2.3.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
              2. 7.7.2.3.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
            2. 7.7.2.3.4.2 One DDR3 Device
              1. 7.7.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device
              2. 7.7.2.3.4.2.2 CK and ADDR_CTRL Routing, One DDR3 Device
          5. 7.7.2.3.5 Data Topologies and Routing Definition
            1. 7.7.2.3.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
            2. 7.7.2.3.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
          6. 7.7.2.3.6 Routing Specification
            1. 7.7.2.3.6.1 CK and ADDR_CTRL Routing Specification
            2. 7.7.2.3.6.2 DQS[x] and DQ[x] Routing Specification
    8. 7.8  I2C
      1. 7.8.1 I2C Electrical Data and Timing
        1. Table 7-70 I2C Timing Conditions – Slave Mode
        2. Table 7-71 Timing Requirements for I2C Input Timings
        3. Table 7-72 Switching Characteristics for I2C Output Timings
    9. 7.9  JTAG Electrical Data and Timing
      1. Table 7-73 JTAG Timing Conditions
      2. Table 7-74 Timing Requirements for JTAG
      3. Table 7-75 Switching Characteristics for JTAG
    10. 7.10 LCD Controller (LCDC)
      1. Table 7-76 LCD Controller Timing Conditions
      2. 7.10.1     LCD Interface Display Driver (LIDD Mode)
        1. Table 7-77 Timing Requirements for LCD LIDD Mode
        2. Table 7-78 Switching Characteristics for LCD LIDD Mode
      3. 7.10.2     LCD Raster Mode
        1. Table 7-79 Switching Characteristics for LCD Raster Mode
    11. 7.11 Multichannel Audio Serial Port (McASP)
      1. 7.11.1 McASP Device-Specific Information
      2. 7.11.2 McASP Electrical Data and Timing
        1. Table 7-80 McASP Timing Conditions
        2. Table 7-81 Timing Requirements for McASP
        3. Table 7-82 Switching Characteristics for McASP
    12. 7.12 Multichannel Serial Port Interface (McSPI)
      1. 7.12.1 McSPI Electrical Data and Timing
        1. 7.12.1.1 McSPI—Slave Mode
          1. Table 7-83 McSPI Timing Conditions – Slave Mode
          2. Table 7-84 Timing Requirements for McSPI Input Timings—Slave Mode
          3. Table 7-85 Switching Characteristics for McSPI Output Timings—Slave Mode
        2. 7.12.1.2 McSPI—Master Mode
          1. Table 7-86 McSPI Timing Conditions – Master Mode
          2. Table 7-87 Timing Requirements for McSPI Input Timings – Master Mode
          3. Table 7-88 Switching Characteristics for McSPI Output Timings – Master Mode
    13. 7.13 Multimedia Card (MMC) Interface
      1. 7.13.1 MMC Electrical Data and Timing
        1. Table 7-89 MMC Timing Conditions
        2. Table 7-90 Timing Requirements for MMC[x]_CMD and MMC[x]_DAT[7:0]
        3. Table 7-91 Switching Characteristics for MMC[x]_CLK
        4. Table 7-92 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—Standard Mode
        5. Table 7-93 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—High-Speed Mode
    14. 7.14 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      1. 7.14.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. Table 7-94 PRU-ICSS PRU Timing Conditions
        2. 7.14.1.1   PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
          1. Table 7-95 PRU-ICSS PRU Timing Requirements - Direct Input Mode
          2. Table 7-96 PRU-ICSS PRU Switching Requirements – Direct Output Mode
        3. 7.14.1.2   PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
          1. Table 7-97 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
        4. 7.14.1.3   PRU-ICSS PRU Shift Mode Electrical Data and Timing
          1. Table 7-98 PRU-ICSS PRU Timing Requirements – Shift In Mode
          2. Table 7-99 PRU-ICSS PRU Switching Requirements - Shift Out Mode
      2. 7.14.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. Table 7-100 PRU-ICSS ECAT Timing Conditions
        2. 7.14.2.1    PRU-ICSS ECAT Electrical Data and Timing
          1. Table 7-101 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
          2. Table 7-102 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
          3. Table 7-103 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
          4. Table 7-104 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
          5. Table 7-105 PRU-ICSS ECAT Switching Requirements - Digital I/Os
      3. 7.14.3 PRU-ICSS MII_RT and Switch
        1. Table 7-106 PRU-ICSS MII_RT Switch Timing Conditions
        2. 7.14.3.1    PRU-ICSS MDIO Electrical Data and Timing
          1. Table 7-107 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
          2. Table 7-108 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
          3. Table 7-109 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
        3. 7.14.3.2    PRU-ICSS MII_RT Electrical Data and Timing
          1. Table 7-110 PRU-ICSS MII_RT Timing Requirements – MII_RXCLK
          2. Table 7-111 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
          3. Table 7-112 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
          4. Table 7-113 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
      4. 7.14.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
        1. Table 7-114 UART Timing Conditions
        2. Table 7-115 Timing Requirements for PRU-ICSS UART Receive
        3. Table 7-116 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
      1. 7.15.1 UART Electrical Data and Timing
        1. Table 7-117 UART Timing Conditions
        2. Table 7-118 Timing Requirements for UARTx Receive
        3. Table 7-119 Switching Characteristics for UARTx Transmit
      2. 7.15.2 UART IrDA Interface
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Via Channel
    2. 9.2 Packaging Information
  10. IMPORTANT NOTICE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZCZ|324
  • ZCE|298
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sprs717l_oa
  • sprs717l_pm
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    • Full reading width
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    • Expanded reading width
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DATA SHEET

AM335x Sitara™ Processors

1 Device Overview

1.1 Features

  • Up to 1-GHz Sitara™ARM®Cortex®-A8 32‑Bit RISC Processor
    • NEON™ SIMD Coprocessor
    • 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
    • 256KB of L2 Cache With Error Correcting Code (ECC)
    • 176KB of On-Chip Boot ROM
    • 64KB of Dedicated RAM
    • Emulation and Debug - JTAG
    • Interrupt Controller (up to 128 Interrupt Requests)
  • On-Chip Memory (Shared L3 RAM)
    • 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
  • External Memory Interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
      • mDDR: 200-MHz Clock (400-MHz Data Rate)
      • DDR2: 266-MHz Clock (532-MHz Data Rate)
      • DDR3: 400-MHz Clock (800-MHz Data Rate)
      • DDR3L: 400-MHz Clock (800-MHz Data Rate)
      • 16-Bit Data Bus
      • 1GB of Total Addressable Space
      • Supports One x16 or Two x8 Memory Device Configurations
    • General-Purpose Memory Controller (GPMC)
      • Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
      • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More
    • Two Programmable Real-Time Units (PRUs)
      • 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
      • 8KB of Instruction RAM With Single-Error Detection (Parity)
      • 8KB of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
    • 12KB of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS:
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One Enhanced Capture (eCAP) Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
    • Power
      • Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
      • Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
      • Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
    • Independent Power-on-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
    • Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
    • Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v1 Precision Time Protocol (PTP)
    • Up to Two Controller-Area Network (CAN) Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Two Master and Slave McSPI Serial Interfaces
      • Up to Two Chip Selects
      • Up to 48 MHz
    • Up to Three MMC, SD, SDIO Ports
      • 1-, 4- and 8-Bit MMC, SD, SDIO Modes
      • MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
      • Up to 48-MHz Data Transfer Rate
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3, SD, SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Four Banks of General-Purpose I/O (GPIO) Pins
      • 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
      • GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
    • Eight 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Watchdog Timer
    • SGX530 3D Graphics Engine
      • Tile-Based Architecture Delivering up to 20 Million Polygons per Second
      • Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
      • Programmable High-Quality Image Anti-Aliasing
      • Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
    • LCD Controller
      • Up to 24-Bit Data Output; 8 Bits per Pixel (RGB)
      • Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)
      • Integrated LCD Interface Display Driver (LIDD) Controller
      • Integrated Raster Controller
      • Integrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer
      • 512-Word Deep Internal FIFO
      • Supported Display Types:
        • Character Displays - Uses LIDD Controller to Program these Displays
        • Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display
        • Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel
    • 12-Bit Successive Approximation Register (SAR) ADC
      • 200K Samples per Second
      • Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
      • Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) Interface
    • Up to Three 32-Bit eCAP Modules
      • Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
    • Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
    • Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Device Identification
    • Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
  • Inter-Processor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox Registers that Generate Interrupts
        • Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
      • Spinlock has 128 Software-Assigned Lock Registers
  • Security
    • Crypto Hardware Accelerators (AES, SHA, RNG)
    • Secure Boot (optional; requires custom part engagement with TI)
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Packages:
    • 298-Pin S-PBGA-N298 Via Channel Package
      (ZCE Suffix), 0.65-mm Ball Pitch
    • 324-Pin S-PBGA-N324 Package
      (ZCZ Suffix), 0.80-mm Ball Pitch

1.2 Applications

  • Gaming Peripherals
  • Home and Industrial Automation
  • Consumer Medical Appliances
  • Printers
  • Smart Toll Systems
  • Connected Vending Machines
  • Weighing Scales
  • Educational Consoles
  • Advanced Toys

1.3 Description

The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI.

The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE
AM3359ZCZ NFBGA (324) 15.0 mm × 15.0 mm
AM3358ZCZ NFBGA (324) 15.0 mm × 15.0 mm
AM3357ZCZ NFBGA (324) 15.0 mm × 15.0 mm
AM3356ZCZ, AM3356ZCE NFBGA (324), NFBGA (298) 15.0 mm × 15.0 mm, 13.0 mm × 13.0 mm
AM3354ZCZ, AM3354ZCE NFBGA (324), NFBGA (298) 15.0 mm × 15.0 mm, 13.0 mm × 13.0 mm
AM3352ZCZ, AM3352ZCE NFBGA (324), NFBGA (298) 15.0 mm × 15.0 mm, 13.0 mm × 13.0 mm
AM3351ZCE NFBGA (298) 13.0 mm × 13.0 mm
(1) For more information, see Section 9, Mechanical, Packaging, and Orderable Information.

1.4 Functional Block Diagram

Figure 1-1 shows the AM335x microprocessor functional block diagram.

AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 fbd_SPRS717.gifFigure 1-1 AM335x Functional Block Diagram

2 Revision History

Changes from December 1, 2018 to March 31, 2020 (from K Revision (December 2018) to L Revision)

  • Changed IEEE 1588v2 feature to IEEE 1588v1. Go
  • Updated Secure Boot feature description. Go
  • Updated AM335x Functional Block Diagram. Go
  • Added U16 to rmii2_crs_dv Signal in the GEMAC_CPSW/RMII2 Signals Description table.Go
  • Updated ADC Clock Frequency in the TSC_ADC Electrical Parameters table.Go
  • Updated DCAN Timing Conditions table. Go
  • Updated DMTimer Timing Conditions table. Go
  • Updated Switching Characteristics for MDIO_DATAGo
  • Updated MDIO_DATA Timing - Output Mode image.Go
  • Added Transition time, RD and Transition time, RX_CTL to Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode.Go
  • Updated GPMC and NOR Flash—Synchronous Burst Read—4x16-Bit (GpmcFCLKDivider = 0) image. Go
  • Updated GPMC and Multiplexed NOR Flash—Synchronous Burst Write image. Go
  • Updated JTAG Timing Conditions table. Go
  • Updated MMC[x]_CLK (Output) Timing image.Go
  • Updated PRU-ICSS MDIO Switching Characteristics - MDIO_DATAGo
  • Updated PRU-ICSS MDIO_DATA Timing – Output Mode image.Go

3 Device Comparison

Table 3-1 lists the features supported across different AM335x devices.

Table 3-1 Device Features Comparison

FUNCTION AM3351 AM3352 AM3354 AM3356 AM3357 AM3358 AM3359
ARM Cortex-A8 Yes Yes Yes Yes Yes Yes Yes
Frequency(1) 300 MHz
600 MHz		 300 MHz
600 MHz
800 MHz
1000 MHz		 600 MHz
800 MHz
1000 MHz		 300 MHz
600 MHz
800 MHz		 300 MHz
600 MHz
800 MHz		 600 MHz
800 MHz
1000 MHz		 800 MHz
MIPS(2) 600
1200		 600
1200
1600
2000		 1200
1600
2000		 600
1200
1600		 600
1200
1600		 1200
1600
2000		 1600
On-chip L1 cache 64KB 64KB 64KB 64KB 64KB 64KB 64KB
On-chip L2 cache 256KB 256KB 256KB 256KB 256KB 256KB 256KB
Graphics accelerator (SGX530) — — 3D — — 3D 3D
Hardware acceleration Crypto accelerator Crypto accelerator Crypto accelerator Crypto accelerator Crypto accelerator Crypto accelerator Crypto accelerator
Programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) — — — Features including basic Industrial protocols;
ZCE: Limited PRU I/Os pinned out		 Features including all Industrial protocols Features including basic Industrial protocols Features including all Industrial protocols
On-chip memory 128KB 128KB 128KB 128KB 128KB 128KB 128KB
Display options LCD LCD LCD LCD LCD LCD LCD
General-purpose memory 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM)
DRAM(3) 1 16-bit (LPDDR-400, DDR2-532, DDR3-800) 1 16-bit (LPDDR-400, DDR2-532, DDR3-800) 1 16-bit (LPDDR-400, DDR2-532, DDR3-800) 1 16-bit (LPDDR-400, DDR2-532, DDR3-800) 1 16-bit (LPDDR-400, DDR2-532, DDR3-800) 1 16-bit (LPDDR-400, DDR2-532, DDR3-800) 1 16-bit (LPDDR-400, DDR2-532, DDR3-800)
Universal serial bus (USB) ZCE: 1 port ZCE: 1 port
ZCZ: 2 ports		 ZCE: 1 port
ZCZ: 2 ports		 ZCE: 1 port
ZCZ: 2 ports		 No ZCE Available
ZCZ: 2 ports		 No ZCE Available
ZCZ: 2 ports		 No ZCE Available
ZCZ: 2 ports
Ethernet media access controller (EMAC) with 2-port switch 10/100/1000
ZCE: 1 port		 10/100/1000
ZCE: 1 port
ZCZ: 2 ports		 10/100/1000
ZCE: 1 port
ZCZ: 2 ports		 10/100/1000
ZCE: 1 port
ZCZ: 2 ports		 10/100/1000
No ZCE Available
ZCZ: 2 ports		 10/100/1000
No ZCE Available
ZCZ: 2 ports		 10/100/1000
No ZCE Available
ZCZ: 2 ports
Multimedia card (MMC) 3 3 3 3 3 3 3
Controller-area network (CAN) — 2 2 2 2 2 2
Universal asynchronous receiver and transmitter (UART) 6 6 6 6 6 6 6
Analog-to-digital converter (ADC) 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit
Enhanced high-resolution PWM modules (eHRPWM) 3 3 3 3 3 3 3
Enhanced capture modules (eCAP) 3 3 3 3 3 3 3
Enhanced quadrature encoder pulse (eQEP) 3 3 3 3 3 3 3
Real-time clock (RTC) 1 1 1 1 1 1 1
Inter-integrated circuit (I2C) 3 3 3 3 3 3 3
Multichannel audio serial port (McASP) 2 2 2 2 2 2 2
Multichannel serial port interface (McSPI) 2 2 2 2 2 2 2
Enhanced direct memory access (EDMA) 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch
Input/output (I/O) supply 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V
Operating temperature range 0 to 90°C
–40 to 105°C		 -40 to 125°C(4)
–40 to 105°C
–40 to 90°C
0 to 90°C		 –40 to 105°C
–40 to 90°C
0 to 90°C		 –40 to 105°C
–40 to 90°C
0 to 90°C		 –40 to 105°C
–40 to 90°C		 –40 to 105°C
–40 to 90°C
0 to 90°C		 –40 to 105°C
–40 to 90°C
DEV_FEATURE register value(5) 0x00FC0302 0x00FC0382 0x20FC0382 0x00FD0383 0x00FF0383 0x20FD0383 0x20FF0383
  1. Frequencies listed correspond to silicon revision 2.x. Earlier silicon revisions support 275 MHz, 500 MHz, 600 MHz, and 720 MHz.
  2. MIPS listed correspond to silicon revision 2.x. Earlier silicon revisions support 560, 1000, 1200, and 1440.
  3. DRAM speeds listed are data rates.
  4. Industrial extended temperature only supported for 300-MHz and 600-MHz frequencies.
  5. For more details about the DEV_FEATURE register, see the AM335x TRM.

3.1 Related Products

For information about other devices in this family of products, see the following links:

    Sitara ProcessorsScalable processors based on ARM Cortex-A cores with flexible peripherals, connectivity and unified software support – perfect for sensors to servers.
    TI's ARM Cortex-A8 AdvantageThe ARM Cortex-A8 core is highly-optimized by ARM for performance and power efficiency. With the ability to scale in speed from 300 MHz to 1.35 GHz, the ARM Cortex-A8-based processor can meet the requirements for power optimized devices with a power budget of less than the Cortex-A8 core a dual-issue superscalar, achieving twice the instructions executed per clock cycle at 2 DMIPS/MHz.
    AM335x Sitara ProcessorsScalable ARM Cortex-A8-based core from 300 MHz up to 1 GHz, 3D graphics option for enhanced user interface, dual-core PRU-ICSS for industrial Ethernet protocols and position feedback control, and premium secure boot option.
    Companion Products for AM335x Sitara ProcessorsReview products that are frequently purchased or used with this product.
    TI Designs for AM335x Sitara ProcessorsThe TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs and design files to speed your time to market. Search and download designs at ti.com/tidesigns.

4 Terminal Configuration and Functions

4.1 Pin Diagram

NOTE

The terms 'ball', 'pin', and 'terminal' are used interchangeably throughout the document. An attempt is made to use 'ball' only when referring to the physical package.

4.1.1 ZCE Package Pin Maps (Top View)

The pin maps that follow show the pin assignments on the ZCE package in three sections (left, middle, and right).

Table 4-1 ZCE Pin Map [Section Left - Top View]

A B C D E F
19 VSS I2C0_SCL UART1_TXD UART1_RTSn UART0_RXD UART0_CTSn
18 SPI0_SCLK SPI0_D0 I2C0_SDA UART1_RXD ECAP0_IN_PWM0_OUT UART0_RTSn
17 SPI0_CS0 SPI0_D1 EXTINTn XXXX UART1_CTSn UART0_TXD
16 WARMRSTn SPI0_CS1 XXXX XXXX XXXX VDDS
15 EMU0 XDMA_EVENT_INTR1 XDMA_EVENT_INTR0 XXXX PWRONRSTn XXXX
14 TDO TCK TMS EMU1 XXXX VDDSHV6
13 TRSTn TDI CAP_VBB_MPU CAP_VDD_SRAM_MPU VDDSHV6 VSS
12 AIN7 AIN5 VDDS_SRAM_MPU_BB VDDS VDDSHV6 VSS
11 AIN1 AIN3 XXXX XXXX VDDSHV6 VDD_CORE
10 AIN6 CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VSS VSS XXXX
9 VREFP VREFN XXXX XXXX VSS VDD_CORE
8 AIN2 AIN0 AIN4 VSSA_ADC VSS VSS
7 RTC_KALDO_ENn RTC_PWRONRSTn PMIC_POWER_EN VDDA_ADC VSS VSS
6 RTC_XTALIN RESERVED VDDS_RTC CAP_VDD_RTC XXXX VSS
5 RTC_XTALOUT EXT_WAKEUP VDDS_PLL_DDR XXXX DDR_A4 XXXX
4 DDR_WEn DDR_BA2 XXXX XXXX XXXX DDR_A12
3 DDR_BA0 DDR_A3 DDR_A8 XXXX DDR_A15 DDR_A0
2 DDR_A5 DDR_A9 DDR_CK DDR_A7 DDR_A10 DDR_RASn
1 VSS DDR_A6 DDR_CKn DDR_A2 DDR_BA1 DDR_CASn
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 ball_map_left.gif

ZCE Pin Map [Section Middle - Top View]

G H J K L M
19 MMC0_CLK MMC0_DAT3 MII1_COL MII1_RX_ER MII1_RX_DV MII1_RX_CLK
18 MMC0_DAT0 MMC0_DAT2 MII1_CRS RMII1_REF_CLK MII1_TXD0 MII1_TXD1
17 MMC0_CMD MMC0_DAT1 XXXX MII1_TX_EN XXXX MII1_TXD3
16 USB0_DRVVBUS VDDS_PLL_MPU XXXX VDD_CORE XXXX VDDS
15 VDDSHV4 VDDSHV4 VSS VDD_CORE VSS VDDSHV5
14 XXXX VDDSHV4 VSS XXXX VSS VDDSHV5
13 XXXX VDD_CORE VDD_CORE XXXX VDD_CORE VDD_CORE
12 VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE
11 VDD_CORE VSS VSS VSS VSS VSS
10 XXXX VSS XXXX XXXX XXXX VSS
9 VDD_CORE VSS VSS VSS VSS VSS
8 VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE
7 XXXX VDD_CORE VDD_CORE XXXX VDD_CORE VDD_CORE
6 XXXX VDDS_DDR VSS XXXX VSS VDDS_DDR
5 VDDS_DDR VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR
4 DDR_A11 DDR_VREF XXXX VDDS_DDR XXXX DDR_D11
3 DDR_CKE DDR_A14 XXXX DDR_DQM1 XXXX DDR_D10
2 DDR_RESETn DDR_CSn0 DDR_A1 DDR_D8 DDR_DQSn1 DDR_D12
1 DDR_ODT DDR_A13 DDR_VTP DDR_D9 DDR_DQS1 DDR_D13
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 ball_map_middle.gif

ZCE Pin Map [Section Right - Top View]

N P R T U V W
19 MII1_TX_CLK MII1_RXD1 MDC USB0_VBUS USB0_DP USB0_ID VSS
18 MII1_TXD2 MII1_RXD0 VDDA3P3V_USB0 USB0_CE USB0_DM GPMC_BEn1 GPMC_WPn
17 MII1_RXD3 MDIO VDDA1P8V_USB0 XXXX GPMC_CSn3 GPMC_AD15 GPMC_AD14
16 MII1_RXD2 VSSA_USB XXXX XXXX XXXX GPMC_CLK GPMC_AD9
15 VDDSHV5 XXXX GPMC_WAIT0 XXXX GPMC_CSn2 GPMC_AD8 GPMC_AD7
14 XXXX VSS XXXX VDDS GPMC_AD6 GPMC_CSn1 GPMC_AD5
13 XXXX VSS VDDSHV1 GPMC_AD13 GPMC_AD12 GPMC_AD4 GPMC_AD3
12 VSS VSS VDDSHV1 GPMC_AD10 GPMC_AD11 GPMC_AD2 XTALOUT
11 VDD_CORE VDD_CORE VDDSHV1 XXXX XXXX VSS_OSC XTALIN
10 XXXX XXXX VSS VSS VDDS_OSC GPMC_ADVn_ALE GPMC_AD0
9 VDD_CORE VDD_CORE VDDSHV1 XXXX XXXX GPMC_AD1 GPMC_OEn_REn
8 VSS VSS VDDSHV1 VDDS_PLL_CORE_LCD GPMC_WEn GPMC_BEn0_CLE GPMC_CSn0
7 XXXX VSS VDDSHV6 LCD_HSYNC LCD_VSYNC LCD_DATA15 LCD_AC_BIAS_EN
6 XXXX VDDSHV6 XXXX VDDS LCD_DATA13 LCD_DATA12 LCD_DATA14
5 VDDS_DDR XXXX VPP XXXX LCD_DATA10 LCD_DATA11 LCD_PCLK
4 DDR_D0 DDR_D1 XXXX XXXX XXXX LCD_DATA8 LCD_DATA9
3 DDR_DQM0 DDR_D4 DDR_D7 XXXX LCD_DATA7 LCD_DATA6 LCD_DATA5
2 DDR_D14 DDR_D2 DDR_DQSn0 DDR_D6 LCD_DATA1 LCD_DATA3 LCD_DATA4
1 DDR_D15 DDR_D3 DDR_DQS0 DDR_D5 LCD_DATA0 LCD_DATA2 VSS
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 ball_map_right.gif

4.1.2 ZCZ Package Pin Maps (Top View)

The pin maps that follow show the pin assignments on the ZCZ package in three sections (left, middle, and right).

ZCZ Pin Map [Section Left - Top View]

A B C D E F
18 VSS EXTINTn ECAP0_IN_PWM0_OUT UART1_CTSn UART0_CTSn MMC0_DAT2
17 SPI0_SCLK SPI0_D0 I2C0_SDA UART1_RTSn UART0_RTSn MMC0_DAT3
16 SPI0_CS0 SPI0_D1 I2C0_SCL UART1_RXD UART0_TXD USB0_DRVVBUS
15 XDMA_EVENT_INTR0 PWRONRSTn SPI0_CS1 UART1_TXD UART0_RXD USB1_DRVVBUS
14 MCASP0_AHCLKX EMU1 EMU0 XDMA_EVENT_INTR1 VDDS VDDSHV6
13 MCASP0_ACLKX MCASP0_FSX MCASP0_FSR MCASP0_AXR1 VDDSHV6 VDD_MPU
12 TCK MCASP0_ACLKR MCASP0_AHCLKR MCASP0_AXR0 VDDSHV6 VDD_MPU
11 TDO TDI TMS CAP_VDD_SRAM_MPU VDDSHV6 VDD_MPU
10 WARMRSTn TRSTn CAP_VBB_MPU VDDS_SRAM_MPU_BB VDDSHV6 VDD_MPU
9 VREFN VREFP AIN7 CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VDDS
8 AIN6 AIN5 AIN4 VDDA_ADC VSSA_ADC VSS
7 AIN3 AIN2 AIN1 VDDS_RTC VDDS_PLL_DDR VDD_CORE
6 RTC_XTALIN AIN0 PMIC_POWER_EN CAP_VDD_RTC VDDS VDD_CORE
5 VSS_RTC RTC_PWRONRSTn EXT_WAKEUP DDR_A6 VDDS_DDR VDDS_DDR
4 RTC_XTALOUT RTC_KALDO_ENn DDR_BA0 DDR_A8 DDR_A2 DDR_A10
3 RESERVED DDR_BA2 DDR_A3 DDR_A15 DDR_A12 DDR_A0
2 VDD_MPU_MON DDR_WEn DDR_A4 DDR_CK DDR_A7 DDR_A11
1 VSS DDR_A5 DDR_A9 DDR_CKn DDR_BA1 DDR_CASn
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 ball_map_left.gif

ZCZ Pin Map [Section Middle - Top View]

G H J K L M
18 MMC0_CMD RMII1_REF_CLK MII1_TXD3 MII1_TX_CLK MII1_RX_CLK MDC
17 MMC0_CLK MII1_CRS MII1_RX_DV MII1_TXD0 MII1_RXD3 MDIO
16 MMC0_DAT0 MII1_COL MII1_TX_EN MII1_TXD1 MII1_RXD2 MII1_RXD0
15 MMC0_DAT1 VDDS_PLL_MPU MII1_RX_ER MII1_TXD2 MII1_RXD1 USB0_CE
14 VDDSHV6 VDDSHV4 VDDSHV4 VDDSHV5 VDDSHV5 VSSA_USB
13 VDD_MPU VDD_MPU VDD_MPU VDDS VSS VDD_CORE
12 VSS VSS VDD_CORE VDD_CORE VSS VSS
11 VSS VDD_CORE VSS VSS VSS VDD_CORE
10 VDD_CORE VSS VSS VSS VSS VSS
9 VSS VSS VSS VSS VDD_CORE VSS
8 VSS VSS VSS VDD_CORE VDD_CORE VSS
7 VDD_CORE VSS VSS VSS VDD_CORE VSS
6 VDD_CORE VSS VSS VDD_CORE VDD_CORE VSS
5 VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VPP
4 DDR_RASn DDR_A14 DDR_VREF DDR_D12 DDR_D14 DDR_D1
3 DDR_CKE DDR_A13 DDR_VTP DDR_D11 DDR_D13 DDR_D0
2 DDR_RESETn DDR_CSn0 DDR_DQM1 DDR_D10 DDR_DQSn1 DDR_DQM0
1 DDR_ODT DDR_A1 DDR_D8 DDR_D9 DDR_DQS1 DDR_D15
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 ball_map_middle.gif

ZCZ Pin Map [Section Right - Top View]

N P R T U V
18 USB0_DM USB1_CE USB1_DM USB1_VBUS GPMC_BEn1 VSS
17 USB0_DP USB1_ID USB1_DP GPMC_WAIT0 GPMC_WPn GPMC_A11
16 VDDA1P8V_USB0 USB0_ID VDDA1P8V_USB1 GPMC_A10 GPMC_A9 GPMC_A8
15 VDDA3P3V_USB0 USB0_VBUS VDDA3P3V_USB1 GPMC_A7 GPMC_A6 GPMC_A5
14 VSSA_USB VDDS GPMC_A4 GPMC_A3 GPMC_A2 GPMC_A1
13 VDD_CORE VDDSHV3 GPMC_A0 GPMC_CSn3 GPMC_AD15 GPMC_AD14
12 VDD_CORE VDDSHV3 GPMC_AD13 GPMC_AD12 GPMC_AD11 GPMC_CLK
11 VSS VDDSHV2 VDDS_OSC GPMC_AD10 XTALOUT VSS_OSC
10 VSS VDDSHV2 VDDS_PLL_CORE_LCD GPMC_AD9 GPMC_AD8 XTALIN
9 VDD_CORE VDDS GPMC_AD6 GPMC_AD7 GPMC_CSn1 GPMC_CSn2
8 VDD_CORE VDDSHV1 GPMC_AD2 GPMC_AD3 GPMC_AD4 GPMC_AD5
7 VSS VDDSHV1 GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD0 GPMC_AD1
6 VDDS VDDSHV6 LCD_AC_BIAS_EN GPMC_BEn0_CLE GPMC_WEn GPMC_CSn0
5 VDDSHV6 VDDSHV6 LCD_HSYNC LCD_DATA15 LCD_VSYNC LCD_PCLK
4 DDR_D5 DDR_D7 LCD_DATA3 LCD_DATA7 LCD_DATA11 LCD_DATA14
3 DDR_D4 DDR_D6 LCD_DATA2 LCD_DATA6 LCD_DATA10 LCD_DATA13
2 DDR_D3 DDR_DQSn0 LCD_DATA1 LCD_DATA5 LCD_DATA9 LCD_DATA12
1 DDR_D2 DDR_DQS0 LCD_DATA0 LCD_DATA4 LCD_DATA8 VSS
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 ball_map_right.gif

 
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