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CC110L Value Line Transceiver
SWRS109C
May 2011 – December 2016
CC110L
PRODUCTION DATA.
CONTENTS
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CC110L Value Line Transceiver
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Terminal Configuration and Functions
3.1
Pin Diagram
3.2
Signal Descriptions
4
Specifications
4.1
Absolute Maximum Ratings
4.2
Handling Ratings
4.3
Recommended Operating Conditions
4.4
General Characteristics
4.5
Current Consumption
4.5.1
Typical TX Current Consumption over Temperature and Supply Voltage, 868 MHz
4.5.2
Typical TX Current Consumption over Temperature and Supply Voltage, 915 MHz
4.6
Typical RX Current Consumption Over Temperature and Input Power Level, 868 or 915 MHz
4.7
RF Receive Section
4.7.1
Typical Sensitivity over Temperature and Supply Voltage, 868 MHz, Sensitivity Optimized Setting
4.7.2
Typical Sensitivity over Temperature and Supply Voltage, 915 MHz, Sensitivity Optimized Setting
4.7.3
Blocking and Selectivity
4.8
RF Transmit Section
4.8.1
Typical Variation in Output Power over Temperature and Supply Voltage, 868 MHz
4.8.2
Typical Variation in Output Power over Temperature and Supply Voltage, 915 MHz
4.9
Crystal Oscillator
4.10
Frequency Synthesizer Characteristics
4.11
DC Characteristics
4.12
Power-On Reset
4.13
Thermal Characteristics
4.14
Typical Characteristics
4.14.1
Typical Characteristics, RX Current Consumption
4.14.2
Typical Characteristics, Blocking and Selectivity
5
Detailed Description
5.1
Overview
5.2
Functional Block Diagram
5.3
Configuration Overview
5.4
Configuration Software
5.5
4-wire Serial Configuration and Data Interface
5.6
Chip Status Byte
5.7
Register Access
5.8
SPI Read
5.9
Command Strobes
5.10
FIFO Access
5.11
PATABLE Access
5.12
Microcontroller Interface and Pin Configuration
5.12.1
Configuration Interface
5.12.2
General Control and Status Pins
5.13
Data Rate Programming
5.14
Receiver Channel Filter Bandwidth
5.15
Demodulator, Symbol Synchronizer, and Data Decision
5.15.1
Frequency Offset Compensation
5.15.2
Bit Synchronization
5.15.3
Byte Synchronization
5.16
Packet Handling Hardware Support
5.16.1
Packet Format
5.16.1.1
Arbitrary Length Field Configuration
5.16.1.2
Packet Length > 255
5.16.2
Packet Filtering in Receive Mode
5.16.2.1
Address Filtering
5.16.2.2
Maximum Length Filtering
5.16.2.3
CRC Filtering
5.16.3
Packet Handling in Transmit Mode
5.16.4
Packet Handling in Receive Mode
5.16.5
Packet Handling in Firmware
5.17
Modulation Formats
5.17.1
Frequency Shift Keying
5.17.2
Amplitude Modulation
5.18
Received Signal Qualifiers and RSSI
5.18.1
Sync Word Qualifier
5.18.2
RSSI
5.18.3
Carrier Sense (CS)
5.18.3.1
CS Absolute Threshold
5.18.3.2
CS Relative Threshold
5.18.4
Clear Channel Assessment (CCA)
5.19
Radio Control
5.19.1
Power-On Start-Up Sequence
5.19.1.1
Automatic POR
5.19.1.2
Manual Reset
5.19.2
Crystal Control
5.19.3
Voltage Regulator Control
5.19.4
Active Modes (RX and TX)
5.19.5
RX Termination
5.19.6
Timing
5.19.6.1
Overall State Transition Times
5.19.6.2
Frequency Synthesizer Calibration Time
5.20
Data FIFO
5.21
Frequency Programming
5.22
VCO
5.22.1
VCO and PLL Self-Calibration
5.23
Voltage Regulators
5.24
Output Power Programming
5.25
General Purpose and Test Output Control Pins
5.26
Asynchronous and Synchronous Serial Operation
5.26.1
Asynchronous Serial Operation
5.26.2
Synchronous Serial Operation
5.27
System Considerations and Guidelines
5.27.1
SRD Regulations
5.27.2
Frequency Hopping and Multi-Channel Systems
5.27.3
Wideband Modulation when not Using Spread Spectrum
5.27.4
Data Burst Transmissions
5.27.5
Continuous Transmissions
5.27.6
Increasing Range
5.28
Configuration Registers
5.28.1
Configuration Register Details - Registers with preserved values in SLEEP state
5.28.2
Configuration Register Details - Registers that Loose Programming in SLEEP State
5.28.3
Status Register Details
5.29
Development Kit Ordering Information
6
Applications, Implementation, and Layout
6.1
Bias Resistor
6.2
Balun and RF Matching
6.3
Crystal
6.4
Reference Signal
6.5
Additional Filtering
6.6
Power Supply Decoupling
6.7
PCB Layout Recommendations
7
Device and Documentation Support
7.1
Device Support
7.1.1
Device Nomenclature
7.2
Documentation Support
7.2.1
Related Documentation from Texas Instruments
7.2.2
Community Resources
7.3
Trademarks
7.4
Electrostatic Discharge Caution
7.5
Export Control Notice
7.6
Glossary
7.7
Additional Acronyms
8
Mechanical Packaging and Orderable Information
8.1
Packaging Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
RGP|20
MPQF126G
Thermal pad, mechanical data (Package|Pins)
RGP|20
QFND856
Orderable Information
swrs109c_oa
swrs109c_pm
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