CC2541-Q1 SimpleLink Bluetooth Low Energy Wireless MCU for Automotive
- SWRS128 June 2014 CC2541-Q1
  
  PRODUCTION DATA.

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DATA SHEET

CC2541-Q1 SimpleLink Bluetooth Low Energy Wireless MCU for Automotive

1 Device Overview

1.1 Features

RF
- 2.4-GHz Bluetooth Low Energy Compliant and Proprietary RF Wireless MCU
- Supports Data Rates of 250 kbps, 500 kbps, 1 Mbps, and 2 Mbps
- Excellent Link Budget, Enabling Long-Range Applications Without External Front End
- Programmable Output Power up to 0 dBm
- Excellent Receiver Sensitivity (–94 dBm at
  1 Mbps), Selectivity, and Blocking Performance
- Suitable for Systems Targeting Compliance With Worldwide Radio Frequency Regulations: ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
Layout
- Few External Components
- 6 mm × 6 mm QFN-40 Package
Low Power
- Active-Mode RX Down to: 18.3 mA
- Active-Mode TX (0 dBm): 18.6 mA
- Power Mode 1 (4-µs Wake-Up): 270 µA
- Power Mode 2 (Sleep Timer On): 1 µA
- Power Mode 3 (External Interrupts): 0.5 µA
- Wide Supply-Voltage Range (2 V to 3.6 V)
Microcontroller
- High-Performance and Low-Power 8051 Microcontroller Core With Code Prefetch
- 256KB In-System Programmable Flash
- 8KB of RAM With Retention in All Power Modes
- Hardware Debug Support
- Extensive Baseband Automation, Including Auto-Acknowledgment and Address Decoding
- Retention of All Relevant Registers in All Power Modes
Peripherals
- Powerful Five-Channel DMA
- IR Generation Circuitry
- General-Purpose Timers (One 16-Bit, Two 8-Bit)
- 32-kHz Sleep Timer With Capture
- Accurate Digital RSSI Support
- Battery Monitor and Temperature Sensor
- 12-Bit ADC With Eight Channels and Configurable Resolution
- AES Security Coprocessor
- Two Powerful USARTs With Support for Several Serial Protocols
- 23 General-Purpose I/O Pins
  (21 × 4 mA, 2 × 20 mA)
- I²C interface
- 2 I/O Pins Have LED Driving Capabilities
- Watchdog Timer
- Integrated High-Performance Comparator
Development Tools
- CC2541 Evaluation Module
- SmartRF™ Software
- IAR Embedded Workbench™ Available
Bluetooth v4.0 Compliant Protocol Stack for Single-Mode BLE Solution
- Complete Power-Optimized Stack, Including Controller and Host
  - GAP – Central, Peripheral, Observer, or Broadcaster (Including Combination Roles)
  - ATT / GATT – Client and Server
  - SMP – AES-128 Encryption and Decryption
  - L2CAP
- Sample Applications and Profiles
  - Generic Applications for GAP Central and Peripheral Roles
  - Proximity, Accelerometer, Simple Keys, and Battery GATT Services
  - More Applications Supported in BLE Software Stack
- Multiple Configuration Options
  - Single-Chip Configuration, Allowing Applications to Run on CC2541-Q1
  - Network Processor Interface for Applications Running on an External Microcontroller
- BTool–Windows PC Application for Evaluation, Development, and Test
- Over the Air Update Capable

1.2 Applications

2.4-GHz Bluetooth Low-Energy Systems
Proprietary 2.4-GHz Systems
Keyless Entry (Passive and Remote)
Tire Pressure Monitoring
Proximity Sensing
Interface and Control
Diagnostics and Maintenance
Cable Replacement
Sensor Nodes
Infotainment and Media
Smart Phone Connectivity
Beacons

1.3 Description

The CC2541-Q1 is a power-optimized true Wireless MCU solution for both Bluetooth low energy and proprietary 2.4-GHz applications. This device enables the building of robust nework nodes with low total bill-of-material costs. The CC2541-Q1 combines the excellent performance of a leading RF transceiver with an industry-standard enhanced 8051 MCU, in-system programmable flash memory, 8KB of RAM, and many other powerful supporting features and peripherals. The CC2541-Q1 is highly suited for systems in which ultralow power consumption is required, which is specified by various operating modes. Short transition times between operating modes further enable low power consumption.

The CC2541-Q1 comes in a 6 mm x 6 mm QFN40 package.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE
CC2541F256TRHARQ1	RHA (40)	6.00 mm × 6.00 mm
CC2541F256TRHATQ1	RHA (40)	6.00 mm × 6.00 mm

(1) For more information, see Section 8, Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

Figure 1-1 shows the CC2541-Q1 block diagram.

Figure 1-1 Block Diagram

2 Revision History

DATE	REVISION	NOTES
June 2014	*	Initial release.

3 Terminal Configuration and Functions

The CC2541-Q1 pinout is shown in Figure 3-1 and a short description of the pins follows.

3.1 Pin Diagram

The exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip.

Figure 3-1 RHA PACKAGE (TOP VIEW)

3.2 Pin Descriptions

Table 3-1 Pin Descriptions

PINS		TYPE	DESCRIPTION
NAME	NO.	TYPE	DESCRIPTION
AVDD1	28	Power (analog)	2-V–3.6-V analog power-supply connection
AVDD2	27	Power (analog)	2-V–3.6-V analog power-supply connection
AVDD3	24	Power (analog)	2-V–3.6-V analog power-supply connection
AVDD4	29	Power (analog)	2-V–3.6-V analog power-supply connection
AVDD5	21	Power (analog)	2-V–3.6-V analog power-supply connection
AVDD6	31	Power (analog)	2-V–3.6-V analog power-supply connection
DCOUPL	40	Power (digital)	1.8-V digital power-supply decoupling. Do not use for supplying external circuits.
DVDD1	39	Power (digital)	2-V–3.6-V digital power-supply connection
DVDD2	10	Power (digital)	2-V–3.6-V digital power-supply connection
GND	1	Ground pin	Connect to GND
GND	—	Ground	The ground pad must be connected to a solid ground plane.
GND	4	Ground pin	Connect to GND
P0_0	19	Digital I/O	Port 0.0
P0_1	18	Digital I/O	Port 0.1
P0_2	17	Digital I/O	Port 0.2
P0_3	16	Digital I/O	Port 0.3
P0_4	15	Digital I/O	Port 0.4
P0_5	14	Digital I/O	Port 0.5
P0_6	13	Digital I/O	Port 0.6
P0_7	12	Digital I/O	Port 0.7
P1_0	11	Digital I/O	Port 1.0 – 20-mA drive capability
P1_1	9	Digital I/O	Port 1.1 – 20-mA drive capability
P1_2	8	Digital I/O	Port 1.2
P1_3	7	Digital I/O	Port 1.3
P1_4	6	Digital I/O	Port 1.4
P1_5	5	Digital I/O	Port 1.5
P1_6	38	Digital I/O	Port 1.6
P1_7	37	Digital I/O	Port 1.7
P2_0	36	Digital I/O	Port 2.0
P2_1/DD	35	Digital I/O	Port 2.1 / debug data
P2_2/DC	34	Digital I/O	Port 2.2 / debug clock
P2_3/ OSC32K_Q2	33	Digital I/O, Analog I/O	Port 2.3/32.768 kHz XOSC
P2_4/ OSC32K_Q1	32	Digital I/O, Analog I/O	Port 2.4/32.768 kHz XOSC
RBIAS	30	Analog I/O	External precision bias resistor for reference current
RESET_N	20	Digital input	Reset, active-low
RF_N	26	RF I/O	Negative RF input signal to LNA during RX Negative RF output signal from PA during TX
RF_P	25	RF I/O	Positive RF input signal to LNA during RX Positive RF output signal from PA during TX
SCL	2	I²C clock or digital I/O	Can be used as I²C clock pin or digital I/O. Leave floating if not used. If grounded disable pull up
SDA	3	I²C clock or digital I/O	Can be used as I²C data pin or digital I/O. Leave floating if not used. If grounded disable pull up
XOSC_Q1	22	Analog I/O	32-MHz crystal oscillator pin 1 or external clock input
XOSC_Q2	23	Analog I/O	32-MHz crystal oscillator pin 2

4 Specifications

4.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Supply voltage	All supply pins must have the same voltage	–0.3	3.9	V
Voltage on any digital pin		–0.3	VDD + 0.3 ≤ 3.9	V
Input RF level			10	dBm

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

4.2 Handling Ratings

				MIN	MAX	UNIT
T_stg	Storage temperature range			–40	125	°C
V_ESD	Electrostatic discharge (ESD) performance:	Human Body Model (HBM), per AEC Q100-002⁽¹⁾	All pins	–1	1	kV
		Human Body Model (HBM), per AEC Q100-002⁽¹⁾	All pins (Excluding pins 25 and 26)	–2	2	kV
		Charged Device Model (CDM), per AEC Q100-011		–500	500	V

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	NOM	MAX	UNIT
Operating ambient temperature range, T_A	–40		105	°C
Operating supply voltage	2		3.6	V

4.4 Thermal Characteristics for RHA Package

NAME	DESCRIPTION	°C/W
RΘ_JC	Junction-to-case (top)	16.1
RΘ_JB	Junction-to-board	5.5
RΘ_JA	Junction-to-free air	30.6
Psi_JT	Junction-to-package top	0.2
Psi_JB	Junction-to-board	5.4
Rθ_JC	Junction-to-case (bottom)	1.0

(1) m/s = meters per second

4.5 Electrical Characteristics

Measured on Texas Instruments CC2541-Q1 EM reference design with T_A = 25°C and VDD = 3 V,
1 Mbps, GFSK, 250-kHz deviation, Bluetooth low energy mode, and 0.1% BER

PARAMETER		TEST CONDITIONS	TYP	UNIT
I_core	Core current consumption	RX mode, standard mode, no peripherals active, low MCU activity	18.3	mA
		RX mode, high-gain mode, no peripherals active, low MCU activity	20.8
		TX mode, –20 dBm output power, no peripherals active, low MCU activity	17.2
		TX mode, 0 dBm output power, no peripherals active, low MCU activity	18.6
		Power mode 1. Digital regulator on; 16-MHz RCOSC and 32-MHz crystal oscillator off; 32.768-kHz XOSC, POR, BOD and sleep timer active; RAM and register retention	270	µA
		Power mode 2. Digital regulator off; 16-MHz RCOSC and 32-MHz crystal oscillator off; 32.768-kHz XOSC, POR, and sleep timer active; RAM and register retention	1
		Power mode 3. Digital regulator off; no clocks; POR active; RAM and register retention	0.5
		Low MCU activity: 32-MHz XOSC running. No radio or peripherals. Limited flash access, no RAM access.	6.7	mA
I_peri	Peripheral current consumption (Adds to core current I_core for each peripheral unit activated)	Timer 1. Timer running, 32-MHz XOSC used	90	μA
		Timer 2. Timer running, 32-MHz XOSC used	90
		Timer 3. Timer running, 32-MHz XOSC used	60
		Timer 4. Timer running, 32-MHz XOSC used	70
		Sleep timer, including 32.753-kHz RCOSC	0.6
		ADC, when converting	1.2	mA

4.6 General Characteristics

Measured on Texas Instruments CC2541-Q1 EM reference design with T_A = 25°C and VDD = 3 V

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
WAKE-UP AND TIMING
Power mode 1 → Active	Digital regulator on, 16-MHz RCOSC and 32-MHz crystal oscillator off. Start-up of 16-MHz RCOSC		4		μs
Power mode 2 or 3 → Active	Digital regulator off, 16-MHz RCOSC and 32-MHz crystal oscillator off. Start-up of regulator and 16-MHz RCOSC		120		μs
Active → TX or RX	Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC, with 32-MHz XOSC OFF		500		μs
Active → TX or RX	With 32-MHz XOSC initially on		180		μs
RX/TX turnaround	Proprietary auto mode		130		μs
RX/TX turnaround	BLE mode		150		μs
RADIO PART
RF frequency range	Programmable in 1-MHz steps	2379		2496	MHz
Data rate and modulation format	2 Mbps, GFSK, 500-kHz deviation 2 Mbps, GFSK, 320-kHz deviation 1 Mbps, GFSK, 250-kHz deviation 1 Mbps, GFSK, 160-kHz deviation 500 kbps, MSK 250 kbps, GFSK, 160-kHz deviation 250 kbps, MSK

4.7 RF Receive Section

Measured on Texas Instruments CC2541-Q1 EM reference design with T_A = 25°C, VDD = 3 V, f_c = 2440 MHz

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
1 Mbps, GFSK, 250-kHz Deviation, Bluetooth low energy Mode, 0.1% BER
Receiver sensitivity⁽³⁾⁽⁴⁾	High-gain mode		–94		dBm
Receiver sensitivity⁽³⁾⁽⁴⁾	Standard mode		–88		dBm
Saturation⁽⁴⁾	BER < 0.1%		5		dBm
Co-channel rejection⁽⁴⁾	Wanted signal –67 dBm		–6		dB
In-band blocking rejection⁽⁴⁾	±1 MHz offset, 0.1% BER, wanted signal –67 dBm		–2		dB
	±2 MHz offset, 0.1% BER, wanted signal –67 dBm		26
	±3 MHz offset, 0.1% BER, wanted signal –67 dBm		34
	>6 MHz offset, 0.1% BER, wanted signal –67 dBm		33
Out-of-band blocking rejection⁽⁴⁾	Minimum interferer level < 2 GHz (Wanted signal –67 dBm)		–21		dBm
	Minimum interferer level [2 GHz, 3 GHz] (Wanted signal –67 dBm)		–27
	Minimum interferer level > 3 GHz (Wanted signal –67 dBm)		–8
Intermodulation⁽⁴⁾	Minimum interferer level		–36		dBm
Frequency error tolerance⁽¹⁾	Including both initial tolerance and drift. Sensitivity better than -67dBm, 250 byte payload. BER 0.1%	–250		250	kHz
Symbol rate error tolerance⁽²⁾	Maximum packet length. Sensitivity better than –67 dBm, 250 byte payload. BER 0.1%	–80		80	ppm
ALL RATES/FORMATS
Spurious emission in RX. Conducted measurement	f < 1 GHz		–67		dBm
Spurious emission in RX. Conducted measurement	f > 1 GHz		–57		dBm

(1) Difference between center frequency of the received RF signal and local oscillator frequency

(2) Difference between incoming symbol rate and the internally generated symbol rate

(3) The receiver sensitivity setting is programmable using a TI BLE stack vendor-specific API command. The default value is standard mode.

(4) Results based on standard-gain mode.

4.8 RF Transmit Section

Measured on Texas Instruments CC2541-Q1 EM reference design with T_A = 25°C, VDD = 3 V and f_c = 2440 MHz

PARAMETER	TEST CONDITIONS	TYP	UNIT
Output power	Delivered to a single-ended 50-Ω load through a balun using maximum recommended output power setting	0	dBm
Output power	Delivered to a single-ended 50-Ω load through a balun using minimum recommended output power setting	–20	dBm
Programmable output power range	Delivered to a single-ended 50-Ω load through a balun using minimum recommended output power setting	20	dB
Spurious emission conducted measurement	f < 1 GHz	–52	dBm
	f > 1 GHz	–48	dBm
	Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
Optimum load impedance	Differential impedance as seen from the RF port (RF_P and RF_N) toward the antenna	70 +j30	Ω

Designs with antenna connectors that require conducted ETSI compliance at 64 MHz should insert an LC resonator in front of the antenna connector. Use a 1.6-nH inductor in parallel with a 1.8-pF capacitor. Connect both from the signal trace to a good RF ground.

4.9 32-MHz Crystal Oscillator

Measured on Texas Instruments CC2541-Q1 EM reference design with T_A = 25°C and VDD = 3 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Crystal frequency			32		MHz
	Crystal frequency accuracy requirement⁽¹⁾		–40		40	ppm
ESR	Equivalent series resistance		6		60	Ω
C₀	Crystal shunt capacitance		1		7	pF
C_L	Crystal load capacitance		10		16	pF
	Start-up time			0.25		ms
	Power-down guard time	The crystal oscillator must be in power down for a guard time before it is used again. This requirement is valid for all modes of operation. The need for power-down guard time can vary with crystal type and load.	3			ms

(1) Including aging and temperature dependency, as specified by [1]

4.10 32.768-kHz Crystal Oscillator

Measured on Texas Instruments CC2541-Q1 EM reference design with T_A = 25°C and VDD = 3 V

PARAMETER		MIN	TYP	MAX	UNIT
	Crystal frequency		32.768		kHz
	Crystal frequency accuracy requirement⁽¹⁾	–40		40	ppm
ESR	Equivalent series resistance		40	130	kΩ
C₀	Crystal shunt capacitance		0.9	2	pF
C_L	Crystal load capacitance		12	16	pF
	Start-up time		0.4		s

4.11 32-kHz RC Oscillator

Measured on Texas Instruments CC2541-Q1 EM reference design with T_A = 25°C and VDD = 3 V.

PARAMETER	TYP	UNIT
Calibrated frequency⁽¹⁾	32.753	kHz
Frequency accuracy after calibration	±0.2%
Temperature coefficient⁽²⁾	0.4	%/°C
Supply-voltage coefficient⁽³⁾	3	%/V
Calibration time⁽⁴⁾	2	ms

(1) The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.

(2) Frequency drift when temperature changes after calibration

(3) Frequency drift when supply voltage changes after calibration

(4) When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator is performed while SLEEPCMD.OSC32K_CALDIS is set to 0.

4.12 16-MHz RC Oscillator

Measured on Texas Instruments CC2541-Q1 EM reference design with T_A = 25°C and VDD = 3 V

PARAMETER	TYP	UNIT
Frequency⁽¹⁾	16	MHz
Uncalibrated frequency accuracy	±18%
Calibrated frequency accuracy	±0.6%
Start-up time	10	μs
Initial calibration time⁽²⁾	50	μs

(1) The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.

(2) When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator is performed while SLEEPCMD.OSC_PD is set to 0.

4.13 RSSI Characteristics

Measured on Texas Instruments CC2541-Q1 EM reference design with T_A = 25°C and VDD = 3 V

PARAMETER	TEST CONDITIONS	TYP	UNIT
2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
Useful RSSI range⁽¹⁾	Reduced gain by AGC algorithm	64	dB
Useful RSSI range⁽¹⁾	High gain by AGC algorithm	64	dB
RSSI offset⁽¹⁾	Reduced gain by AGC algorithm	79	dBm
RSSI offset⁽¹⁾	High gain by AGC algorithm	99	dBm
Absolute uncalibrated accuracy⁽¹⁾		±6	dB
Step size (LSB value)		1	dB
All Other Rates/Formats
Useful RSSI range⁽¹⁾	Standard mode	64	dB
Useful RSSI range⁽¹⁾	High-gain mode	64	dB
RSSI offset⁽¹⁾	Standard mode	98	dBm
RSSI offset⁽¹⁾	High-gain mode	107	dBm
Absolute uncalibrated accuracy⁽¹⁾		±3	dB
Step size (LSB value)		1	dB

(1) Assuming CC2541-Q1 EM reference design. Other RF designs give an offset from the reported value.

4.14 Frequency Synthesizer Characteristics

Measured on Texas Instruments CC2541-Q1 EM reference design with T_A = 25°C, VDD = 3 V and f_c = 2440 MHz

PARAMETER	TEST CONDITIONS	TYP	UNIT
Phase noise, unmodulated carrier	At ±1-MHz offset from carrier	–109	dBc/Hz
	At ±3-MHz offset from carrier	–112
	At ±5-MHz offset from carrier	–119

4.15 Analog Temperature Sensor

Measured on Texas Instruments CC2541-Q1 EM reference design with T_A = 25°C and VDD = 3 V

PARAMETER	TEST CONDITIONS	TYP	UNIT
Output	Measured using integrated ADC, internal band-gap voltage reference, and maximum resolution	1480	12-bit
Temperature coefficient		4.5	/ 1°C
Voltage coefficient		1	0.1 V
Initial accuracy without calibration		±10	°C
Accuracy using 1-point calibration		±5	°C
Current consumption when enabled		0.5	mA

4.16 Comparator Characteristics

T_A = 25°C, VDD = 3 V. All measurement results are obtained using the CC2541-Q1 reference designs, post-calibration.

	TYP	UNIT
Common-mode maximum voltage	VDD	V
Common-mode minimum voltage	–0.3
Input offset voltage	1	mV
Offset vs temperature	16	µV/°C
Offset vs operating voltage	4	mV/V
Supply current	230	nA
Hysteresis	0.15	mV

4.17 ADC Characteristics

T_A = 25°C and VDD = 3 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Input voltage	VDD is voltage on AVDD5 pin	0		VDD	V
	External reference voltage	VDD is voltage on AVDD5 pin	0		VDD	V
	External reference voltage differential	VDD is voltage on AVDD5 pin	0		VDD	V
	Input resistance, signal	Simulated using 4-MHz clock speed		197		kΩ
	Full-scale signal⁽¹⁾	Peak-to-peak, defines 0 dBFS		2.97		V
ENOB⁽¹⁾	Effective number of bits	Single-ended input, 7-bit setting		5.7		bits
		Single-ended input, 9-bit setting		7.5
		Single-ended input, 10-bit setting		9.3
		Single-ended input, 12-bit setting		10.3
		Differential input, 7-bit setting		6.5
		Differential input, 9-bit setting		8.3
		Differential input, 10-bit setting		10
		Differential input, 12-bit setting		11.5
		10-bit setting, clocked by RCOSC		9.7
		12-bit setting, clocked by RCOSC		10.9
	Useful power bandwidth	7-bit setting, both single and differential		0–20		kHz
THD	Total harmonic distortion	Single ended input, 12-bit setting, –6 dBFS⁽¹⁾		–75.2		dB
THD	Total harmonic distortion	Differential input, 12-bit setting, –6 dBFS⁽¹⁾		–86.6		dB
	Signal to nonharmonic ratio	Single-ended input, 12-bit setting⁽¹⁾		70.2		dB
		Differential input, 12-bit setting⁽¹⁾		79.3
		Single-ended input, 12-bit setting, –6 dBFS⁽¹⁾		78.8
		Differential input, 12-bit setting, –6 dBFS⁽¹⁾		88.9
CMRR	Common-mode rejection ratio	Differential input, 12-bit setting, 1-kHz sine (0 dBFS), limited by ADC resolution		>84		dB
	Crosstalk	Single ended input, 12-bit setting, 1-kHz sine (0 dBFS), limited by ADC resolution		>84		dB
	Offset	Midscale		–3		mV
	Gain error			0.68%
DNL	Differential nonlinearity	12-bit setting, mean⁽¹⁾		0.05		LSB
DNL	Differential nonlinearity	12-bit setting, maximum⁽¹⁾		0.9		LSB
INL	Integral nonlinearity	12-bit setting, mean⁽¹⁾		4.6		LSB
		12-bit setting, maximum⁽¹⁾		13.3
		12-bit setting, mean, clocked by RCOSC		10
		12-bit setting, max, clocked by RCOSC		29
SINAD (–THD+N)	Signal-to-noise-and-distortion	Single ended input, 7-bit setting⁽¹⁾		35.4		dB
		Single ended input, 9-bit setting⁽¹⁾		46.8
		Single ended input, 10-bit setting⁽¹⁾		57.5
		Single ended input, 12-bit setting⁽¹⁾		66.6
		Differential input, 7-bit setting⁽¹⁾		40.7
		Differential input, 9-bit setting⁽¹⁾		51.6
		Differential input, 10-bit setting⁽¹⁾		61.8
		Differential input, 12-bit setting⁽¹⁾		70.8
	Conversion time	7-bit setting		20		μs
		9-bit setting		36
		10-bit setting		68
		12-bit setting		132
	Power consumption			1.2		mA
	Internal reference VDD coefficient			4		mV/V
	Internal reference temperature coefficient			0.4		mV/10°C
	Internal reference voltage			1.24		V

(1) Measured with 300-Hz sine-wave input and VDD as reference.

4.18 DC Characteristics

T_A = 25°C, VDD = 3 V

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Logic-0 input voltage				0.5	V
Logic-1 input voltage		2.4			V
Logic-0 input current	Input equals 0 V	–50		50	nA
Logic-1 input current	Input equals VDD	–50		50	nA
I/O-pin pullup and pulldown resistors			20		kΩ
Logic-0 output voltage, 4- mA pins	Output load 4 mA			0.5	V
Logic-1 output voltage, 4-mA pins	Output load 4 mA	2.5			V
Logic-0 output voltage, 20- mA pins	Output load 20 mA			0.5	V
Logic-1 output voltage, 20-mA pins	Output load 20 mA	2.5			V

4.19 Control Input AC Characteristics

T_A = –40°C to 105°C, VDD = 2 V to 3.6 V

PARAMETER	TEST CONDITIONS	MIN	MAX	UNIT
System clock, f_SYSCLK t_SYSCLK = 1/ f_SYSCLK	The undivided system clock is 32 MHz when crystal oscillator is used. The undivided system clock is 16 MHz when calibrated 16-MHz RC oscillator is used.	16	32	MHz
RESET_N low duration	See item 1, Figure 4-1. This is the shortest pulse that is recognized as a complete reset pin request. Note that shorter pulses may be recognized but do not lead to complete reset of all modules within the chip.	1		µs
Interrupt pulse duration	See item 2, Figure 4-1.This is the shortest pulse that is recognized as an interrupt request.	20		ns

Figure 4-1 Control Input AC Characteristics

4.20 SPI AC Characteristics

T_A = –40°C to 105°C, VDD = 2 V to 3.6 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t₁	SCK period	Master, RX and TX	250			ns
t₁	SCK period	Slave, RX and TX	250			ns
	SCK duty cycle	Master		50%
t₂	SSN low to SCK	Master	63			ns
t₂	SSN low to SCK	Slave	63			ns
t₃	SCK to SSN high	Master	63			ns
t₃	SCK to SSN high	Slave	63			ns
t₄	MOSI early out	Master, load = 10 pF			7	ns
t₅	MOSI late out	Master, load = 10 pF			10	ns
t₆	MISO setup	Master	90			ns
t₇	MISO hold	Master	10			ns
	SCK duty cycle	Slave		50%		ns
t₁₀	MOSI setup	Slave	35			ns
t₁₁	MOSI hold	Slave	10			ns
t₉	MISO late out	Slave, load = 10 pF			95	ns
	Operating frequency	Master, TX only			8	MHz
		Master, RX and TX			4
		Slave, RX only			8
		Slave, RX and TX			4

Figure 4-2 SPI Master AC Characteristics

Figure 4-3 SPI Slave AC Characteristics

4.21 Debug Interface AC Characteristics

T_A = –40°C to 105°C, VDD = 2 V to 3.6 V

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
f_{clk_dbg}	Debug clock frequency (see Figure 4-4)			12	MHz
t₁	Allowed high pulse on clock (see Figure 4-4)		35		ns
t₂	Allowed low pulse on clock (see Figure 4-4)		35		ns
t₃	EXT_RESET_N low to first falling edge on debug clock (see Figure 4-6)		167		ns
t₄	Falling edge on clock to EXT_RESET_N high (see Figure 4-6)		83		ns
t₅	EXT_RESET_N high to first debug command (see Figure 4-6)		83		ns
t₆	Debug data setup (see Figure 4-5)		2		ns
t₇	Debug data hold (see Figure 4-5)		4		ns
t₈	Clock-to-data delay (see Figure 4-5)	Load = 10 pF		30	ns

Figure 4-4 Debug Clock – Basic Timing

Figure 4-5 Debug Enable Timing

Figure 4-6 Data Setup and Hold Timing

4.22 Timer Inputs AC Characteristics

T_A = –40°C to 105°C, VDD = 2 V to 3.6 V

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Input capture pulse duration	Synchronizers determine the shortest input pulse that can be recognized. The synchronizers operate at the current system clock rate (16 MHz or 32 MHz).	1.5			t_SYSCLK

4.23 Typical Characteristics

Figure 4-7 RX Current vs Temperature

Figure 4-9 RX Sensitivity vs Temperature

Figure 4-11 RX Current vs Supply Voltage

	1-Mbps GFSK 250-kHz Standard Gain Setting
	T_A = 25°C

Figure 4-13 RX Sensitivity vs Supply Voltage

	1-Mbps GFSK 250-kHz Standard Gain Setting
	T_A = 25°C
	V_cc = 3 V

Figure 4-15 RX Sensitivity vs Frequency

Figure 4-8 TX Current vs Temperature

Figure 4-10 TX Power vs Temperature

Figure 4-12 TX Current vs Supply Voltage

	TX Power Setting = 0 dBm
	T_A = 25°C

Figure 4-14 TX Power vs Supply Voltage

	TX Power Setting = 0 dBm
	T_A = 25°C
	V_cc = 3 V

Figure 4-16 TX Power vs Frequency

Table 4-1 Output Power⁽¹⁾⁽²⁾

TX POWER Setting	Typical Output Power (dBm)
0xE1	0
0xD1	–2
0xC1	–4
0xB1	–6
0xA1	–8
0x91	–10
0x81	–12
0x71	–14
0x61	–16
0x51	–18
0x41	–20

(1) Measured on Texas Instruments CC2541-Q1 EM reference design with T_A = 25°C, VDD = 3 V and f_c = 2440 MHz. See SWRU191 for recommended register settings.

(2) 1 Mbsp, GFSK, 250-kHz deviation, Bluetooth low energy mode, 1% BER