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DAC3484 四通道 16 位 1.25GSPS 数模转换器 (DAC)
ZHCS072E
March 2011 – November 2015
DAC3484
PRODUCTION DATA.
CONTENTS
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DAC3484 四通道 16 位 1.25GSPS 数模转换器 (DAC)
1
特性
2
应用范围
3
说明
4
修订历史记录
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal InformationZAY package information to Thermal InformationTJ row from top of thermal table
6.5
Electrical Characteristics - DC Specifications
6.6
Electrical Characteristics - Digital Specifications
6.7
Electrical Characteristics - AC Specifications
6.8
Timing Requirements - Digital Specifications
6.9
Switching Characteristics - AC Specifications
6.10
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Serial Interface
7.3.2
Data Interface
7.3.2.1
Word-Wide Format
7.3.2.2
Byte-Wide Format
7.3.3
Input FIFO
7.3.4
FIFO Modes of Operation
7.3.4.1
Dual Sync Sources Mode
7.3.4.2
Single Sync Source Mode
7.3.4.3
Bypass Mode
7.3.5
Clocking Modes
7.3.5.1
PLL Bypass Mode
7.3.5.2
PLL Mode
7.3.6
FIR Filters
7.3.7
Complex Signal Mixer
7.3.7.1
Full Complex Mixer
7.3.7.2
Coarse Complex Mixer
7.3.7.3
Mixer Gain
7.3.7.4
Real Channel Upconversion
7.3.8
Quadrature Modulation Correction (QMC)
7.3.8.1
Gain and Phase Correction
7.3.8.2
Offset Correction
7.3.8.3
Group Delay Correction
7.3.9
Temperature Sensor
7.3.10
Data Pattern Checker
7.3.11
Parity Check Test
7.3.11.1
Word-by-Word Parity
7.3.11.2
Block Parity
7.3.12
DAC3484 Alarm Monitoring
7.3.13
LVPECL Inputs
7.3.14
LVDS Inputs
7.3.15
Unused LVDS Port Termination
7.3.16
CMOS Digital Inputs
7.3.17
Reference Operation
7.3.18
DAC Transfer Function
7.3.19
Analog Current Outputs
7.4
Device Functional Modes
7.4.1
Multi-Device Synchronization
7.4.1.1
Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
7.4.1.2
Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
7.4.1.3
Multi-Device Operation: Single Sync Source Mode
7.5
Programming
7.5.1
Power-Up Sequence
7.5.2
Example Start-Up Routine
7.5.2.1
Device Configuration
7.5.2.2
PLL Configuration
7.5.2.3
NCO Configuration
7.5.2.4
Example Start-Up Sequence
7.6
Register Map
7.6.1
Register Descriptions
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
IF Based LTE Transmitter
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Data Input Rate
8.2.1.2.2
Interpolation
8.2.1.2.3
LO Feedthrough and Sideband Correction
8.2.1.3
Application Curves
8.2.2
Direct Upconversion (Zero IF) LTE Transmitter
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.2.1
Data Input Rate
8.2.2.2.2
Interpolation
8.2.2.2.3
LO Feedthrough and Sideband Correction
8.2.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.1.1
Assembly
10.2
Layout Examples
11
器件和文档支持
11.1
器件支持
11.1.1
Third-Party Products Disclaimer
11.1.2
器件命名规则
11.1.2.1
技术参数定义
11.2
文档支持
11.2.1
相关文档
11.3
社区资源
11.4
商标
11.5
静电放电警告
11.6
Glossary
12
机械、封装和可订购信息
重要声明
封装选项
机械数据 (封装 | 引脚)
RKD|88
MPQF242
ZAY|196
MPBGAL1
散热焊盘机械数据 (封装 | 引脚)
RKD|88
QFND211A
订购信息
zhcs072e_oa
zhcs072e_pm
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