OPA2333-HT 1.8-V Micropower CMOS Operational Amplifier Zero-Drift Series
1 Features
- Low Offset Voltage: 26 μV (Maximum)
- 0.01-Hz to 10-Hz Noise: 1.5 μVPP
- Quiescent Current: 50 μA
- Single-Supply Operation
- Supply Voltage: 1.8 V to 5.5 V
- Rail-to-Rail Input and Output
- Supports Extreme Temperature Applications
- Controlled Baseline
- One Assembly/Test Site
- One Fabrication Site
- Available in Extreme (–55°C to 210°C) Temperature Range
- Extended Product Life Cycle
- Extended Product-Change Notification
- Product Traceability
- Texas Instruments' high temperature products use highly optimized silicon (die) solutions with design and process enhancements to maximize performance over extended temperatures.
2 Applications
- Down-Hole Drilling
- High Temperature Environments
3 Description
The OPA2333 series of CMOS operational amplifiers uses a proprietary auto-calibration technique to simultaneously provide very low offset voltage and near-zero drift over time and temperature(1). These miniature, high-precision, low-quiescent-current amplifiers offer high-impedance inputs that have a common-mode range 100 mV beyond the rails, and rail-to-rail output that swings within 150 mV of the rails. Single or dual supplies as low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V) may be used. They are optimized for low-voltage single-supply operation.
The OPA2333 offers excellent common-mode rejection ratio (CMRR) without the crossover associated with traditional complementary input stages. This design results in superior performance for driving analog-to-digital converters (ADCs) without degradation of differential linearity.
Device Information(2)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| OPA2333-HT | SOIC (8) | 4.90 mm × 3.91 mm |
| CFP (8) | 6.90 mm × 5.65 mm | |
| CFP (8) | 7.035 mm × 5.75 mm | |
| CDIP SB (8) | 18.55 mm × 7.49 mm |
- See Electrical Characteristics for
performance degradation over temperature. - For all available packages, see the orderable addendum at the end of the data sheet.
Typical Application
4 Revision History
Changes from H Revision (November 2013) to I Revision
- Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
- Removed Ordering Information table Go
- Moved temperature range from Electrical Characteristics table to the Absolute Maximum Ratings and Recommended Operating Conditions tables Go
Changes from G Revision (September 2012) to H Revision
- Changed Operating Life Derating ChartGo
5 Pin Configuration and Functions
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | OUT A | O | Analog output channel A |
| 2 | –IN A | I | Inverting analog input channel A |
| 3 | +IN A | I | Noninverting analog input channel A |
| 5 | +IN B | I | Noninverting analog input channel B |
| 6 | –IN B | I | Inverting analog input channel B |
| 4 | V– | — | Negative (lowest) power supply |
| 7 | OUT B | O | Analog output channel B |
| 8 | V+ | — | Positive (highest) power supply |
Table 1. Bare Die Information
| DIE THICKNESS | BACKSIDE FINISH | BACKSIDE POTENTIAL |
BOND PAD METALLIZATION COMPOSITION |
|---|---|---|---|
| 15 mils. | Silicon with backgrind | V- | Al-Si-Cu (0.5%) |
Table 2. Bond Pad Coordinates
| DESCRIPTION | PAD NUMBER | A | B | C | D |
|---|---|---|---|---|---|
| OUT A | 1 | 21.20 | 1288.50 | 97.20 | 1364.50 |
| –IN A | 2 | 21.20 | 923.65 | 97.20 | 999.65 |
| +IN A | 3 | 21.20 | 533.05 | 97.20 | 609.05 |
| V– | 4 | 31.30 | 172.20 | 107.30 | 248.20 |
| +IN B | 5 | 864.80 | 162.25 | 940.80 | 238.25 |
| –IN B | 6 | 864.80 | 552.65 | 940.80 | 628.65 |
| OUT B | 7 | 864.80 | 897.10 | 940.80 | 973.10 |
| V+ | 8 | 854.70 | 1280.45 | 930.70 | 1356.45 |
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply voltage | 7 | V | ||
| Signal input terminals, voltage(2) | –0.3 | (V+) + 0.3 | V | |
| Output short circuit(3) | Continuous | |||
| Operating temperature | JD, HKJ, HKQ packages | –55 | 210 | °C |
| D package | –55 | 175 | ||
| Junction temperature | JD, HKJ, HKQ packages | 210 | °C | |
| D package | 175 | |||
| Storage temperature, Tstg | –65 | 210 | °C | |
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| Supply voltage, VS = (V+) – (V–) | 1.8 (±0.9) | 5 (±2.5) | 5.5 (±2.75) | V | |
| Operating temperature | JD, HKJ, HKQ packages | –55 | 210 | °C | |
| D package | –55 | 175 | |||
6.4 Thermal Information
| THERMAL METRIC(1) | OPA2333-HT | UNIT | |||||
|---|---|---|---|---|---|---|---|
| JD (CDIP SB) |
HKJ (CFP) |
HKQ (CFP) |
D (SOIC) |
||||
| 8 PINS | 8 PINS | 8 PINS | 8 PINS | ||||
| RθJA | Junction-to-ambient thermal resistance(2) | High-K board(3), no airflow | — | — | — | 117.5 | °C/W |
| No airflow | — | — | — | — | |||
| RθJC(top) | Junction-to-case (top) thermal resistance | 53.8 | 57.7 | 62.0 | °C/W | ||
| to ceramic side of case | — | — | 15.2 | — | |||
| to top of case lid (metal side of case) | — | — | — | — | |||
| RθJB | Junction-to-board thermal resistance | High-K board without underfill | 76.0 | 61.0 | 151.6 | 57.7 | °C/W |
| ψJT | Junction-to-top characterization parameter | — | — | — | 19.4 | °C/W | |
| ψJB | Junction-to-board characterization parameter | — | — | — | 57.2 | °C/W | |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 26.7 | 15.2 | 56.9 | — | °C/W | |
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
6.5 Electrical Characteristics
VS = 1.8 V to 5.5 V, TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2 (unless otherwise noted).| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| OFFSET VOLTAGE | |||||||
| VOS | Input offset voltage | VS = 5 V | TA = 25°C | 2 | 10 | μV | |
| TA = –55°C to 125°C | 22 | ||||||
| TA = –55°C to 175°C(1) | 26 | ||||||
| TA = –55°C to 210°C(2) | 26 | μV | |||||
| dVOS/dT | Input Offset Voltage Temperature Drift | VS = 5 V | TA = –55°C to 125°C | 0.02 | μV/°C | ||
| TA = –55°C to 175°C(1) | 0.05 | ||||||
| TA = –55°C to 210°C(2) | 0.05 | ||||||
| PSRR | Input Offset Voltage vs Power Supply | VS = 1.8 V to 5.5 V | TA = –55°C to 125°C | 1 | 6 | μV/V | |
| TA = –55°C to 175°C(1) | 1.2 | 8 | |||||
| TA = –55°C to 210°C(2) | 1.7 | 11 | |||||
| INPUT BIAS CURRENT | |||||||
| IB | Input bias current | TA = 25°C | ±70 | ±200 | pA | ||
| TA = –55°C to 125°C | ±150 | ||||||
| TA = –55°C to 175°C | ±1250 | ||||||
| TA = –55°C to 210°C | ±5300 | ||||||
| IOS | Input offset current | TA = –55°C to 125°C | ±140 | ±400 | pA | ||
| TA = –55°C to 175°C | ±700 | ||||||
| TA = –55°C to 210°C | ±10600 | ||||||
| NOISE | |||||||
| Input Noise Voltage | f = 0.01 Hz to 1 Hz | TA = –55°C to 125°C | 0.3 | μVPP | |||
| TA = –55°C to 175°C(1) | 1 | ||||||
| TA = –55°C to 210°C(2) | 1 | ||||||
| f = 0.1 Hz to 10 Hz | TA = –55°C to 125°C | 1.1 | μVPP | ||||
| TA = –55°C to 175°C(1) | 1.5 | ||||||
| TA = –55°C to 210°C(2) | 1.5 | ||||||
| in | Input Noise Current Density | f = 10 Hz | TA = 25°C | 100 | fA/√Hz | ||
| INPUT VOLTAGE RANGE(3) | |||||||
| VCM | Common mode voltage range | TA = –55°C to 125°C | (V–) – 0.1 | (V+) + 0.1 | V | ||
| TA = –55°C to 175°C | (V–) – 0.25 | (V+) + 0.25 | |||||
| TA = –55°C to 210°C | (V–) – 0.25 | (V+) + 0.25 | |||||
| CMRR | Common-Mode Rejection Ratio | (V–) – 0.1 V < VCM < (V+) + 0.1 V | TA = –55°C to 125°C | 102 | 130 | dB | |
| TA = –55°C to 175°C | 101 | ||||||
| TA = –55°C to 210°C | 91 | ||||||
| INPUT CAPACITANCE | |||||||
| Differential | TA = –55°C to 125°C | 2 | pF | ||||
| TA = –55°C to 175°C | 4.25 | ||||||
| TA = –55°C to 210°C | 4.25 | ||||||
| Common mode | TA = –55°C to 125°C | 4 | pF | ||||
| TA = –55°C to 175°C | 12.25 | ||||||
| TA = –55°C to 210°C | 12.25 | ||||||
| OPEN-LOOP GAIN | |||||||
| AOL | Open-loop voltage gain | (V–) + 100 mV < VO < (V+) – 100 mV, RL = 10 kΩ | TA = –55°C to 125°C | 104 | 130 | dB | |
| TA = –55°C to 175°C(1) | 93 | 110 | |||||
| TA = –55°C to 210°C(2) | 85 | 93 | |||||
| FREQUENCY RESPONSE | |||||||
| GBW | Gain-bandwidth product | CL = 100 pF | TA = –55°C to 125°C | 350 | kHz | ||
| TA = –55°C to 175°C | 350 | ||||||
| TA = –55°C to 210°C | 350 | ||||||
| SR | Slew rate | G = 1 | TA = –55°C to 125°C | 0.16 | V/μs | ||
| TA = –55°C to 175°C | 0.25 | ||||||
| TA = –55°C to 210°C | 0.25 | ||||||
| OUTPUT | |||||||
| Voltage output swing from rail | RL = 10 kΩ | TA = 25°C | 30 | 50 | mV | ||
| TA = –55°C to 125°C | 85 | ||||||
| TA = –55°C to 175°C(1) | 110 | ||||||
| TA = –55°C to 210°C(2) | 150 | ||||||
| ISC | Short-circuit current | TA = 25°C | ±5 | mA | |||
| Open-loop output impedance(4) | f = 350 kHz, IO = 0 | 2 | kΩ | ||||
| POWER SUPPLY | |||||||
| VS | Specified voltage range | TA = –55°C to 210°C(2) | 1.8 | 5.5 | V | ||
| IQ | Quiescent current per amplifier | IO = 0 | TA = 25°C | 17 | 25 | μA | |
| TA = –55°C to 125°C | 30 | ||||||
| TA = –55°C to 175°C(1) | 35 | 40 | |||||
| TA = –55°C to 210°C(2) | 50 | 80 | |||||
| Turnon time | VS = 5 V | TA = 25°C | 100 | μs | |||
6.6 Typical Characteristics
At TA = 25°C, VS = 5 V, and CL = 0 pF (unless otherwise noted).
Figure 2. Offset Voltage Production Distribution
Figure 4. Open−Loop Gain vs Frequency
Figure 6. PSRR vs Frequency
Figure 8. Input Bias Current vs Common−Mode Voltage
Figure 10. Quiescent Current vs Temperature
Figure 12. Small−Signal Step Response
Figure 14. Negative Overvoltage Recovery
Figure 16. Small−Signal Overshoot vs Load Capacitance
Figure 18. Current and Voltage Noise Spectral Density vs Frequency
Figure 3. Offset Voltage Drift Production Distribution
Figure 5. CMMR vs Frequency
Figure 7. Output Voltage Swing vs Output Current
Figure 9. Input Bias Current vs Temperature
Figure 11. Large−Signal Step Response
Figure 13. Positive Overvoltage Recovery
Figure 15. Settling Time vs Closed−Loop Gain
Figure 17. 0.1-Hz to 10-Hz Noise
7 Detailed Description
7.1 Overview
The OPA2333 is a Zero-Drift, low-power, rail-to-rail input and output dual operational amplifier. The device operates from 1.8 V to 5.5 V, is unity-gain stable, and is suitable for a wide range of general-purpose applications. The Zero-Drift architecture provides low offset voltage and near zero offset voltage drift.
7.2 Functional Block Diagrams
Figure 19. Functional Block Diagram for A and B Amps
7.3 Feature Description
The OPA2333 is unity-gain stable and free from unexpected output phase reversal. It uses a proprietary auto-calibration technique to provide low offset voltage and very low drift over time and temperature. For lowest offset voltage and precision performance, circuit layout and mechanical conditions should be optimized. Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by ensuring they are equal on both input terminals. Other layout and design considerations include: (1)
- Use low thermoelectric-coefficient conditions (avoid dissimilar metals)
- Thermally isolate components from power supplies or other heat sources
- Shield operational amplifier and input circuitry from air currents, such as cooling fans
Following these guidelines will reduce the likelihood of junctions being at different temperatures, which can cause thermoelectric voltages of 0.1 μV/°C or higher, depending on materials used.
7.3.1 Operating Voltage
The OPA2333 operational amplifier operates over a power-supply range of 1.8 V to 5.5 V (±0.9 V to
±2.75 V). Supply voltages higher than 7 V (absolute maximum) can permanently damage the device. Parameters that vary over supply voltage or temperature are shown in Typical Characteristics.
7.3.2 Input Voltage
The OPA2333 input common-mode voltage range extends 0.1 V beyond the supply rails. The OPA2333 is designed to cover the full range without the troublesome transition region found in some other rail-to-rail amplifiers.
Normally, input bias current is about 70 pA; however, input voltages exceeding the power supplies can cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input resistor (see Figure 20).
7.3.3 Internal Offset Correction
The OPA2333 operational amplifier uses an auto-calibration technique with a time-continuous 350-kHz operational amplifier in the signal path. This amplifier is zero corrected every 8 μs using a proprietary technique. Upon power up, the amplifier requires approximately 100 μs to achieve specified VOS accuracy. This design has no aliasing or flicker noise.
7.3.4 Achieving Output Swing to the Operational Amplifier Negative Rail
Some applications require output voltage swings from 0 V to a positive full-scale voltage (such as 2.5 V) with excellent accuracy. With most single-supply operational amplifiers, problems arise when the output signal approaches 0 V, near the lower output swing limit of a single-supply operational amplifier. A good single-supply operational amplifier may swing close to single-supply ground, but will not reach ground. The output of the OPA2333 can be made to swing to ground, or slightly below, on a single-supply power source. To do so requires the use of another resistor and an additional, more negative, power supply than the operational amplifier negative supply. A pulldown resistor may be connected between the output and the additional negative supply to pull the output down below the value that the output would otherwise achieve (see Figure 21).
Figure 21. VOUT Range to Ground
The OPA2333 has an output stage that allows the output voltage to be pulled to its negative supply rail, or slightly below, using the technique previously described. This technique only works with some types of output stages. The OPA2333 has been characterized to perform with this technique; however, the recommended resistor value is approximately 20 kΩ.
NOTE
This configuration will increase the current consumption by several hundreds of microamps.
Accuracy is excellent down to 0 V and as low as –2 mV. Limiting and nonlinearity occurs below –2 mV, but excellent accuracy returns as the output is again driven above –2 mV. Lowering the resistance of the pulldown resistor allows the operational amplifier to swing even further below the negative rail. Resistances as low as 10 kΩ can be used to achieve excellent accuracy down to –10 mV.
7.4 Device Functional Modes
The OPA2333 device has a single functional mode. The device is powered on as long as the power supply voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA2333 family is a unity-gain stable, precision operational amplifier with very low offset voltage drift; these devices are also free from output phase reversal. Applications with noisy or high-impedance power supplies require decoupling capacitors close to the device power-supply pins. In most cases, 0.1-μF capacitors are adequate.
8.2 Typical Applications
8.2.1 High-Side Voltage-to-Current (V-I) Converter
The circuit shown in Figure 22 is a high-side voltage-to-current (V-I) converter. It translates in input voltage of 0 V to 2 V to and output current of 0 mA to 100 mA. Figure 23 shows the measured transfer function for this circuit. The low offset voltage and offset drift of the OPA2333 facilitate excellent dc accuracy for the circuit.
Figure 22. High-Side Voltage-to-Current (V-I) Converter
8.2.1.1 Design Requirements
The design requirements are as follows:
- Supply Voltage: 5-V DC
- Input: 0-V to 2-V DC
- Output: 0-mA to 10-mA DC
8.2.1.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, and the three current sensing resistors, RS1, RS2, and RS3. The relationship between VIN and RS1 determines the current that flows through the first stage of the design. The current gain from the first stage to the second stage is based on the relationship between RS2 and RS3.
For a successful design, pay close attention to the DC characteristics of the operational amplifier chosen for the application. To meet the performance goals, this application benefits from an operational amplifier with low offset voltage, low temperature drift, and rail-to-rail output. The OPA2333 CMOS operational amplifier is a high-precision, 5-µV offset, 0.05-μV/°C drift amplifier optimized for low-voltage, single-supply operation with an output swing to within 50 mV of the positive rail. The OPA2333 family uses chopping techniques to provide low initial offset voltage and near-zero drift over time and temperature. Low offset voltage and low drift reduce the offset error in the system, making these devices appropriate for precise DC control. The rail-to-rail output stage of the OPA2333 ensures that the output swing of the operational amplifier is able to fully control the gate of the MOSFET devices within the supply rails.
See TIPD102 for a detailed error analysis, design procedure, and additional measured results.
8.2.1.3 Application Curve
Figure 23. Measured Transfer Function for High-Side V-I Converter
8.2.2 Precision, Low-Level Voltage-to-Current (V-I) Converter
The circuit shown in Figure 24 is a precision, low-level voltage-to-current (V-I) converter. The converter translates in input voltage of 0 V to 5 V and output current of 0 µA to 5 µA. Figure 25 shows the measured transfer function for this circuit. The low offset voltage and offset drift of the OPA2333 facilitate excellent dc accuracy for the circuit. Figure 26 shows the calibrated error for the entire range of the circuit.
Figure 24. Low-Level, Precision V-I Converter
8.2.2.1 Design Requirements
The design requirements are as follows:
- Supply Voltage: 5-V DC
- Input: 0-V to 5-V DC
- Output: 0-μA to 5-μA DC
8.2.2.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, RSET, and the instrumentation amplifier (INA) gain. During operation, the input voltage divided by the INA gain appears across the set resistor in Equation 1:
The current through RSET must flow through the load, so IOUT is VSET / RSET. IOUT remains a well-regulated current as long as the total voltage across RSET and RLOAD does not violate the output limits of the operational amplifier or the input common-mode limits of the INA. The voltage across the set resistor (VSET) is the input voltage divided by the INA gain (that is, VSET = 1 V / 10 = 0.1 V). The current is determined by VSET and RSET shown in Equation 2:
See TIPD107 for a detailed error analysis, design procedure, and additional measured results.
8.2.2.3 Application Curves
Figure 25. Measured Transfer Function for Low-Level Precision V-I
Figure 26. Calibrated Output Error for Low-Level V-I
8.2.3 Composite Amplifier
The circuit shown in Figure 27 is a composite amplifier used to drive the reference on the ADS8881. The OPA2333 provides excellent dc accuracy, and the THS4281 allows the output of the circuit to respond quickly to the transient current requirements of a typical SAR data converter reference input. The ADS8881 system was optimized for THD and achieved a measured performance of –110 dB. The linearity of the ADC is shown Figure 28.
Figure 27. Composite Amplifier Reference Driver Circuit
8.2.3.1 Design Requirements
The design requirements for this block design are:
- System Supply Voltage: 5-V DC
- ADC Supply Voltage: 3.3-V DC
- ADC Sampling Rate: 1 MSPS
- ADC Reference Voltage (VREF): 4.5-V DC
- ADC Input Signal: A differential input signal with amplitude of Vpk = 4.315 V (–0.4 dBFS to avoid clipping) and frequency, fIN = 10 kHz are applied to each differential input of the ADC
8.2.3.2 Detailed Design Procedure
The two primary design considerations to maximize the performance of a high-resolution SAR ADC are the input driver and the reference driver design. The circuit comprises the critical analog circuit blocks, the input driver, anti-aliasing filter, and the reference driver. Each analog circuit block should be carefully designed based on the ADC performance specifications in order to maximize the distortion and noise performance of the data acquisition system while consuming low power. The diagram includes the most important specifications for each individual analog block. This design systematically approaches the design of each analog circuit block to achieve a 16-bit, low-noise and low-distortion data acquisition system for a 10-kHz sinusoidal input signal. The first step in the design requires an understanding of the requirement of extremely low distortion input driver amplifier. This understanding helps in the decision of an appropriate input driver configuration and selection of an input amplifier to meet the system requirements. The next important step is the design of the anti-aliasing RC-filter to attenuate ADC kick-back noise while maintaining the amplifier stability. The final design challenge is to design a high-precision reference driver circuit, which would provide the required value VREF with low offset, drift, and noise contributions.
In designing a very low distortion data acquisition block, it is important to understand the sources of nonlinearity. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. To achieve the lowest distortion, the input driver for a high-performance SAR ADC must have a distortion that is negligible against the ADC distortion. This parameter requires the input driver distortion to be 10 dB lower than the ADC THD. This stringent requirement ensures that overall THD of the system is not degraded by more than –0.5 dB.
It is therefore important to choose an amplifier that meets the above criteria to avoid the system THD from being limited by the input driver. The amplifier nonlinearity in a feedback system depends on the available loop gain. See TIPD115 for a detailed error analysis, design procedure, and additional measured results.
8.2.3.3 Application Curve
Figure 28. Linearity of the ADC8881 System
8.3 System Examples
8.3.1 Temperature Measurement Application
Figure 29 shows a temperature measurement application.
Figure 29. Temperature Measurementf
8.3.2 Single Operational Amplifier Bridge Amplifier Application
Figure 30 shows the basic configuration for a bridge amplifier.
Figure 30. Single Operational Amplifier Bridge Amplifier
8.3.3 Low-Side Current Monitor Application
A low-side current shunt monitor is shown in Figure 31. RN are operational resistors used to isolate the ADS1100 from the noise of the digital I2C bus. The ADS1100 is a 16-bit converter; therefore, a precise reference is essential for maximum accuracy. If absolute accuracy is not required and the 5-V power supply is sufficiently stable, the REF3130 can be omitted.
NOTE:
1% resistors provide adequate common-mode rejection at small ground-loop errors.8.3.4 Other Applications
Additional application ideas are shown in Figure 32 through Figure 35.
Figure 33. Thermistor Measurement
Figure 34. Precision Instrumentation Amplifier
9 Power Supply Recommendations
The OPA2333 is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply from –40°C to 125°C. The Recommended Operating Conditions presents parameters that can exhibit significant variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute Maximum Ratings).
TI recommends placing 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, see Layout.
10 Layout
10.1 Layout Guidelines
10.1.1 General Layout Guidelines
Pay attention to good layout practices. Keep traces short and when possible, use a printed-circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-μF capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility.
Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified as a variation in offset voltage or DC signal levels with changes in the interfering RF signal. The OPA2333 is specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to previous generation devices. Strong RF fields may still cause varying offset levels.
10.1.2 DFN Layout Guidelines
Solder the exposed leadframe die pad on the DFN package to a thermal pad on the PCB. A mechanical drawing showing an example layout is attached at the end of this data sheet. Refinements to this layout may be necessary based on assembly process requirements. Mechanical drawings located at the end of this data sheet list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are intended for use with thermal vias that connect the leadframe die pad to the heatsink area on the PCB.
Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push, package shear, and similar board-level tests. Even with applications that have low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.
10.2 Layout Example
Figure 36. OPA2333-HT Layout Example
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For development support on this product, see the following:
- High-Side V-I Converter, 0 V to 2 V to 0 mA to 100 mA, 1% Full-Scale Error, TIPD102
- Low-Level V-to-I Converter Reference Design, 0-V to 5-V Input to 0-µA to 5-µA Output, TIPD107
- 18-Bit, 1-MSPS, Serial Interface, microPower, Truly-Differential Input, SAR ADC, ADS8881
- Very Low-Power, High-Speed, Rail-To-Rail Input/Output, Voltage Feedback Operational Amplifier, THS4281
- Data Acquisition Optimized for Lowest Distortion, Lowest Noise, 18-bit, 1-MSPS Reference Design, TIPD115
- Self-Calibrating, 16-Bit Analog-to-Digital Converter, ADS1100
- 20-ppm/Degrees C Max, 100-µA, SOT23-3 Series Voltage Reference, REF3130
- Precision, Low Drift, CMOS Instrumentation Amplifier, INA326, INA326
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
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11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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