ZHCS810H
January 2012 – February 2018
DS125DF410
PRODUCTION DATA.
1
特性
2
应用
3
说明
典型应用图
4
修订历史记录
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Device Data Path Operation
7.3.2
Signal Detect
7.3.3
CTLE
7.3.4
DFE
7.3.5
Clock and Data Recovery
7.3.6
Output Driver
7.3.7
Device Configuration
7.3.7.1
Rate and Subrate Setting
7.4
Device Functional Modes
7.4.1
SMBus Master Mode and SMBus Slave Mode
7.4.2
Address Lines <ADDR_[3:0]>
7.4.3
SDA and SDC
7.4.4
Standards-Based Modes
7.4.4.1
Ref_mode 3 Mode (Reference Clock Required)
7.4.4.2
False Lock Detector Setting
7.4.4.3
Reference Clock In
7.4.4.4
Reference Clock Out
7.4.4.5
Driver Output Voltage
7.4.4.6
Driver Output De-Emphasis
7.4.4.7
Driver Output Rise/Fall Time
7.4.4.8
INT
7.4.4.9
LOCK_3, LOCK_2, LOCK_1, and LOCK_0
7.5
Programming
7.5.1
SMBus Strap Observation
7.5.2
Device Revision and Device ID
7.5.3
Control/Shared Register Reset
7.5.4
Interrupt Channel Flag Bits
7.5.5
SMBus Master Mode Control Bits
7.5.6
Resetting Individual Channels of the Retimer
7.5.7
Interrupt Status
7.5.8
Overriding the CTLE Boost Setting
7.5.9
Overriding the VCO Search Values
7.5.10
Overriding the Output Multiplexer
7.5.11
Overriding the VCO Divider Selection
7.5.12
Using the PRBS Generator
7.5.13
Using the Internal Eye Opening Monitor
7.5.14
Overriding the DFE Tap Weights and Polarities
7.5.15
Enabling Slow Rise/Fall Time on the Output Driver
7.5.16
Inverting the Output Polarity
7.5.17
Overriding the Figure of Merit for Adaptation
7.5.18
Setting the Rate and Subrate for Lock Acquisition
7.5.19
Setting the Adaptation/Lock Mode
7.5.20
Initiating Adaptation
7.5.21
Setting the Reference Enable Mode
7.5.22
Overriding the CTLE Settings Used for CTLE Adaptation
7.5.23
Setting the Output Differential Voltage
7.5.24
Setting the Output De-Emphasis Setting
7.6
Register Maps
7.6.1
Register Information
7.6.2
Bit Fields in the Register Set
7.6.3
Writing to and Reading from the Control/Shared Registers
7.6.4
Channel Select Register
7.6.5
Reading to and Writing from the Channel Registers
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
器件和文档支持
11.1
文档支持
11.1.1
相关文档
11.2
商标
11.3
静电放电警告
11.4
Glossary
12
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
RHS|48
MPQF159B
散热焊盘机械数据 (封装 | 引脚)
RHS|48
QFND509A
订购信息
zhcs810h_oa
zhcs810h_pm
1
特性
每个通道独立锁定到 9.8 至 12.5Gbps 的数据速率和约数
基于协议选择模式的快速锁定操作
低延迟(约 300ps)
具有自适应均衡功能,可在 5GHz 频率下提供最高 34dB 的升压
可调节的发送 V
OD
:600 至 1300mVp-p
可调节发送去加重功能:最高达 -15dB
典型功耗 (EQ + DFE + CDR + DE):每通道 180mW
可编程的输出极性反转
输入信号检测,CDR 锁定检测/指示器
片上眼图监视器 (EOM),伪随机二进制序列 (PRBS) 发生器
2.5V±5% 单电源
系统管理总线 (SMbus)/EEPROM 配置模式
工作温度范围为 -40°C 至 85°C
48 引脚 7mm x 7mm 超薄四方扁平无引线 (WQFN) 封装
可轻松在中继器与重定时器之间进行引脚兼容升级
DS100RT410 (EQ + CDR + DE):10.3125Gbps
DS100DF410 (EQ + DFE + CDR + DE):10.3125Gbps
DS110RT410 (EQ + CDR + DE):8.5–11.3Gbps
DS110DF410 (EQ + DFE + CDR + DE):8.5–11.3Gbps
DS125RT410 (EQ + CDR + DE):9.8–12.5Gbps
DS125DF410 (EQ + DFE + CDR + DE):9.8–12.5Gbps
DS100BR410 (EQ + DE):最高为 10.3125Gbps