ZHCSKE8D
March 2016 – October 2019
DS250DF410
PRODUCTION DATA.
1
特性
2
应用
3
说明
Device Images
简化原理图
4
修订历史记录
5
说明 (续)
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements, Retimer Jitter Specifications
7.7
Timing Requirements, Retimer Specifications
7.8
Timing Requirements, Recommended Calibration Clock Specifications
7.9
Recommended SMBus Switching Characteristics (Slave Mode)
7.10
Recommended SMBus Switching Characteristics (Master Mode)
7.11
Recommended JTAG Switching Characteristics
7.12
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Device Data Path Operation
8.3.2
Signal Detect
8.3.3
Continuous Time Linear Equalizer (CTLE)
8.3.4
Variable Gain Amplifier (VGA)
8.3.5
Cross-Point Switch
8.3.6
Decision Feedback Equalizer (DFE)
8.3.7
Clock and Data Recovery (CDR)
8.3.8
Calibration Clock
8.3.9
Differential Driver with FIR Filter
8.3.9.1
Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
8.3.9.2
Output Driver Polarity Inversion
8.3.10
Debug Features
8.3.10.1
Pattern Generator
8.3.10.2
Pattern Checker
8.3.10.3
Eye Opening Monitor
8.3.11
Interrupt Signals
8.3.12
JTAG Boundary Scan
8.4
Device Functional Modes
8.4.1
Supported Data Rates
8.4.2
SMBus Master Mode
8.4.3
Device SMBus Address
8.5
Programming
8.5.1
Bit Fields in the Register Set
8.5.2
Writing to and Reading from the Global/Shared/Channel Registers
8.6
Register Maps
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Front-Port Jitter Cleaning Applications
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
Active Cable Applications
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.3
Application Curves
9.2.3
Backplane and Mid-plane Applications
9.2.3.1
Design Requirements
9.2.3.2
Detailed Design Procedure
9.2.3.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
器件和文档支持
12.1
文档支持
12.1.1
开发支持
12.2
文档支持
12.2.1
相关文档
12.3
接收文档更新通知
12.4
支持资源
12.5
商标
12.6
静电放电警告
12.7
Glossary
13
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
ABM|101
MPBGAL0A
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcske8d_oa
zhcske8d_pm
1
特性
具有集成信号调节功能的四通道多速率重定时器
所有通道均可独立锁定在 20.2752 至 25.8Gbps 的范围内(包括 10.3125Gbps、12.5Gbps 等子速率)
超低延迟:25.78125Gbps 数据速率下的典型延迟 < 500ps
单电源,无需低抖动参考时钟,最大限度减少电源去耦以降低电路板布线复杂程度并节省物料清单 (BOM) 成本
集成 2×2 交叉点
自适应性连续时间线性均衡器 (CTLE)
自适应判决反馈均衡器 (DFE)
带有 3 抽头有限冲激响应 (FIR) 滤波器的低抖动发射器
组合式均衡,在 12.9GHz 频率下支持 35dB 以上的通道损耗
可调节发送幅值:205mVppd 至 1225mVppd(典型值)
片上眼图张开度监视器 (EOM),PRBS 模式校验器/发生器
支持 JTAG/AC-JTAG 边界扫描
小型 6mm × 6mm BGA 封装,可轻松实现直通布线